2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
55 /* register offsets */
56 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
57 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
58 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
59 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
60 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
61 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
62 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
63 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
64 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
65 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
66 PDC_FLASH_CTL = 0x44, /* Flash control register */
67 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
68 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
69 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
70 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
71 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
72 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
75 (1<<8) | (1<<9) | (1<<10),
77 board_2037x = 0, /* FastTrak S150 TX2plus */
78 board_20319 = 1, /* FastTrak S150 TX4 */
79 board_20619 = 2, /* FastTrak TX4000 */
80 board_2057x = 3, /* SATAII150 Tx2plus */
81 board_40518 = 4, /* SATAII150 Tx4 */
83 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
85 /* Sequence counter control registers bit definitions */
86 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
88 /* Feature register values */
89 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
90 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
92 /* Device/Head register values */
93 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
95 /* PDC_CTLSTAT bit definitions */
96 PDC_DMA_ENABLE = (1 << 7),
97 PDC_IRQ_DISABLE = (1 << 10),
98 PDC_RESET = (1 << 11), /* HDMA reset */
100 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
102 ATA_FLAG_PIO_POLLING,
105 PDC_FLAG_GEN_II = (1 << 0),
109 struct pdc_port_priv {
114 struct pdc_host_priv {
116 unsigned long port_flags[ATA_MAX_PORTS];
119 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
120 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
121 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
122 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
123 static void pdc_eng_timeout(struct ata_port *ap);
124 static int pdc_port_start(struct ata_port *ap);
125 static void pdc_pata_phy_reset(struct ata_port *ap);
126 static void pdc_qc_prep(struct ata_queued_cmd *qc);
127 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
129 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
130 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
131 static void pdc_irq_clear(struct ata_port *ap);
132 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
133 static void pdc_freeze(struct ata_port *ap);
134 static void pdc_thaw(struct ata_port *ap);
135 static void pdc_error_handler(struct ata_port *ap);
136 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
139 static struct scsi_host_template pdc_ata_sht = {
140 .module = THIS_MODULE,
142 .ioctl = ata_scsi_ioctl,
143 .queuecommand = ata_scsi_queuecmd,
144 .can_queue = ATA_DEF_QUEUE,
145 .this_id = ATA_SHT_THIS_ID,
146 .sg_tablesize = LIBATA_MAX_PRD,
147 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
148 .emulated = ATA_SHT_EMULATED,
149 .use_clustering = ATA_SHT_USE_CLUSTERING,
150 .proc_name = DRV_NAME,
151 .dma_boundary = ATA_DMA_BOUNDARY,
152 .slave_configure = ata_scsi_slave_config,
153 .slave_destroy = ata_scsi_slave_destroy,
154 .bios_param = ata_std_bios_param,
157 static const struct ata_port_operations pdc_sata_ops = {
158 .port_disable = ata_port_disable,
159 .tf_load = pdc_tf_load_mmio,
160 .tf_read = ata_tf_read,
161 .check_status = ata_check_status,
162 .exec_command = pdc_exec_command_mmio,
163 .dev_select = ata_std_dev_select,
164 .check_atapi_dma = pdc_check_atapi_dma,
166 .qc_prep = pdc_qc_prep,
167 .qc_issue = pdc_qc_issue_prot,
168 .freeze = pdc_freeze,
170 .error_handler = pdc_error_handler,
171 .post_internal_cmd = pdc_post_internal_cmd,
172 .data_xfer = ata_data_xfer,
173 .irq_handler = pdc_interrupt,
174 .irq_clear = pdc_irq_clear,
176 .scr_read = pdc_sata_scr_read,
177 .scr_write = pdc_sata_scr_write,
178 .port_start = pdc_port_start,
181 /* First-generation chips need a more restrictive ->check_atapi_dma op */
182 static const struct ata_port_operations pdc_old_sata_ops = {
183 .port_disable = ata_port_disable,
184 .tf_load = pdc_tf_load_mmio,
185 .tf_read = ata_tf_read,
186 .check_status = ata_check_status,
187 .exec_command = pdc_exec_command_mmio,
188 .dev_select = ata_std_dev_select,
189 .check_atapi_dma = pdc_old_check_atapi_dma,
191 .qc_prep = pdc_qc_prep,
192 .qc_issue = pdc_qc_issue_prot,
193 .freeze = pdc_freeze,
195 .error_handler = pdc_error_handler,
196 .post_internal_cmd = pdc_post_internal_cmd,
197 .data_xfer = ata_data_xfer,
198 .irq_handler = pdc_interrupt,
199 .irq_clear = pdc_irq_clear,
201 .scr_read = pdc_sata_scr_read,
202 .scr_write = pdc_sata_scr_write,
203 .port_start = pdc_port_start,
206 static const struct ata_port_operations pdc_pata_ops = {
207 .port_disable = ata_port_disable,
208 .tf_load = pdc_tf_load_mmio,
209 .tf_read = ata_tf_read,
210 .check_status = ata_check_status,
211 .exec_command = pdc_exec_command_mmio,
212 .dev_select = ata_std_dev_select,
213 .check_atapi_dma = pdc_check_atapi_dma,
215 .phy_reset = pdc_pata_phy_reset,
217 .qc_prep = pdc_qc_prep,
218 .qc_issue = pdc_qc_issue_prot,
219 .data_xfer = ata_data_xfer,
220 .eng_timeout = pdc_eng_timeout,
221 .irq_handler = pdc_interrupt,
222 .irq_clear = pdc_irq_clear,
224 .port_start = pdc_port_start,
227 static const struct ata_port_info pdc_port_info[] = {
231 .flags = PDC_COMMON_FLAGS,
232 .pio_mask = 0x1f, /* pio0-4 */
233 .mwdma_mask = 0x07, /* mwdma0-2 */
234 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
235 .port_ops = &pdc_old_sata_ops,
241 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
242 .pio_mask = 0x1f, /* pio0-4 */
243 .mwdma_mask = 0x07, /* mwdma0-2 */
244 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
245 .port_ops = &pdc_old_sata_ops,
251 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
252 .pio_mask = 0x1f, /* pio0-4 */
253 .mwdma_mask = 0x07, /* mwdma0-2 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &pdc_pata_ops,
261 .flags = PDC_COMMON_FLAGS,
262 .pio_mask = 0x1f, /* pio0-4 */
263 .mwdma_mask = 0x07, /* mwdma0-2 */
264 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
265 .port_ops = &pdc_sata_ops,
271 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
272 .pio_mask = 0x1f, /* pio0-4 */
273 .mwdma_mask = 0x07, /* mwdma0-2 */
274 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
275 .port_ops = &pdc_sata_ops,
279 static const struct pci_device_id pdc_ata_pci_tbl[] = {
280 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
281 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
282 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
283 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
284 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
285 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
286 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
287 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
288 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
292 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
293 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
294 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
295 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
296 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
298 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
300 { } /* terminate list */
304 static struct pci_driver pdc_ata_pci_driver = {
306 .id_table = pdc_ata_pci_tbl,
307 .probe = pdc_ata_init_one,
308 .remove = ata_pci_remove_one,
312 static int pdc_port_start(struct ata_port *ap)
314 struct device *dev = ap->host->dev;
315 struct pdc_host_priv *hp = ap->host->private_data;
316 struct pdc_port_priv *pp;
319 /* fix up port flags and cable type for SATA+PATA chips */
320 ap->flags |= hp->port_flags[ap->port_no];
321 if (ap->flags & ATA_FLAG_SATA)
322 ap->cbl = ATA_CBL_SATA;
324 rc = ata_port_start(ap);
328 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
332 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
336 ap->private_data = pp;
338 /* fix up PHYMODE4 align timing */
339 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
340 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
343 tmp = readl(mmio + 0x014);
344 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
345 writel(tmp, mmio + 0x014);
351 static void pdc_reset_port(struct ata_port *ap)
353 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
357 for (i = 11; i > 0; i--) {
370 readl(mmio); /* flush */
373 static void pdc_pata_cbl_detect(struct ata_port *ap)
376 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
381 ap->cbl = ATA_CBL_PATA40;
382 ap->udma_mask &= ATA_UDMA_MASK_40C;
384 ap->cbl = ATA_CBL_PATA80;
387 static void pdc_pata_phy_reset(struct ata_port *ap)
389 pdc_pata_cbl_detect(ap);
395 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
397 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
399 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
403 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
406 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
408 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
411 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
413 struct ata_port *ap = qc->ap;
414 dma_addr_t sg_table = ap->prd_dma;
415 unsigned int cdb_len = qc->dev->cdb_len;
417 struct pdc_port_priv *pp = ap->private_data;
419 u32 *buf32 = (u32 *) buf;
420 unsigned int dev_sel, feature, nbytes;
422 /* set control bits (byte 0), zero delay seq id (byte 3),
423 * and seq id (byte 2)
425 switch (qc->tf.protocol) {
426 case ATA_PROT_ATAPI_DMA:
427 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
428 buf32[0] = cpu_to_le32(PDC_PKT_READ);
432 case ATA_PROT_ATAPI_NODATA:
433 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
439 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
440 buf32[2] = 0; /* no next-packet */
443 if (sata_scr_valid(ap)) {
444 dev_sel = PDC_DEVICE_SATA;
446 dev_sel = ATA_DEVICE_OBS;
447 if (qc->dev->devno != 0)
450 buf[12] = (1 << 5) | ATA_REG_DEVICE;
452 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
453 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
455 buf[16] = (1 << 5) | ATA_REG_NSECT;
457 buf[18] = (1 << 5) | ATA_REG_LBAL;
460 /* set feature and byte counter registers */
461 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
462 feature = PDC_FEATURE_ATAPI_PIO;
463 /* set byte counter register to real transfer byte count */
468 feature = PDC_FEATURE_ATAPI_DMA;
469 /* set byte counter register to 0 */
472 buf[20] = (1 << 5) | ATA_REG_FEATURE;
474 buf[22] = (1 << 5) | ATA_REG_BYTEL;
475 buf[23] = nbytes & 0xFF;
476 buf[24] = (1 << 5) | ATA_REG_BYTEH;
477 buf[25] = (nbytes >> 8) & 0xFF;
479 /* send ATAPI packet command 0xA0 */
480 buf[26] = (1 << 5) | ATA_REG_CMD;
481 buf[27] = ATA_CMD_PACKET;
483 /* select drive and check DRQ */
484 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
487 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
488 BUG_ON(cdb_len & ~0x1E);
490 /* append the CDB as the final part */
491 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
492 memcpy(buf+31, cdb, cdb_len);
495 static void pdc_qc_prep(struct ata_queued_cmd *qc)
497 struct pdc_port_priv *pp = qc->ap->private_data;
502 switch (qc->tf.protocol) {
507 case ATA_PROT_NODATA:
508 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
509 qc->dev->devno, pp->pkt);
511 if (qc->tf.flags & ATA_TFLAG_LBA48)
512 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
514 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
516 pdc_pkt_footer(&qc->tf, pp->pkt, i);
523 case ATA_PROT_ATAPI_DMA:
526 case ATA_PROT_ATAPI_NODATA:
535 static void pdc_freeze(struct ata_port *ap)
537 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
540 tmp = readl(mmio + PDC_CTLSTAT);
541 tmp |= PDC_IRQ_DISABLE;
542 tmp &= ~PDC_DMA_ENABLE;
543 writel(tmp, mmio + PDC_CTLSTAT);
544 readl(mmio + PDC_CTLSTAT); /* flush */
547 static void pdc_thaw(struct ata_port *ap)
549 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
553 readl(mmio + PDC_INT_SEQMASK);
555 /* turn IRQ back on */
556 tmp = readl(mmio + PDC_CTLSTAT);
557 tmp &= ~PDC_IRQ_DISABLE;
558 writel(tmp, mmio + PDC_CTLSTAT);
559 readl(mmio + PDC_CTLSTAT); /* flush */
562 static void pdc_error_handler(struct ata_port *ap)
564 ata_reset_fn_t hardreset;
566 if (!(ap->pflags & ATA_PFLAG_FROZEN))
570 if (sata_scr_valid(ap))
571 hardreset = sata_std_hardreset;
573 /* perform recovery */
574 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
578 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
580 struct ata_port *ap = qc->ap;
582 if (qc->flags & ATA_QCFLAG_FAILED)
583 qc->err_mask |= AC_ERR_OTHER;
585 /* make DMA engine forget about the failed command */
590 static void pdc_eng_timeout(struct ata_port *ap)
592 struct ata_host *host = ap->host;
594 struct ata_queued_cmd *qc;
599 spin_lock_irqsave(&host->lock, flags);
601 qc = ata_qc_from_tag(ap, ap->active_tag);
603 switch (qc->tf.protocol) {
605 case ATA_PROT_NODATA:
606 ata_port_printk(ap, KERN_ERR, "command timeout\n");
607 drv_stat = ata_wait_idle(ap);
608 qc->err_mask |= __ac_err_mask(drv_stat);
612 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
614 ata_port_printk(ap, KERN_ERR,
615 "unknown timeout, cmd 0x%x stat 0x%x\n",
616 qc->tf.command, drv_stat);
618 qc->err_mask |= ac_err_mask(drv_stat);
622 spin_unlock_irqrestore(&host->lock, flags);
623 ata_eh_qc_complete(qc);
627 static inline unsigned int pdc_host_intr( struct ata_port *ap,
628 struct ata_queued_cmd *qc)
630 unsigned int handled = 0;
632 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
635 if (tmp & PDC_ERR_MASK) {
636 qc->err_mask |= AC_ERR_DEV;
640 switch (qc->tf.protocol) {
642 case ATA_PROT_NODATA:
643 case ATA_PROT_ATAPI_DMA:
644 case ATA_PROT_ATAPI_NODATA:
645 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
651 ap->stats.idle_irq++;
658 static void pdc_irq_clear(struct ata_port *ap)
660 struct ata_host *host = ap->host;
661 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
663 readl(mmio + PDC_INT_SEQMASK);
666 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
668 struct ata_host *host = dev_instance;
672 unsigned int handled = 0;
673 void __iomem *mmio_base;
677 if (!host || !host->iomap[PDC_MMIO_BAR]) {
678 VPRINTK("QUICK EXIT\n");
682 mmio_base = host->iomap[PDC_MMIO_BAR];
684 /* reading should also clear interrupts */
685 mask = readl(mmio_base + PDC_INT_SEQMASK);
687 if (mask == 0xffffffff) {
688 VPRINTK("QUICK EXIT 2\n");
692 spin_lock(&host->lock);
694 mask &= 0xffff; /* only 16 tags possible */
696 VPRINTK("QUICK EXIT 3\n");
700 writel(mask, mmio_base + PDC_INT_SEQMASK);
702 for (i = 0; i < host->n_ports; i++) {
703 VPRINTK("port %u\n", i);
705 tmp = mask & (1 << (i + 1));
707 !(ap->flags & ATA_FLAG_DISABLED)) {
708 struct ata_queued_cmd *qc;
710 qc = ata_qc_from_tag(ap, ap->active_tag);
711 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
712 handled += pdc_host_intr(ap, qc);
719 spin_unlock(&host->lock);
720 return IRQ_RETVAL(handled);
723 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
725 struct ata_port *ap = qc->ap;
726 struct pdc_port_priv *pp = ap->private_data;
727 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
728 unsigned int port_no = ap->port_no;
729 u8 seq = (u8) (port_no + 1);
731 VPRINTK("ENTER, ap %p\n", ap);
733 writel(0x00000001, mmio + (seq * 4));
734 readl(mmio + (seq * 4)); /* flush */
737 wmb(); /* flush PRD, pkt writes */
738 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
739 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
742 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
744 switch (qc->tf.protocol) {
745 case ATA_PROT_ATAPI_NODATA:
746 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
749 case ATA_PROT_ATAPI_DMA:
751 case ATA_PROT_NODATA:
752 pdc_packet_start(qc);
759 return ata_qc_issue_prot(qc);
762 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
764 WARN_ON (tf->protocol == ATA_PROT_DMA ||
765 tf->protocol == ATA_PROT_NODATA);
770 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
772 WARN_ON (tf->protocol == ATA_PROT_DMA ||
773 tf->protocol == ATA_PROT_NODATA);
774 ata_exec_command(ap, tf);
777 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
779 u8 *scsicmd = qc->scsicmd->cmnd;
780 int pio = 1; /* atapi dma off by default */
782 /* Whitelist commands that may use DMA. */
783 switch (scsicmd[0]) {
790 case 0xad: /* READ_DVD_STRUCTURE */
791 case 0xbe: /* READ_CD */
794 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
795 if (scsicmd[0] == WRITE_10) {
797 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
798 if (lba >= 0xFFFF4FA2)
804 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
806 struct ata_port *ap = qc->ap;
808 /* First generation chips cannot use ATAPI DMA on SATA ports */
809 if (sata_scr_valid(ap))
811 return pdc_check_atapi_dma(qc);
814 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
816 port->cmd_addr = base;
817 port->data_addr = base;
819 port->error_addr = base + 0x4;
820 port->nsect_addr = base + 0x8;
821 port->lbal_addr = base + 0xc;
822 port->lbam_addr = base + 0x10;
823 port->lbah_addr = base + 0x14;
824 port->device_addr = base + 0x18;
826 port->status_addr = base + 0x1c;
827 port->altstatus_addr =
828 port->ctl_addr = base + 0x38;
832 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
834 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
835 struct pdc_host_priv *hp = pe->private_data;
839 if (hp->flags & PDC_FLAG_GEN_II)
840 hotplug_offset = PDC2_SATA_PLUG_CSR;
842 hotplug_offset = PDC_SATA_PLUG_CSR;
845 * Except for the hotplug stuff, this is voodoo from the
846 * Promise driver. Label this entire section
847 * "TODO: figure out why we do this"
850 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
851 tmp = readl(mmio + PDC_FLASH_CTL);
852 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
853 if (!(hp->flags & PDC_FLAG_GEN_II))
854 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
855 writel(tmp, mmio + PDC_FLASH_CTL);
857 /* clear plug/unplug flags for all ports */
858 tmp = readl(mmio + hotplug_offset);
859 writel(tmp | 0xff, mmio + hotplug_offset);
861 /* mask plug/unplug ints */
862 tmp = readl(mmio + hotplug_offset);
863 writel(tmp | 0xff0000, mmio + hotplug_offset);
865 /* don't initialise TBG or SLEW on 2nd generation chips */
866 if (hp->flags & PDC_FLAG_GEN_II)
869 /* reduce TBG clock to 133 Mhz. */
870 tmp = readl(mmio + PDC_TBG_MODE);
871 tmp &= ~0x30000; /* clear bit 17, 16*/
872 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
873 writel(tmp, mmio + PDC_TBG_MODE);
875 readl(mmio + PDC_TBG_MODE); /* flush */
878 /* adjust slew rate control register. */
879 tmp = readl(mmio + PDC_SLEW_CTL);
880 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
881 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
882 writel(tmp, mmio + PDC_SLEW_CTL);
885 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
887 static int printed_version;
888 struct ata_probe_ent *probe_ent;
889 struct pdc_host_priv *hp;
891 unsigned int board_idx = (unsigned int) ent->driver_data;
895 if (!printed_version++)
896 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
898 rc = pcim_enable_device(pdev);
902 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
904 pcim_pin_device(pdev);
908 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
911 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
915 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
916 if (probe_ent == NULL)
919 probe_ent->dev = pci_dev_to_dev(pdev);
920 INIT_LIST_HEAD(&probe_ent->node);
922 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
926 probe_ent->private_data = hp;
928 probe_ent->sht = pdc_port_info[board_idx].sht;
929 probe_ent->port_flags = pdc_port_info[board_idx].flags;
930 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
931 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
932 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
933 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
935 probe_ent->irq = pdev->irq;
936 probe_ent->irq_flags = IRQF_SHARED;
937 probe_ent->iomap = pcim_iomap_table(pdev);
939 base = probe_ent->iomap[PDC_MMIO_BAR];
941 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
942 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
944 probe_ent->port[0].scr_addr = base + 0x400;
945 probe_ent->port[1].scr_addr = base + 0x500;
947 /* notice 4-port boards */
950 hp->flags |= PDC_FLAG_GEN_II;
953 probe_ent->n_ports = 4;
955 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
956 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
958 probe_ent->port[2].scr_addr = base + 0x600;
959 probe_ent->port[3].scr_addr = base + 0x700;
962 hp->flags |= PDC_FLAG_GEN_II;
965 /* TX2plus boards also have a PATA port */
966 tmp = readb(base + PDC_FLASH_CTL+1);
968 probe_ent->n_ports = 3;
969 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
970 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
971 printk(KERN_INFO DRV_NAME " PATA port found\n");
973 probe_ent->n_ports = 2;
974 hp->port_flags[0] = ATA_FLAG_SATA;
975 hp->port_flags[1] = ATA_FLAG_SATA;
978 probe_ent->n_ports = 4;
980 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
981 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
983 probe_ent->port[2].scr_addr = base + 0x600;
984 probe_ent->port[3].scr_addr = base + 0x700;
991 pci_set_master(pdev);
993 /* initialize adapter */
994 pdc_host_init(board_idx, probe_ent);
996 if (!ata_device_add(probe_ent))
999 devm_kfree(&pdev->dev, probe_ent);
1004 static int __init pdc_ata_init(void)
1006 return pci_register_driver(&pdc_ata_pci_driver);
1010 static void __exit pdc_ata_exit(void)
1012 pci_unregister_driver(&pdc_ata_pci_driver);
1016 MODULE_AUTHOR("Jeff Garzik");
1017 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1018 MODULE_LICENSE("GPL");
1019 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1020 MODULE_VERSION(DRV_VERSION);
1022 module_init(pdc_ata_init);
1023 module_exit(pdc_ata_exit);