2 * drivers/ata/sata_dwc_460ex.c
4 * Synopsys DesignWare Cores (DWC) SATA host driver
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
21 #ifdef CONFIG_SATA_DWC_DEBUG
25 #ifdef CONFIG_SATA_DWC_VDEBUG
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/device.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/libata.h>
37 #include <linux/slab.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_cmnd.h>
43 /* These two are defined in "libata.h" */
46 #define DRV_NAME "sata-dwc"
47 #define DRV_VERSION "1.3"
49 /* SATA DMA driver Globals */
50 #define DMA_NUM_CHANS 1
51 #define DMA_NUM_CHAN_REGS 8
53 /* SATA DMA Register definitions */
54 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
57 u32 low; /* Low bits 0-31 */
58 u32 high; /* High bits 32-63 */
61 /* DMA Per Channel registers */
62 struct dma_chan_regs {
63 struct dmareg sar; /* Source Address */
64 struct dmareg dar; /* Destination address */
65 struct dmareg llp; /* Linked List Pointer */
66 struct dmareg ctl; /* Control */
67 struct dmareg sstat; /* Source Status not implemented in core */
68 struct dmareg dstat; /* Destination Status not implemented in core*/
69 struct dmareg sstatar; /* Source Status Address not impl in core */
70 struct dmareg dstatar; /* Destination Status Address not implemente */
71 struct dmareg cfg; /* Config */
72 struct dmareg sgr; /* Source Gather */
73 struct dmareg dsr; /* Destination Scatter */
76 /* Generic Interrupt Registers */
77 struct dma_interrupt_regs {
78 struct dmareg tfr; /* Transfer Interrupt */
79 struct dmareg block; /* Block Interrupt */
80 struct dmareg srctran; /* Source Transfer Interrupt */
81 struct dmareg dsttran; /* Dest Transfer Interrupt */
82 struct dmareg error; /* Error */
86 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
87 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
88 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
89 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
90 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
91 struct dmareg statusInt; /* Interrupt combined*/
92 struct dmareg rq_srcreg; /* Src Trans Req */
93 struct dmareg rq_dstreg; /* Dst Trans Req */
94 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
95 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
96 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
97 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
98 struct dmareg dma_cfg; /* DMA Config */
99 struct dmareg dma_chan_en; /* DMA Channel Enable*/
100 struct dmareg dma_id; /* DMA ID */
101 struct dmareg dma_test; /* DMA Test */
102 struct dmareg res1; /* reserved */
103 struct dmareg res2; /* reserved */
106 * Param 6 = dma_param[0], Param 5 = dma_param[1],
107 * Param 4 = dma_param[2] ...
109 struct dmareg dma_params[6];
112 /* Data structure for linked list item */
114 u32 sar; /* Source Address */
115 u32 dar; /* Destination address */
116 u32 llp; /* Linked List Pointer */
117 struct dmareg ctl; /* Control */
118 struct dmareg dstat; /* Destination Status */
122 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
123 SATA_DWC_DMAC_LLI_NUM = 256,
124 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
125 SATA_DWC_DMAC_LLI_NUM),
126 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
127 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
128 SATA_DWC_DMAC_TWIDTH_BYTES),
131 /* DMA Register Operation Bits */
133 DMA_EN = 0x00000001, /* Enable AHB DMA */
134 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
135 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
138 #define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
139 #define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
141 #define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
142 ((0x000000001 << (ch)) << 8))
143 /* Disable channel */
144 #define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
145 /* Transfer Type & Flow Controller */
146 #define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
147 #define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
148 #define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
149 /* Src Burst Transaction Length */
150 #define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
151 /* Dst Burst Transaction Length */
152 #define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
153 /* Source Transfer Width */
154 #define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
155 /* Destination Transfer Width */
156 #define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
158 /* Assign HW handshaking interface (x) to destination / source peripheral */
159 #define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
160 #define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
161 #define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
164 * This define is used to set block chaining disabled in the control low
165 * register. It is already in little endian format so it can be &'d dirctly.
166 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
169 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
170 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
171 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
172 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
173 DMA_CTL_SINC_DEC = 0x00000200,
174 DMA_CTL_SINC_NOCHANGE = 0x00000400,
175 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
176 DMA_CTL_DINC_DEC = 0x00000080,
177 DMA_CTL_DINC_NOCHANGE = 0x00000100,
178 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
180 /* Channel Configuration Register high bits */
181 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
182 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
184 /* Channel Configuration Register low bits */
185 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
186 DMA_CFG_RELD_SRC = 0x40000000,
187 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
188 DMA_CFG_HS_SELDST = 0x00000400,
189 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
191 /* Channel Linked List Pointer Register */
192 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
193 DMA_LLP_AHBMASTER2 = 1,
195 SATA_DWC_MAX_PORTS = 1,
197 SATA_DWC_SCR_OFFSET = 0x24,
198 SATA_DWC_REG_OFFSET = 0x64,
201 /* DWC SATA Registers */
202 struct sata_dwc_regs {
203 u32 fptagr; /* 1st party DMA tag */
204 u32 fpbor; /* 1st party DMA buffer offset */
205 u32 fptcr; /* 1st party DMA Xfr count */
206 u32 dmacr; /* DMA Control */
207 u32 dbtsr; /* DMA Burst Transac size */
208 u32 intpr; /* Interrupt Pending */
209 u32 intmr; /* Interrupt Mask */
210 u32 errmr; /* Error Mask */
211 u32 llcr; /* Link Layer Control */
212 u32 phycr; /* PHY Control */
213 u32 physr; /* PHY Status */
214 u32 rxbistpd; /* Recvd BIST pattern def register */
215 u32 rxbistpd1; /* Recvd BIST data dword1 */
216 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
217 u32 txbistpd; /* Trans BIST pattern def register */
218 u32 txbistpd1; /* Trans BIST data dword1 */
219 u32 txbistpd2; /* Trans BIST data dword2 */
220 u32 bistcr; /* BIST Control Register */
221 u32 bistfctr; /* BIST FIS Count Register */
222 u32 bistsr; /* BIST Status Register */
223 u32 bistdecr; /* BIST Dword Error count register */
224 u32 res[15]; /* Reserved locations */
225 u32 testr; /* Test Register */
226 u32 versionr; /* Version Register */
227 u32 idr; /* ID Register */
228 u32 unimpl[192]; /* Unimplemented */
229 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
233 SCR_SCONTROL_DET_ENABLE = 0x00000001,
234 SCR_SSTATUS_DET_PRESENT = 0x00000001,
235 SCR_SERROR_DIAG_X = 0x04000000,
236 /* DWC SATA Register Operations */
237 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
238 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
239 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
240 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
241 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
242 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
243 SATA_DWC_INTPR_DMAT = 0x00000001,
244 SATA_DWC_INTPR_NEWFP = 0x00000002,
245 SATA_DWC_INTPR_PMABRT = 0x00000004,
246 SATA_DWC_INTPR_ERR = 0x00000008,
247 SATA_DWC_INTPR_NEWBIST = 0x00000010,
248 SATA_DWC_INTPR_IPF = 0x10000000,
249 SATA_DWC_INTMR_DMATM = 0x00000001,
250 SATA_DWC_INTMR_NEWFPM = 0x00000002,
251 SATA_DWC_INTMR_PMABRTM = 0x00000004,
252 SATA_DWC_INTMR_ERRM = 0x00000008,
253 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
254 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
255 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
256 SATA_DWC_LLCR_RPDEN = 0x00000004,
257 /* This is all error bits, zero's are reserved fields. */
258 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
261 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
262 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
263 SATA_DWC_DMACR_TMOD_TXCHEN)
264 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
265 SATA_DWC_DMACR_TMOD_TXCHEN)
266 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
267 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
269 struct sata_dwc_device {
270 struct device *dev; /* generic device struct */
271 struct ata_probe_ent *pe; /* ptr to probe-ent */
272 struct ata_host *host;
274 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
278 #define SATA_DWC_QCMD_MAX 32
280 struct sata_dwc_device_port {
281 struct sata_dwc_device *hsdev;
282 int cmd_issued[SATA_DWC_QCMD_MAX];
283 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
284 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
285 u32 dma_chan[SATA_DWC_QCMD_MAX];
286 int dma_pending[SATA_DWC_QCMD_MAX];
290 * Commonly used DWC SATA driver Macros
292 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
293 (host)->private_data)
294 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
295 (ap)->host->private_data)
296 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
298 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
299 (qc)->ap->host->private_data)
300 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
304 SATA_DWC_CMD_ISSUED_NOT = 0,
305 SATA_DWC_CMD_ISSUED_PEND = 1,
306 SATA_DWC_CMD_ISSUED_EXEC = 2,
307 SATA_DWC_CMD_ISSUED_NODATA = 3,
309 SATA_DWC_DMA_PENDING_NONE = 0,
310 SATA_DWC_DMA_PENDING_TX = 1,
311 SATA_DWC_DMA_PENDING_RX = 2,
314 struct sata_dwc_host_priv {
315 void __iomem *scr_addr_sstatus;
316 u32 sata_dwc_sactive_issued ;
317 u32 sata_dwc_sactive_queued ;
318 u32 dma_interrupt_count;
319 struct ahb_dma_regs *sata_dma_regs;
320 struct device *dwc_dev;
322 struct sata_dwc_host_priv host_pvt;
326 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
327 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
329 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
330 static void sata_dwc_port_stop(struct ata_port *ap);
331 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
332 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
333 static void dma_dwc_exit(struct sata_dwc_device *hsdev);
334 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
335 struct lli *lli, dma_addr_t dma_lli,
336 void __iomem *addr, int dir);
337 static void dma_dwc_xfer_start(int dma_ch);
339 static const char *get_prot_descript(u8 protocol)
341 switch ((enum ata_tf_protocols)protocol) {
342 case ATA_PROT_NODATA:
343 return "ATA no data";
350 case ATAPI_PROT_NODATA:
351 return "ATAPI no data";
361 static const char *get_dma_dir_descript(int dma_dir)
363 switch ((enum dma_data_direction)dma_dir) {
364 case DMA_BIDIRECTIONAL:
365 return "bidirectional";
368 case DMA_FROM_DEVICE:
369 return "from device";
375 static void sata_dwc_tf_dump(struct ata_taskfile *tf)
377 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
378 "0x%lx device: %x\n", tf->command,
379 get_prot_descript(tf->protocol), tf->flags, tf->device);
380 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
381 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
383 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
384 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
385 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
390 * Function: get_burst_length_encode
391 * arguments: datalength: length in bytes of data
392 * returns value to be programmed in register corresponding to data length
393 * This value is effectively the log(base 2) of the length
395 static int get_burst_length_encode(int datalength)
397 int items = datalength >> 2; /* div by 4 to get lword count */
417 static void clear_chan_interrupts(int c)
419 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
421 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
423 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
425 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
427 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
432 * Function: dma_request_channel
434 * returns channel number if available else -1
435 * This function assigns the next available DMA channel from the list to the
438 static int dma_request_channel(void)
442 for (i = 0; i < DMA_NUM_CHANS; i++) {
443 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &\
447 dev_err(host_pvt.dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
448 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)));
453 * Function: dma_dwc_interrupt
454 * arguments: irq, dev_id, pt_regs
455 * returns channel number if available else -1
456 * Interrupt Handler for DW AHB SATA DMA
458 static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
461 u32 tfr_reg, err_reg;
463 struct sata_dwc_device *hsdev =
464 (struct sata_dwc_device *)hsdev_instance;
465 struct ata_host *host = (struct ata_host *)hsdev->host;
467 struct sata_dwc_device_port *hsdevp;
469 unsigned int port = 0;
471 spin_lock_irqsave(&host->lock, flags);
472 ap = host->ports[port];
473 hsdevp = HSDEVP_FROM_AP(ap);
474 tag = ap->link.active_tag;
476 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
478 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
481 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
482 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
484 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
485 /* Check for end-of-transfer interrupt. */
486 if (tfr_reg & DMA_CHANNEL(chan)) {
488 * Each DMA command produces 2 interrupts. Only
489 * complete the command after both interrupts have been
490 * seen. (See sata_dwc_isr())
492 host_pvt.dma_interrupt_count++;
493 sata_dwc_clear_dmacr(hsdevp, tag);
495 if (hsdevp->dma_pending[tag] ==
496 SATA_DWC_DMA_PENDING_NONE) {
497 dev_err(ap->dev, "DMA not pending eot=0x%08x "
498 "err=0x%08x tag=0x%02x pending=%d\n",
499 tfr_reg, err_reg, tag,
500 hsdevp->dma_pending[tag]);
503 if ((host_pvt.dma_interrupt_count % 2) == 0)
504 sata_dwc_dma_xfer_complete(ap, 1);
506 /* Clear the interrupt */
507 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
512 /* Check for error interrupt. */
513 if (err_reg & DMA_CHANNEL(chan)) {
514 /* TODO Need error handler ! */
515 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
518 /* Clear the interrupt. */
519 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
524 spin_unlock_irqrestore(&host->lock, flags);
529 * Function: dma_request_interrupts
532 * This function registers ISR for a particular DMA channel interrupt
534 static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
539 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
540 /* Unmask error interrupt */
541 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
542 DMA_ENABLE_CHAN(chan));
544 /* Unmask end-of-transfer interrupt */
545 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
546 DMA_ENABLE_CHAN(chan));
549 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
551 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
556 /* Mark this interrupt as requested */
557 hsdev->irq_dma = irq;
562 * Function: map_sg_to_lli
563 * The Synopsis driver has a comment proposing that better performance
564 * is possible by only enabling interrupts on the last item in the linked list.
565 * However, it seems that could be a problem if an error happened on one of the
566 * first items. The transfer would halt, but no error interrupt would occur.
567 * Currently this function sets interrupts enabled for each linked list item:
570 static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
571 struct lli *lli, dma_addr_t dma_lli,
572 void __iomem *dmadr_addr, int dir)
579 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
580 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
583 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
585 for (i = 0; i < num_elems; i++, sg++) {
589 addr = (u32) sg_dma_address(sg);
590 sg_len = sg_dma_len(sg);
592 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
593 "=%d\n", __func__, i, addr, sg_len);
596 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
597 /* The LLI table is not large enough. */
598 dev_err(host_pvt.dwc_dev, "LLI table overrun "
602 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
603 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
605 offset = addr & 0xffff;
606 if ((offset + sg_len) > 0x10000)
607 len = 0x10000 - offset;
610 * Make sure a LLI block is not created that will span
611 * 8K max FIS boundary. If the block spans such a FIS
612 * boundary, there is a chance that a DMA burst will
613 * cross that boundary -- this results in an error in
614 * the host controller.
616 if (fis_len + len > 8192) {
617 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
618 "%d(0x%x) len=%d(0x%x)\n", fis_len,
620 len = 8192 - fis_len;
629 * Set DMA addresses and lower half of control register
630 * based on direction.
632 if (dir == DMA_FROM_DEVICE) {
633 lli[idx].dar = cpu_to_le32(addr);
634 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
636 lli[idx].ctl.low = cpu_to_le32(
637 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
640 DMA_CTL_SRC_MSIZE(bl) |
641 DMA_CTL_DST_MSIZE(bl) |
642 DMA_CTL_SINC_NOCHANGE |
643 DMA_CTL_SRC_TRWID(2) |
644 DMA_CTL_DST_TRWID(2) |
648 } else { /* DMA_TO_DEVICE */
649 lli[idx].sar = cpu_to_le32(addr);
650 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
652 lli[idx].ctl.low = cpu_to_le32(
653 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
656 DMA_CTL_SRC_MSIZE(bl) |
657 DMA_CTL_DST_MSIZE(bl) |
658 DMA_CTL_DINC_NOCHANGE |
659 DMA_CTL_SRC_TRWID(2) |
660 DMA_CTL_DST_TRWID(2) |
666 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
667 "0x%08x val: 0x%08x\n", __func__,
668 len, DMA_CTL_BLK_TS(len / 4));
670 /* Program the LLI CTL high register */
671 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
674 /* Program the next pointer. The next pointer must be
675 * the physical address, not the virtual address.
677 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
680 /* The last 2 bits encode the list master select. */
681 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
683 lli[idx].llp = cpu_to_le32(next_llp);
691 * The last next ptr has to be zero and the last control low register
692 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
693 * and destination enable) set back to 0 (disabled.) This is what tells
694 * the core that this is the last item in the linked list.
697 lli[idx-1].llp = 0x00000000;
698 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
700 /* Flush cache to memory */
701 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
709 * Function: dma_dwc_xfer_start
710 * arguments: Channel number
712 * Enables the DMA channel
714 static void dma_dwc_xfer_start(int dma_ch)
716 /* Enable the DMA channel */
717 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
718 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
719 DMA_ENABLE_CHAN(dma_ch));
722 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
723 struct lli *lli, dma_addr_t dma_lli,
724 void __iomem *addr, int dir)
728 /* Acquire DMA channel */
729 dma_ch = dma_request_channel();
731 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
736 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
737 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
739 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
740 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
741 lli, (u32)dma_lli, addr, num_lli);
743 clear_chan_interrupts(dma_ch);
745 /* Program the CFG register. */
746 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
747 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
748 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
750 /* Program the address of the linked list */
751 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
752 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
754 /* Program the CTL register with src enable / dst enable */
755 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
756 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
761 * Function: dma_dwc_exit
764 * This function exits the SATA DMA driver
766 static void dma_dwc_exit(struct sata_dwc_device *hsdev)
768 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
769 if (host_pvt.sata_dma_regs) {
770 iounmap(host_pvt.sata_dma_regs);
771 host_pvt.sata_dma_regs = NULL;
774 if (hsdev->irq_dma) {
775 free_irq(hsdev->irq_dma, hsdev);
781 * Function: dma_dwc_init
784 * This function initializes the SATA DMA driver
786 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
790 err = dma_request_interrupts(hsdev, irq);
792 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
793 " %d\n", __func__, err);
798 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
800 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
801 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
807 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
809 if (scr > SCR_NOTIFICATION) {
810 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
815 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
816 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
817 __func__, link->ap->print_id, scr, *val);
822 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
824 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
825 __func__, link->ap->print_id, scr, val);
826 if (scr > SCR_NOTIFICATION) {
827 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
831 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
836 static u32 core_scr_read(unsigned int scr)
838 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
842 static void core_scr_write(unsigned int scr, u32 val)
844 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
848 static void clear_serror(void)
851 val = core_scr_read(SCR_ERROR);
852 core_scr_write(SCR_ERROR, val);
856 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
858 out_le32(&hsdev->sata_dwc_regs->intpr,
859 in_le32(&hsdev->sata_dwc_regs->intpr));
862 static u32 qcmd_tag_to_mask(u8 tag)
864 return 0x00000001 << (tag & 0x1f);
868 static void sata_dwc_error_intr(struct ata_port *ap,
869 struct sata_dwc_device *hsdev, uint intpr)
871 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
872 struct ata_eh_info *ehi = &ap->link.eh_info;
873 unsigned int err_mask = 0, action = 0;
874 struct ata_queued_cmd *qc;
879 ata_ehi_clear_desc(ehi);
881 serror = core_scr_read(SCR_ERROR);
882 status = ap->ops->sff_check_status(ap);
884 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
886 tag = ap->link.active_tag;
888 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
889 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
890 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
891 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
893 /* Clear error register and interrupt bit */
895 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
897 /* This is the only error happening now. TODO check for exact error */
899 err_mask |= AC_ERR_HOST_BUS;
900 action |= ATA_EH_RESET;
902 /* Pass this on to EH */
903 ehi->serror |= serror;
904 ehi->action |= action;
906 qc = ata_qc_from_tag(ap, tag);
908 qc->err_mask |= err_mask;
910 ehi->err_mask |= err_mask;
916 * Function : sata_dwc_isr
917 * arguments : irq, void *dev_instance, struct pt_regs *regs
918 * Return value : irqreturn_t - status of IRQ
919 * This Interrupt handler called via port ops registered function.
920 * .irq_handler = sata_dwc_isr
922 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
924 struct ata_host *host = (struct ata_host *)dev_instance;
925 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
927 struct ata_queued_cmd *qc;
930 int handled, num_processed, port = 0;
931 uint intpr, sactive, sactive2, tag_mask;
932 struct sata_dwc_device_port *hsdevp;
933 host_pvt.sata_dwc_sactive_issued = 0;
935 spin_lock_irqsave(&host->lock, flags);
937 /* Read the interrupt register */
938 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
940 ap = host->ports[port];
941 hsdevp = HSDEVP_FROM_AP(ap);
943 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
944 ap->link.active_tag);
946 /* Check for error interrupt */
947 if (intpr & SATA_DWC_INTPR_ERR) {
948 sata_dwc_error_intr(ap, hsdev, intpr);
953 /* Check for DMA SETUP FIS (FP DMA) interrupt */
954 if (intpr & SATA_DWC_INTPR_NEWFP) {
955 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
957 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
958 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
959 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
960 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
962 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
964 qc = ata_qc_from_tag(ap, tag);
966 * Start FP DMA for NCQ command. At this point the tag is the
967 * active tag. It is the tag that matches the command about to
970 qc->ap->link.active_tag = tag;
971 sata_dwc_bmdma_start_by_tag(qc, tag);
976 sactive = core_scr_read(SCR_ACTIVE);
977 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
979 /* If no sactive issued and tag_mask is zero then this is not NCQ */
980 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
981 if (ap->link.active_tag == ATA_TAG_POISON)
984 tag = ap->link.active_tag;
985 qc = ata_qc_from_tag(ap, tag);
987 /* DEV interrupt w/ no active qc? */
988 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
989 dev_err(ap->dev, "%s interrupt with no active qc "
990 "qc=%p\n", __func__, qc);
991 ap->ops->sff_check_status(ap);
995 status = ap->ops->sff_check_status(ap);
997 qc->ap->link.active_tag = tag;
998 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1000 if (status & ATA_ERR) {
1001 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1002 sata_dwc_qc_complete(ap, qc, 1);
1007 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
1008 __func__, get_prot_descript(qc->tf.protocol));
1010 if (ata_is_dma(qc->tf.protocol)) {
1012 * Each DMA transaction produces 2 interrupts. The DMAC
1013 * transfer complete interrupt and the SATA controller
1014 * operation done interrupt. The command should be
1015 * completed only after both interrupts are seen.
1017 host_pvt.dma_interrupt_count++;
1018 if (hsdevp->dma_pending[tag] == \
1019 SATA_DWC_DMA_PENDING_NONE) {
1020 dev_err(ap->dev, "%s: DMA not pending "
1021 "intpr=0x%08x status=0x%08x pending"
1022 "=%d\n", __func__, intpr, status,
1023 hsdevp->dma_pending[tag]);
1026 if ((host_pvt.dma_interrupt_count % 2) == 0)
1027 sata_dwc_dma_xfer_complete(ap, 1);
1028 } else if (ata_is_pio(qc->tf.protocol)) {
1029 ata_sff_hsm_move(ap, qc, status, 0);
1033 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1042 * This is a NCQ command. At this point we need to figure out for which
1043 * tags we have gotten a completion interrupt. One interrupt may serve
1044 * as completion for more than one operation when commands are queued
1045 * (NCQ). We need to process each completed command.
1048 /* process completed commands */
1049 sactive = core_scr_read(SCR_ACTIVE);
1050 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1052 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1054 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1055 "tag_mask=0x%08x\n", __func__, sactive,
1056 host_pvt.sata_dwc_sactive_issued, tag_mask);
1059 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1060 (host_pvt.sata_dwc_sactive_issued)) {
1061 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1062 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1063 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1067 /* read just to clear ... not bad if currently still busy */
1068 status = ap->ops->sff_check_status(ap);
1069 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1075 while (!(tag_mask & 0x00000001)) {
1080 tag_mask &= (~0x00000001);
1081 qc = ata_qc_from_tag(ap, tag);
1083 /* To be picked up by completion functions */
1084 qc->ap->link.active_tag = tag;
1085 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1087 /* Let libata/scsi layers handle error */
1088 if (status & ATA_ERR) {
1089 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1091 sata_dwc_qc_complete(ap, qc, 1);
1096 /* Process completed command */
1097 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1098 get_prot_descript(qc->tf.protocol));
1099 if (ata_is_dma(qc->tf.protocol)) {
1100 host_pvt.dma_interrupt_count++;
1101 if (hsdevp->dma_pending[tag] == \
1102 SATA_DWC_DMA_PENDING_NONE)
1103 dev_warn(ap->dev, "%s: DMA not pending?\n",
1105 if ((host_pvt.dma_interrupt_count % 2) == 0)
1106 sata_dwc_dma_xfer_complete(ap, 1);
1108 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1114 ap->stats.idle_irq++;
1115 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1117 } /* while tag_mask */
1120 * Check to see if any commands completed while we were processing our
1121 * initial set of completed commands (read status clears interrupts,
1122 * so we might miss a completed command interrupt if one came in while
1123 * we were processing --we read status as part of processing a completed
1126 sactive2 = core_scr_read(SCR_ACTIVE);
1127 if (sactive2 != sactive) {
1128 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1129 "=0x%x\n", sactive, sactive2);
1134 spin_unlock_irqrestore(&host->lock, flags);
1135 return IRQ_RETVAL(handled);
1138 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1140 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1142 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1143 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1144 SATA_DWC_DMACR_RX_CLEAR(
1145 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1146 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1147 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1148 SATA_DWC_DMACR_TX_CLEAR(
1149 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1152 * This should not happen, it indicates the driver is out of
1153 * sync. If it does happen, clear dmacr anyway.
1155 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1156 "TX DMA not pending tag=0x%02x pending=%d"
1157 " dmacr: 0x%08x\n", __func__, tag,
1158 hsdevp->dma_pending[tag],
1159 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1160 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1161 SATA_DWC_DMACR_TXRXCH_CLEAR);
1165 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1167 struct ata_queued_cmd *qc;
1168 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1169 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1172 tag = ap->link.active_tag;
1173 qc = ata_qc_from_tag(ap, tag);
1175 dev_err(ap->dev, "failed to get qc");
1181 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1182 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1183 get_dma_dir_descript(qc->dma_dir),
1184 get_prot_descript(qc->tf.protocol),
1185 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1189 if (ata_is_dma(qc->tf.protocol)) {
1190 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1191 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1192 "pending dmacr: 0x%08x\n", __func__,
1193 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1196 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1197 sata_dwc_qc_complete(ap, qc, check_status);
1198 ap->link.active_tag = ATA_TAG_POISON;
1200 sata_dwc_qc_complete(ap, qc, check_status);
1204 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1210 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1211 host_pvt.sata_dwc_sactive_queued = 0;
1212 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1214 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1215 dev_err(ap->dev, "TX DMA PENDING\n");
1216 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1217 dev_err(ap->dev, "RX DMA PENDING\n");
1218 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1219 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1222 /* clear active bit */
1223 mask = (~(qcmd_tag_to_mask(tag)));
1224 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1226 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1228 ata_qc_complete(qc);
1232 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1234 /* Enable selective interrupts by setting the interrupt maskregister*/
1235 out_le32(&hsdev->sata_dwc_regs->intmr,
1236 SATA_DWC_INTMR_ERRM |
1237 SATA_DWC_INTMR_NEWFPM |
1238 SATA_DWC_INTMR_PMABRTM |
1239 SATA_DWC_INTMR_DMATM);
1241 * Unmask the error bits that should trigger an error interrupt by
1242 * setting the error mask register.
1244 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1246 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1247 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1248 in_le32(&hsdev->sata_dwc_regs->errmr));
1251 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1253 port->cmd_addr = (void *)base + 0x00;
1254 port->data_addr = (void *)base + 0x00;
1256 port->error_addr = (void *)base + 0x04;
1257 port->feature_addr = (void *)base + 0x04;
1259 port->nsect_addr = (void *)base + 0x08;
1261 port->lbal_addr = (void *)base + 0x0c;
1262 port->lbam_addr = (void *)base + 0x10;
1263 port->lbah_addr = (void *)base + 0x14;
1265 port->device_addr = (void *)base + 0x18;
1266 port->command_addr = (void *)base + 0x1c;
1267 port->status_addr = (void *)base + 0x1c;
1269 port->altstatus_addr = (void *)base + 0x20;
1270 port->ctl_addr = (void *)base + 0x20;
1274 * Function : sata_dwc_port_start
1275 * arguments : struct ata_ioports *port
1276 * Return value : returns 0 if success, error code otherwise
1277 * This function allocates the scatter gather LLI table for AHB DMA
1279 static int sata_dwc_port_start(struct ata_port *ap)
1282 struct sata_dwc_device *hsdev;
1283 struct sata_dwc_device_port *hsdevp = NULL;
1284 struct device *pdev;
1287 hsdev = HSDEV_FROM_AP(ap);
1289 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1291 hsdev->host = ap->host;
1292 pdev = ap->host->dev;
1294 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1299 /* Allocate Port Struct */
1300 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1302 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1306 hsdevp->hsdev = hsdev;
1308 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1309 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1311 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1312 ap->bmdma_prd_dma = 0;
1315 * DMA - Assign scatter gather LLI table. We can't use the libata
1316 * version since it's PRD is IDE PCI specific.
1318 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1319 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1320 SATA_DWC_DMAC_LLI_TBL_SZ,
1321 &(hsdevp->llit_dma[i]),
1323 if (!hsdevp->llit[i]) {
1324 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1331 if (ap->port_no == 0) {
1332 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1334 out_le32(&hsdev->sata_dwc_regs->dmacr,
1335 SATA_DWC_DMACR_TXRXCH_CLEAR);
1337 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1339 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1340 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1341 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1344 /* Clear any error bits before libata starts issuing commands */
1346 ap->private_data = hsdevp;
1347 dev_dbg(ap->dev, "%s: done\n", __func__);
1353 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
1357 static void sata_dwc_port_stop(struct ata_port *ap)
1360 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1361 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1363 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1365 if (hsdevp && hsdev) {
1366 /* deallocate LLI table */
1367 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1368 dma_free_coherent(ap->host->dev,
1369 SATA_DWC_DMAC_LLI_TBL_SZ,
1370 hsdevp->llit[i], hsdevp->llit_dma[i]);
1375 ap->private_data = NULL;
1379 * Function : sata_dwc_exec_command_by_tag
1380 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1381 * Return value : None
1382 * This function keeps track of individual command tag ids and calls
1383 * ata_exec_command in libata
1385 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1386 struct ata_taskfile *tf,
1387 u8 tag, u32 cmd_issued)
1389 unsigned long flags;
1390 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1392 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1393 ata_get_cmd_descript(tf->command), tag);
1395 spin_lock_irqsave(&ap->host->lock, flags);
1396 hsdevp->cmd_issued[tag] = cmd_issued;
1397 spin_unlock_irqrestore(&ap->host->lock, flags);
1399 * Clear SError before executing a new command.
1400 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1401 * managed SError register for the disk needs to be done before the
1402 * task file is loaded.
1405 ata_sff_exec_command(ap, tf);
1408 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1410 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1411 SATA_DWC_CMD_ISSUED_PEND);
1414 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1418 if (ata_is_ncq(qc->tf.protocol)) {
1419 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1420 __func__, qc->ap->link.sactive, tag);
1424 sata_dwc_bmdma_setup_by_tag(qc, tag);
1427 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1431 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1432 struct ata_port *ap = qc->ap;
1433 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1434 int dir = qc->dma_dir;
1435 dma_chan = hsdevp->dma_chan[tag];
1437 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1439 if (dir == DMA_TO_DEVICE)
1440 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1442 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1444 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1445 "(tag=%d) DMA NOT started\n", __func__,
1446 hsdevp->cmd_issued[tag], tag);
1450 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1451 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1452 get_dma_dir_descript(qc->dma_dir), start_dma);
1453 sata_dwc_tf_dump(&(qc->tf));
1456 reg = core_scr_read(SCR_ERROR);
1457 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1458 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1462 if (dir == DMA_TO_DEVICE)
1463 out_le32(&hsdev->sata_dwc_regs->dmacr,
1464 SATA_DWC_DMACR_TXCHEN);
1466 out_le32(&hsdev->sata_dwc_regs->dmacr,
1467 SATA_DWC_DMACR_RXCHEN);
1469 /* Enable AHB DMA transfer on the specified channel */
1470 dma_dwc_xfer_start(dma_chan);
1474 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1478 if (ata_is_ncq(qc->tf.protocol)) {
1479 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1480 __func__, qc->ap->link.sactive, tag);
1484 dev_dbg(qc->ap->dev, "%s\n", __func__);
1485 sata_dwc_bmdma_start_by_tag(qc, tag);
1489 * Function : sata_dwc_qc_prep_by_tag
1490 * arguments : ata_queued_cmd *qc, u8 tag
1491 * Return value : None
1492 * qc_prep for a particular queued command based on tag
1494 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1496 struct scatterlist *sg = qc->sg;
1497 struct ata_port *ap = qc->ap;
1499 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1500 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1502 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1503 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
1506 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1507 hsdevp->llit_dma[tag],
1508 (void *__iomem)(&hsdev->sata_dwc_regs->\
1509 dmadr), qc->dma_dir);
1511 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1512 __func__, dma_chan);
1515 hsdevp->dma_chan[tag] = dma_chan;
1518 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1522 struct ata_port *ap = qc->ap;
1525 if (qc->tag > 0 || ap->link.sactive > 1)
1526 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1527 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1528 __func__, ap->print_id, qc->tf.command,
1529 ata_get_cmd_descript(qc->tf.command),
1530 qc->tag, get_prot_descript(qc->tf.protocol),
1531 ap->link.active_tag, ap->link.sactive);
1534 if (!ata_is_ncq(qc->tf.protocol))
1536 sata_dwc_qc_prep_by_tag(qc, tag);
1538 if (ata_is_ncq(qc->tf.protocol)) {
1539 sactive = core_scr_read(SCR_ACTIVE);
1540 sactive |= (0x00000001 << tag);
1541 core_scr_write(SCR_ACTIVE, sactive);
1543 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1544 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1547 ap->ops->sff_tf_load(ap, &qc->tf);
1548 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1549 SATA_DWC_CMD_ISSUED_PEND);
1551 ata_sff_qc_issue(qc);
1557 * Function : sata_dwc_qc_prep
1558 * arguments : ata_queued_cmd *qc
1559 * Return value : None
1560 * qc_prep for a particular queued command
1563 static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1565 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1570 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1571 __func__, qc->tag, qc->ap->link.active_tag);
1577 static void sata_dwc_error_handler(struct ata_port *ap)
1579 ap->link.flags |= ATA_LFLAG_NO_HRST;
1580 ata_sff_error_handler(ap);
1584 * scsi mid-layer and libata interface structures
1586 static struct scsi_host_template sata_dwc_sht = {
1587 ATA_NCQ_SHT(DRV_NAME),
1589 * test-only: Currently this driver doesn't handle NCQ
1590 * correctly. We enable NCQ but set the queue depth to a
1591 * max of 1. This will get fixed in in a future release.
1593 .sg_tablesize = LIBATA_MAX_PRD,
1594 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1595 .dma_boundary = ATA_DMA_BOUNDARY,
1598 static struct ata_port_operations sata_dwc_ops = {
1599 .inherits = &ata_sff_port_ops,
1601 .error_handler = sata_dwc_error_handler,
1603 .qc_prep = sata_dwc_qc_prep,
1604 .qc_issue = sata_dwc_qc_issue,
1606 .scr_read = sata_dwc_scr_read,
1607 .scr_write = sata_dwc_scr_write,
1609 .port_start = sata_dwc_port_start,
1610 .port_stop = sata_dwc_port_stop,
1612 .bmdma_setup = sata_dwc_bmdma_setup,
1613 .bmdma_start = sata_dwc_bmdma_start,
1616 static const struct ata_port_info sata_dwc_port_info[] = {
1618 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1619 .pio_mask = ATA_PIO4,
1620 .udma_mask = ATA_UDMA6,
1621 .port_ops = &sata_dwc_ops,
1625 static int sata_dwc_probe(struct platform_device *ofdev)
1627 struct sata_dwc_device *hsdev;
1629 char *ver = (char *)&versionr;
1633 struct ata_host *host;
1634 struct ata_port_info pi = sata_dwc_port_info[0];
1635 const struct ata_port_info *ppi[] = { &pi, NULL };
1637 /* Allocate DWC SATA device */
1638 hsdev = kzalloc(sizeof(*hsdev), GFP_KERNEL);
1639 if (hsdev == NULL) {
1640 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1645 /* Ioremap SATA registers */
1646 base = of_iomap(ofdev->dev.of_node, 0);
1648 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1653 hsdev->reg_base = base;
1654 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1656 /* Synopsys DWC SATA specific Registers */
1657 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1659 /* Allocate and fill host */
1660 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1662 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1667 host->private_data = hsdev;
1670 host->ports[0]->ioaddr.cmd_addr = base;
1671 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1672 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1673 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1675 /* Read the ID and Version Registers */
1676 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1677 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1678 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1679 idr, ver[0], ver[1], ver[2]);
1681 /* Get SATA DMA interrupt number */
1682 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1683 if (irq == NO_IRQ) {
1684 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1689 /* Get physical SATA DMA register base address */
1690 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1691 if (!(host_pvt.sata_dma_regs)) {
1692 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1698 /* Save dev for later use in dev_xxx() routines */
1699 host_pvt.dwc_dev = &ofdev->dev;
1701 /* Initialize AHB DMAC */
1702 err = dma_dwc_init(hsdev, irq);
1704 goto error_dma_iomap;
1706 /* Enable SATA Interrupts */
1707 sata_dwc_enable_interrupts(hsdev);
1709 /* Get SATA interrupt number */
1710 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1711 if (irq == NO_IRQ) {
1712 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1718 * Now, register with libATA core, this will also initiate the
1719 * device discovery process, invoking our port_start() handler &
1720 * error_handler() to execute a dummy Softreset EH session
1722 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1724 dev_err(&ofdev->dev, "failed to activate host");
1726 dev_set_drvdata(&ofdev->dev, host);
1730 /* Free SATA DMA resources */
1731 dma_dwc_exit(hsdev);
1733 iounmap((void __iomem *)host_pvt.sata_dma_regs);
1742 static int sata_dwc_remove(struct platform_device *ofdev)
1744 struct device *dev = &ofdev->dev;
1745 struct ata_host *host = dev_get_drvdata(dev);
1746 struct sata_dwc_device *hsdev = host->private_data;
1748 ata_host_detach(host);
1749 dev_set_drvdata(dev, NULL);
1751 /* Free SATA DMA resources */
1752 dma_dwc_exit(hsdev);
1754 iounmap((void __iomem *)host_pvt.sata_dma_regs);
1755 iounmap(hsdev->reg_base);
1758 dev_dbg(&ofdev->dev, "done\n");
1762 static const struct of_device_id sata_dwc_match[] = {
1763 { .compatible = "amcc,sata-460ex", },
1766 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1768 static struct platform_driver sata_dwc_driver = {
1771 .owner = THIS_MODULE,
1772 .of_match_table = sata_dwc_match,
1774 .probe = sata_dwc_probe,
1775 .remove = sata_dwc_remove,
1778 static int __init sata_dwc_init(void)
1780 return platform_driver_register(&sata_dwc_driver);
1783 static void __exit sata_dwc_exit(void)
1785 platform_driver_unregister(&sata_dwc_driver);
1788 module_init(sata_dwc_init);
1789 module_exit(sata_dwc_exit);
1791 MODULE_LICENSE("GPL");
1792 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1793 MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1794 MODULE_VERSION(DRV_VERSION);