2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/gfp.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/blkdev.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <linux/libata.h>
47 #define DRV_NAME "pdc_adma"
48 #define DRV_VERSION "1.0"
50 /* macro to calculate base address for ATA regs */
51 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
53 /* macro to calculate base address for ADMA regs */
54 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
56 /* macro to obtain addresses from ata_port */
57 #define ADMA_PORT_REGS(ap) \
58 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
65 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
66 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
68 ADMA_DMA_BOUNDARY = 0xffffffff,
70 /* global register offsets */
71 ADMA_MODE_LOCK = 0x00c7,
73 /* per-channel register offsets */
74 ADMA_CONTROL = 0x0000, /* ADMA control */
75 ADMA_STATUS = 0x0002, /* ADMA status */
76 ADMA_CPB_COUNT = 0x0004, /* CPB count */
77 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
78 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
79 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
80 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
81 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
83 /* ADMA_CONTROL register bits */
84 aNIEN = (1 << 8), /* irq mask: 1==masked */
85 aGO = (1 << 7), /* packet trigger ("Go!") */
86 aRSTADM = (1 << 5), /* ADMA logic reset */
87 aPIOMD4 = 0x0003, /* PIO mode 4 */
89 /* ADMA_STATUS register bits */
107 /* ATA register flags */
111 /* ATA register addresses */
112 ADMA_REGS_CONTROL = 0x0e,
113 ADMA_REGS_SECTOR_COUNT = 0x12,
114 ADMA_REGS_LBA_LOW = 0x13,
115 ADMA_REGS_LBA_MID = 0x14,
116 ADMA_REGS_LBA_HIGH = 0x15,
117 ADMA_REGS_DEVICE = 0x16,
118 ADMA_REGS_COMMAND = 0x17,
121 board_1841_idx = 0, /* ADMA 2-port controller */
124 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
126 struct adma_port_priv {
132 static int adma_ata_init_one(struct pci_dev *pdev,
133 const struct pci_device_id *ent);
134 static int adma_port_start(struct ata_port *ap);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_freeze(struct ata_port *ap);
140 static void adma_thaw(struct ata_port *ap);
141 static int adma_prereset(struct ata_link *link, unsigned long deadline);
143 static struct scsi_host_template adma_ata_sht = {
144 ATA_BASE_SHT(DRV_NAME),
145 .sg_tablesize = LIBATA_MAX_PRD,
146 .dma_boundary = ADMA_DMA_BOUNDARY,
149 static struct ata_port_operations adma_ata_ops = {
150 .inherits = &ata_sff_port_ops,
152 .lost_interrupt = ATA_OP_NULL,
154 .check_atapi_dma = adma_check_atapi_dma,
155 .qc_prep = adma_qc_prep,
156 .qc_issue = adma_qc_issue,
158 .freeze = adma_freeze,
160 .prereset = adma_prereset,
162 .port_start = adma_port_start,
163 .port_stop = adma_port_stop,
166 static struct ata_port_info adma_port_info[] = {
169 .flags = ATA_FLAG_SLAVE_POSS |
170 ATA_FLAG_NO_LEGACY | ATA_FLAG_PIO_POLLING,
171 .pio_mask = ATA_PIO4_ONLY,
172 .udma_mask = ATA_UDMA4,
173 .port_ops = &adma_ata_ops,
177 static const struct pci_device_id adma_ata_pci_tbl[] = {
178 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
180 { } /* terminate list */
183 static struct pci_driver adma_ata_pci_driver = {
185 .id_table = adma_ata_pci_tbl,
186 .probe = adma_ata_init_one,
187 .remove = ata_pci_remove_one,
190 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
192 return 1; /* ATAPI DMA not yet supported */
195 static void adma_reset_engine(struct ata_port *ap)
197 void __iomem *chan = ADMA_PORT_REGS(ap);
199 /* reset ADMA to idle state */
200 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
202 writew(aPIOMD4, chan + ADMA_CONTROL);
206 static void adma_reinit_engine(struct ata_port *ap)
208 struct adma_port_priv *pp = ap->private_data;
209 void __iomem *chan = ADMA_PORT_REGS(ap);
211 /* mask/clear ATA interrupts */
212 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
213 ata_sff_check_status(ap);
215 /* reset the ADMA engine */
216 adma_reset_engine(ap);
218 /* set in-FIFO threshold to 0x100 */
219 writew(0x100, chan + ADMA_FIFO_IN);
221 /* set CPB pointer */
222 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
224 /* set out-FIFO threshold to 0x100 */
225 writew(0x100, chan + ADMA_FIFO_OUT);
228 writew(1, chan + ADMA_CPB_COUNT);
230 /* read/discard ADMA status */
231 readb(chan + ADMA_STATUS);
234 static inline void adma_enter_reg_mode(struct ata_port *ap)
236 void __iomem *chan = ADMA_PORT_REGS(ap);
238 writew(aPIOMD4, chan + ADMA_CONTROL);
239 readb(chan + ADMA_STATUS); /* flush */
242 static void adma_freeze(struct ata_port *ap)
244 void __iomem *chan = ADMA_PORT_REGS(ap);
246 /* mask/clear ATA interrupts */
247 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
248 ata_sff_check_status(ap);
250 /* reset ADMA to idle state */
251 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
253 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
257 static void adma_thaw(struct ata_port *ap)
259 adma_reinit_engine(ap);
262 static int adma_prereset(struct ata_link *link, unsigned long deadline)
264 struct ata_port *ap = link->ap;
265 struct adma_port_priv *pp = ap->private_data;
267 if (pp->state != adma_state_idle) /* healthy paranoia */
268 pp->state = adma_state_mmio;
269 adma_reinit_engine(ap);
271 return ata_sff_prereset(link, deadline);
274 static int adma_fill_sg(struct ata_queued_cmd *qc)
276 struct scatterlist *sg;
277 struct ata_port *ap = qc->ap;
278 struct adma_port_priv *pp = ap->private_data;
279 u8 *buf = pp->pkt, *last_buf = NULL;
280 int i = (2 + buf[3]) * 8;
281 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
284 for_each_sg(qc->sg, sg, qc->n_elem, si) {
288 addr = (u32)sg_dma_address(sg);
289 *(__le32 *)(buf + i) = cpu_to_le32(addr);
292 len = sg_dma_len(sg) >> 3;
293 *(__le32 *)(buf + i) = cpu_to_le32(len);
298 buf[i++] = qc->dev->dma_mode & 0xf;
299 buf[i++] = 0; /* pPKLW */
300 buf[i++] = 0; /* reserved */
302 *(__le32 *)(buf + i) =
303 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
306 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
307 (unsigned long)addr, len);
310 if (likely(last_buf))
316 static void adma_qc_prep(struct ata_queued_cmd *qc)
318 struct adma_port_priv *pp = qc->ap->private_data;
320 u32 pkt_dma = (u32)pp->pkt_dma;
325 adma_enter_reg_mode(qc->ap);
326 if (qc->tf.protocol != ATA_PROT_DMA)
329 buf[i++] = 0; /* Response flags */
330 buf[i++] = 0; /* reserved */
331 buf[i++] = cVLD | cDAT | cIEN;
332 i++; /* cLEN, gets filled in below */
334 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
336 i += 4; /* cPRD, gets filled in below */
338 buf[i++] = 0; /* reserved */
339 buf[i++] = 0; /* reserved */
340 buf[i++] = 0; /* reserved */
341 buf[i++] = 0; /* reserved */
343 /* ATA registers; must be a multiple of 4 */
344 buf[i++] = qc->tf.device;
345 buf[i++] = ADMA_REGS_DEVICE;
346 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
347 buf[i++] = qc->tf.hob_nsect;
348 buf[i++] = ADMA_REGS_SECTOR_COUNT;
349 buf[i++] = qc->tf.hob_lbal;
350 buf[i++] = ADMA_REGS_LBA_LOW;
351 buf[i++] = qc->tf.hob_lbam;
352 buf[i++] = ADMA_REGS_LBA_MID;
353 buf[i++] = qc->tf.hob_lbah;
354 buf[i++] = ADMA_REGS_LBA_HIGH;
356 buf[i++] = qc->tf.nsect;
357 buf[i++] = ADMA_REGS_SECTOR_COUNT;
358 buf[i++] = qc->tf.lbal;
359 buf[i++] = ADMA_REGS_LBA_LOW;
360 buf[i++] = qc->tf.lbam;
361 buf[i++] = ADMA_REGS_LBA_MID;
362 buf[i++] = qc->tf.lbah;
363 buf[i++] = ADMA_REGS_LBA_HIGH;
365 buf[i++] = ADMA_REGS_CONTROL;
368 buf[i++] = qc->tf.command;
369 buf[i++] = ADMA_REGS_COMMAND | rEND;
371 buf[3] = (i >> 3) - 2; /* cLEN */
372 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
374 i = adma_fill_sg(qc);
375 wmb(); /* flush PRDs and pkt to memory */
377 /* dump out CPB + PRDs for debug */
380 static char obuf[2048];
381 for (j = 0; j < i; ++j) {
382 len += sprintf(obuf+len, "%02x ", buf[j]);
384 printk("%s\n", obuf);
389 printk("%s\n", obuf);
394 static inline void adma_packet_start(struct ata_queued_cmd *qc)
396 struct ata_port *ap = qc->ap;
397 void __iomem *chan = ADMA_PORT_REGS(ap);
399 VPRINTK("ENTER, ap %p\n", ap);
401 /* fire up the ADMA engine */
402 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
405 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
407 struct adma_port_priv *pp = qc->ap->private_data;
409 switch (qc->tf.protocol) {
411 pp->state = adma_state_pkt;
412 adma_packet_start(qc);
423 pp->state = adma_state_mmio;
424 return ata_sff_qc_issue(qc);
427 static inline unsigned int adma_intr_pkt(struct ata_host *host)
429 unsigned int handled = 0, port_no;
431 for (port_no = 0; port_no < host->n_ports; ++port_no) {
432 struct ata_port *ap = host->ports[port_no];
433 struct adma_port_priv *pp;
434 struct ata_queued_cmd *qc;
435 void __iomem *chan = ADMA_PORT_REGS(ap);
436 u8 status = readb(chan + ADMA_STATUS);
441 adma_enter_reg_mode(ap);
442 pp = ap->private_data;
443 if (!pp || pp->state != adma_state_pkt)
445 qc = ata_qc_from_tag(ap, ap->link.active_tag);
446 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
448 qc->err_mask |= AC_ERR_HOST_BUS;
449 else if ((status & (aPSD | aUIRQ)))
450 qc->err_mask |= AC_ERR_OTHER;
452 if (pp->pkt[0] & cATERR)
453 qc->err_mask |= AC_ERR_DEV;
454 else if (pp->pkt[0] != cDONE)
455 qc->err_mask |= AC_ERR_OTHER;
460 struct ata_eh_info *ehi = &ap->link.eh_info;
461 ata_ehi_clear_desc(ehi);
462 ata_ehi_push_desc(ehi,
463 "ADMA-status 0x%02X", status);
464 ata_ehi_push_desc(ehi,
465 "pkt[0] 0x%02X", pp->pkt[0]);
467 if (qc->err_mask == AC_ERR_DEV)
477 static inline unsigned int adma_intr_mmio(struct ata_host *host)
479 unsigned int handled = 0, port_no;
481 for (port_no = 0; port_no < host->n_ports; ++port_no) {
482 struct ata_port *ap = host->ports[port_no];
483 struct adma_port_priv *pp = ap->private_data;
484 struct ata_queued_cmd *qc;
486 if (!pp || pp->state != adma_state_mmio)
488 qc = ata_qc_from_tag(ap, ap->link.active_tag);
489 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
491 /* check main status, clearing INTRQ */
492 u8 status = ata_sff_check_status(ap);
493 if ((status & ATA_BUSY))
495 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
496 ap->print_id, qc->tf.protocol, status);
498 /* complete taskfile transaction */
499 pp->state = adma_state_idle;
500 qc->err_mask |= ac_err_mask(status);
504 struct ata_eh_info *ehi = &ap->link.eh_info;
505 ata_ehi_clear_desc(ehi);
506 ata_ehi_push_desc(ehi, "status 0x%02X", status);
508 if (qc->err_mask == AC_ERR_DEV)
519 static irqreturn_t adma_intr(int irq, void *dev_instance)
521 struct ata_host *host = dev_instance;
522 unsigned int handled = 0;
526 spin_lock(&host->lock);
527 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
528 spin_unlock(&host->lock);
532 return IRQ_RETVAL(handled);
535 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
538 port->data_addr = base + 0x000;
540 port->feature_addr = base + 0x004;
541 port->nsect_addr = base + 0x008;
542 port->lbal_addr = base + 0x00c;
543 port->lbam_addr = base + 0x010;
544 port->lbah_addr = base + 0x014;
545 port->device_addr = base + 0x018;
547 port->command_addr = base + 0x01c;
548 port->altstatus_addr =
549 port->ctl_addr = base + 0x038;
552 static int adma_port_start(struct ata_port *ap)
554 struct device *dev = ap->host->dev;
555 struct adma_port_priv *pp;
557 adma_enter_reg_mode(ap);
558 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
561 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
566 if ((pp->pkt_dma & 7) != 0) {
567 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
571 memset(pp->pkt, 0, ADMA_PKT_BYTES);
572 ap->private_data = pp;
573 adma_reinit_engine(ap);
577 static void adma_port_stop(struct ata_port *ap)
579 adma_reset_engine(ap);
582 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
584 unsigned int port_no;
586 /* enable/lock aGO operation */
587 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
589 /* reset the ADMA logic */
590 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
591 adma_reset_engine(host->ports[port_no]);
594 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
598 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
600 dev_printk(KERN_ERR, &pdev->dev,
601 "32-bit DMA enable failed\n");
604 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
606 dev_printk(KERN_ERR, &pdev->dev,
607 "32-bit consistent DMA enable failed\n");
613 static int adma_ata_init_one(struct pci_dev *pdev,
614 const struct pci_device_id *ent)
616 static int printed_version;
617 unsigned int board_idx = (unsigned int) ent->driver_data;
618 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
619 struct ata_host *host;
620 void __iomem *mmio_base;
623 if (!printed_version++)
624 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
627 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
631 /* acquire resources and fill host */
632 rc = pcim_enable_device(pdev);
636 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
639 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
642 host->iomap = pcim_iomap_table(pdev);
643 mmio_base = host->iomap[ADMA_MMIO_BAR];
645 rc = adma_set_dma_masks(pdev, mmio_base);
649 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
650 struct ata_port *ap = host->ports[port_no];
651 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
652 unsigned int offset = port_base - mmio_base;
654 adma_ata_setup_port(&ap->ioaddr, port_base);
656 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
657 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
660 /* initialize adapter */
661 adma_host_init(host, board_idx);
663 pci_set_master(pdev);
664 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
668 static int __init adma_ata_init(void)
670 return pci_register_driver(&adma_ata_pci_driver);
673 static void __exit adma_ata_exit(void)
675 pci_unregister_driver(&adma_ata_pci_driver);
678 MODULE_AUTHOR("Mark Lord");
679 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
680 MODULE_LICENSE("GPL");
681 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
682 MODULE_VERSION(DRV_VERSION);
684 module_init(adma_ata_init);
685 module_exit(adma_ata_exit);