2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
14 * Look into engine reset on timeout errors. Should not be
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_hpt37x"
28 #define DRV_VERSION "0.5.2"
38 struct hpt_clock const *clocks[4];
41 /* key for bus clock timings
43 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
44 * DMA. cycles = value + 1
45 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
46 * DMA. cycles = value + 1
47 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
49 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
51 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
52 * during task file register access.
53 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
55 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
59 * 30 PIO_MST enable. if set, the chip is in bus master mode during
64 /* from highpoint documentation. these are old values */
65 static const struct hpt_clock hpt370_timings_33[] = {
66 /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
67 { XFER_UDMA_5, 0x16454e31 },
68 { XFER_UDMA_4, 0x16454e31 },
69 { XFER_UDMA_3, 0x166d4e31 },
70 { XFER_UDMA_2, 0x16494e31 },
71 { XFER_UDMA_1, 0x164d4e31 },
72 { XFER_UDMA_0, 0x16514e31 },
74 { XFER_MW_DMA_2, 0x26514e21 },
75 { XFER_MW_DMA_1, 0x26514e33 },
76 { XFER_MW_DMA_0, 0x26514e97 },
78 { XFER_PIO_4, 0x06514e21 },
79 { XFER_PIO_3, 0x06514e22 },
80 { XFER_PIO_2, 0x06514e33 },
81 { XFER_PIO_1, 0x06914e43 },
82 { XFER_PIO_0, 0x06914e57 },
86 static const struct hpt_clock hpt370_timings_66[] = {
87 { XFER_UDMA_5, 0x14846231 },
88 { XFER_UDMA_4, 0x14886231 },
89 { XFER_UDMA_3, 0x148c6231 },
90 { XFER_UDMA_2, 0x148c6231 },
91 { XFER_UDMA_1, 0x14906231 },
92 { XFER_UDMA_0, 0x14986231 },
94 { XFER_MW_DMA_2, 0x26514e21 },
95 { XFER_MW_DMA_1, 0x26514e33 },
96 { XFER_MW_DMA_0, 0x26514e97 },
98 { XFER_PIO_4, 0x06514e21 },
99 { XFER_PIO_3, 0x06514e22 },
100 { XFER_PIO_2, 0x06514e33 },
101 { XFER_PIO_1, 0x06914e43 },
102 { XFER_PIO_0, 0x06914e57 },
106 /* these are the current (4 sep 2001) timings from highpoint */
107 static const struct hpt_clock hpt370a_timings_33[] = {
108 { XFER_UDMA_5, 0x12446231 },
109 { XFER_UDMA_4, 0x12446231 },
110 { XFER_UDMA_3, 0x126c6231 },
111 { XFER_UDMA_2, 0x12486231 },
112 { XFER_UDMA_1, 0x124c6233 },
113 { XFER_UDMA_0, 0x12506297 },
115 { XFER_MW_DMA_2, 0x22406c31 },
116 { XFER_MW_DMA_1, 0x22406c33 },
117 { XFER_MW_DMA_0, 0x22406c97 },
119 { XFER_PIO_4, 0x06414e31 },
120 { XFER_PIO_3, 0x06414e42 },
121 { XFER_PIO_2, 0x06414e53 },
122 { XFER_PIO_1, 0x06814e93 },
123 { XFER_PIO_0, 0x06814ea7 },
127 /* 2x 33MHz timings */
128 static const struct hpt_clock hpt370a_timings_66[] = {
129 { XFER_UDMA_5, 0x1488e673 },
130 { XFER_UDMA_4, 0x1488e673 },
131 { XFER_UDMA_3, 0x1498e673 },
132 { XFER_UDMA_2, 0x1490e673 },
133 { XFER_UDMA_1, 0x1498e677 },
134 { XFER_UDMA_0, 0x14a0e73f },
136 { XFER_MW_DMA_2, 0x2480fa73 },
137 { XFER_MW_DMA_1, 0x2480fa77 },
138 { XFER_MW_DMA_0, 0x2480fb3f },
140 { XFER_PIO_4, 0x0c82be73 },
141 { XFER_PIO_3, 0x0c82be95 },
142 { XFER_PIO_2, 0x0c82beb7 },
143 { XFER_PIO_1, 0x0d02bf37 },
144 { XFER_PIO_0, 0x0d02bf5f },
148 static const struct hpt_clock hpt370a_timings_50[] = {
149 { XFER_UDMA_5, 0x12848242 },
150 { XFER_UDMA_4, 0x12ac8242 },
151 { XFER_UDMA_3, 0x128c8242 },
152 { XFER_UDMA_2, 0x120c8242 },
153 { XFER_UDMA_1, 0x12148254 },
154 { XFER_UDMA_0, 0x121882ea },
156 { XFER_MW_DMA_2, 0x22808242 },
157 { XFER_MW_DMA_1, 0x22808254 },
158 { XFER_MW_DMA_0, 0x228082ea },
160 { XFER_PIO_4, 0x0a81f442 },
161 { XFER_PIO_3, 0x0a81f443 },
162 { XFER_PIO_2, 0x0a81f454 },
163 { XFER_PIO_1, 0x0ac1f465 },
164 { XFER_PIO_0, 0x0ac1f48a },
168 static const struct hpt_clock hpt372_timings_33[] = {
169 { XFER_UDMA_6, 0x1c81dc62 },
170 { XFER_UDMA_5, 0x1c6ddc62 },
171 { XFER_UDMA_4, 0x1c8ddc62 },
172 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
173 { XFER_UDMA_2, 0x1c91dc62 },
174 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
175 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
177 { XFER_MW_DMA_2, 0x2c829262 },
178 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
179 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
181 { XFER_PIO_4, 0x0c829c62 },
182 { XFER_PIO_3, 0x0c829c84 },
183 { XFER_PIO_2, 0x0c829ca6 },
184 { XFER_PIO_1, 0x0d029d26 },
185 { XFER_PIO_0, 0x0d029d5e },
189 static const struct hpt_clock hpt372_timings_50[] = {
190 { XFER_UDMA_5, 0x12848242 },
191 { XFER_UDMA_4, 0x12ac8242 },
192 { XFER_UDMA_3, 0x128c8242 },
193 { XFER_UDMA_2, 0x120c8242 },
194 { XFER_UDMA_1, 0x12148254 },
195 { XFER_UDMA_0, 0x121882ea },
197 { XFER_MW_DMA_2, 0x22808242 },
198 { XFER_MW_DMA_1, 0x22808254 },
199 { XFER_MW_DMA_0, 0x228082ea },
201 { XFER_PIO_4, 0x0a81f442 },
202 { XFER_PIO_3, 0x0a81f443 },
203 { XFER_PIO_2, 0x0a81f454 },
204 { XFER_PIO_1, 0x0ac1f465 },
205 { XFER_PIO_0, 0x0ac1f48a },
209 static const struct hpt_clock hpt372_timings_66[] = {
210 { XFER_UDMA_6, 0x1c869c62 },
211 { XFER_UDMA_5, 0x1cae9c62 },
212 { XFER_UDMA_4, 0x1c8a9c62 },
213 { XFER_UDMA_3, 0x1c8e9c62 },
214 { XFER_UDMA_2, 0x1c929c62 },
215 { XFER_UDMA_1, 0x1c9a9c62 },
216 { XFER_UDMA_0, 0x1c829c62 },
218 { XFER_MW_DMA_2, 0x2c829c62 },
219 { XFER_MW_DMA_1, 0x2c829c66 },
220 { XFER_MW_DMA_0, 0x2c829d2e },
222 { XFER_PIO_4, 0x0c829c62 },
223 { XFER_PIO_3, 0x0c829c84 },
224 { XFER_PIO_2, 0x0c829ca6 },
225 { XFER_PIO_1, 0x0d029d26 },
226 { XFER_PIO_0, 0x0d029d5e },
230 static const struct hpt_clock hpt374_timings_33[] = {
231 { XFER_UDMA_6, 0x12808242 },
232 { XFER_UDMA_5, 0x12848242 },
233 { XFER_UDMA_4, 0x12ac8242 },
234 { XFER_UDMA_3, 0x128c8242 },
235 { XFER_UDMA_2, 0x120c8242 },
236 { XFER_UDMA_1, 0x12148254 },
237 { XFER_UDMA_0, 0x121882ea },
239 { XFER_MW_DMA_2, 0x22808242 },
240 { XFER_MW_DMA_1, 0x22808254 },
241 { XFER_MW_DMA_0, 0x228082ea },
243 { XFER_PIO_4, 0x0a81f442 },
244 { XFER_PIO_3, 0x0a81f443 },
245 { XFER_PIO_2, 0x0a81f454 },
246 { XFER_PIO_1, 0x0ac1f465 },
247 { XFER_PIO_0, 0x0ac1f48a },
251 static const struct hpt_chip hpt370 = {
262 static const struct hpt_chip hpt370a = {
273 static const struct hpt_chip hpt372 = {
284 static const struct hpt_chip hpt302 = {
295 static const struct hpt_chip hpt371 = {
306 static const struct hpt_chip hpt372a = {
317 static const struct hpt_chip hpt374 = {
329 * hpt37x_find_mode - reset the hpt37x bus
331 * @speed: transfer mode
333 * Return the 32bit register programming information for this channel
334 * that matches the speed provided.
337 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
339 struct hpt_clock *clocks = ap->host->private_data;
341 while(clocks->xfer_speed) {
342 if (clocks->xfer_speed == speed)
343 return clocks->timing;
347 return 0xffffffffU; /* silence compiler warning */
350 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
352 unsigned char model_num[ATA_ID_PROD_LEN];
357 ata_id_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
359 len = strnlen(s, sizeof(model_num));
361 /* ATAPI specifies that empty space is blank-filled; remove blanks */
362 while ((len > 0) && (s[len - 1] == ' ')) {
367 while(list[i] != NULL) {
368 if (!strncmp(list[i], s, len)) {
369 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
378 static const char *bad_ata33[] = {
379 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
380 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
381 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
383 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
384 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
385 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
389 static const char *bad_ata100_5[] = {
409 * hpt370_filter - mode selection filter
413 * Block UDMA on devices that cause trouble with this controller.
416 static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
418 if (adev->class == ATA_DEV_ATA) {
419 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
420 mask &= ~ATA_MASK_UDMA;
421 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
422 mask &= ~(0x1F << ATA_SHIFT_UDMA);
424 return ata_pci_default_filter(ap, adev, mask);
428 * hpt370a_filter - mode selection filter
432 * Block UDMA on devices that cause trouble with this controller.
435 static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
437 if (adev->class != ATA_DEV_ATA) {
438 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
439 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
441 return ata_pci_default_filter(ap, adev, mask);
445 * hpt37x_pre_reset - reset the hpt37x bus
446 * @ap: ATA port to reset
448 * Perform the initial reset handling for the 370/372 and 374 func 0
451 static int hpt37x_pre_reset(struct ata_port *ap)
454 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
455 static const struct pci_bits hpt37x_enable_bits[] = {
456 { 0x50, 1, 0x04, 0x04 },
457 { 0x54, 1, 0x04, 0x04 }
459 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
462 pci_read_config_byte(pdev, 0x5B, &scr2);
463 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
464 /* Cable register now active */
465 pci_read_config_byte(pdev, 0x5A, &ata66);
467 pci_write_config_byte(pdev, 0x5B, scr2);
469 if (ata66 & (1 << ap->port_no))
470 ap->cbl = ATA_CBL_PATA40;
472 ap->cbl = ATA_CBL_PATA80;
474 /* Reset the state machine */
475 pci_write_config_byte(pdev, 0x50, 0x37);
476 pci_write_config_byte(pdev, 0x54, 0x37);
479 return ata_std_prereset(ap);
483 * hpt37x_error_handler - reset the hpt374
484 * @ap: ATA port to reset
486 * Perform probe for HPT37x, except for HPT374 channel 2
489 static void hpt37x_error_handler(struct ata_port *ap)
491 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
494 static int hpt374_pre_reset(struct ata_port *ap)
496 static const struct pci_bits hpt37x_enable_bits[] = {
497 { 0x50, 1, 0x04, 0x04 },
498 { 0x54, 1, 0x04, 0x04 }
502 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
504 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
507 /* Do the extra channel work */
508 pci_read_config_word(pdev, 0x52, &mcr3);
509 pci_read_config_word(pdev, 0x56, &mcr6);
510 /* Set bit 15 of 0x52 to enable TCBLID as input
511 Set bit 15 of 0x56 to enable FCBLID as input
513 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
514 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
515 pci_read_config_byte(pdev, 0x5A, &ata66);
516 /* Reset TCBLID/FCBLID to output */
517 pci_write_config_word(pdev, 0x52, mcr3);
518 pci_write_config_word(pdev, 0x56, mcr6);
520 if (ata66 & (1 << ap->port_no))
521 ap->cbl = ATA_CBL_PATA40;
523 ap->cbl = ATA_CBL_PATA80;
525 /* Reset the state machine */
526 pci_write_config_byte(pdev, 0x50, 0x37);
527 pci_write_config_byte(pdev, 0x54, 0x37);
530 return ata_std_prereset(ap);
534 * hpt374_error_handler - reset the hpt374
537 * The 374 cable detect is a little different due to the extra
538 * channels. The function 0 channels work like usual but function 1
542 static void hpt374_error_handler(struct ata_port *ap)
544 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
546 if (!(PCI_FUNC(pdev->devfn) & 1))
547 hpt37x_error_handler(ap);
549 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
553 * hpt370_set_piomode - PIO setup
555 * @adev: device on the interface
557 * Perform PIO mode setup.
560 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
562 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
568 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
569 addr2 = 0x51 + 4 * ap->port_no;
571 /* Fast interrupt prediction disable, hold off interrupt disable */
572 pci_read_config_byte(pdev, addr2, &fast);
575 pci_write_config_byte(pdev, addr2, fast);
577 pci_read_config_dword(pdev, addr1, ®);
578 mode = hpt37x_find_mode(ap, adev->pio_mode);
579 mode &= ~0x8000000; /* No FIFO in PIO */
580 mode &= ~0x30070000; /* Leave config bits alone */
581 reg &= 0x30070000; /* Strip timing bits */
582 pci_write_config_dword(pdev, addr1, reg | mode);
586 * hpt370_set_dmamode - DMA timing setup
588 * @adev: Device being configured
590 * Set up the channel for MWDMA or UDMA modes. Much the same as with
591 * PIO, load the mode number and then set MWDMA or UDMA flag.
594 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
596 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
602 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
603 addr2 = 0x51 + 4 * ap->port_no;
605 /* Fast interrupt prediction disable, hold off interrupt disable */
606 pci_read_config_byte(pdev, addr2, &fast);
609 pci_write_config_byte(pdev, addr2, fast);
611 pci_read_config_dword(pdev, addr1, ®);
612 mode = hpt37x_find_mode(ap, adev->dma_mode);
613 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
614 mode &= ~0xC0000000; /* Leave config bits alone */
615 reg &= 0xC0000000; /* Strip timing bits */
616 pci_write_config_dword(pdev, addr1, reg | mode);
620 * hpt370_bmdma_start - DMA engine begin
623 * The 370 and 370A want us to reset the DMA engine each time we
624 * use it. The 372 and later are fine.
627 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
629 struct ata_port *ap = qc->ap;
630 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
631 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
637 * hpt370_bmdma_end - DMA engine stop
640 * Work around the HPT370 DMA engine.
643 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
645 struct ata_port *ap = qc->ap;
646 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
647 u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2);
649 unsigned long bmdma = ap->ioaddr.bmdma_addr;
651 if (dma_stat & 0x01) {
653 dma_stat = inb(bmdma + 2);
655 if (dma_stat & 0x01) {
656 /* Clear the engine */
657 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
660 dma_cmd = inb(bmdma );
661 outb(dma_cmd & 0xFE, bmdma);
663 dma_stat = inb(bmdma + 2);
664 outb(dma_stat | 0x06 , bmdma + 2);
665 /* Clear the engine */
666 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
673 * hpt372_set_piomode - PIO setup
675 * @adev: device on the interface
677 * Perform PIO mode setup.
680 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
682 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
688 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
689 addr2 = 0x51 + 4 * ap->port_no;
691 /* Fast interrupt prediction disable, hold off interrupt disable */
692 pci_read_config_byte(pdev, addr2, &fast);
694 pci_write_config_byte(pdev, addr2, fast);
696 pci_read_config_dword(pdev, addr1, ®);
697 mode = hpt37x_find_mode(ap, adev->pio_mode);
699 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
700 mode &= ~0x80000000; /* No FIFO in PIO */
701 mode &= ~0x30070000; /* Leave config bits alone */
702 reg &= 0x30070000; /* Strip timing bits */
703 pci_write_config_dword(pdev, addr1, reg | mode);
707 * hpt372_set_dmamode - DMA timing setup
709 * @adev: Device being configured
711 * Set up the channel for MWDMA or UDMA modes. Much the same as with
712 * PIO, load the mode number and then set MWDMA or UDMA flag.
715 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
717 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
723 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
724 addr2 = 0x51 + 4 * ap->port_no;
726 /* Fast interrupt prediction disable, hold off interrupt disable */
727 pci_read_config_byte(pdev, addr2, &fast);
729 pci_write_config_byte(pdev, addr2, fast);
731 pci_read_config_dword(pdev, addr1, ®);
732 mode = hpt37x_find_mode(ap, adev->dma_mode);
733 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
734 mode &= ~0xC0000000; /* Leave config bits alone */
735 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
736 reg &= 0xC0000000; /* Strip timing bits */
737 pci_write_config_dword(pdev, addr1, reg | mode);
741 * hpt37x_bmdma_end - DMA engine stop
744 * Clean up after the HPT372 and later DMA engine
747 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
749 struct ata_port *ap = qc->ap;
750 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
751 int mscreg = 0x50 + 4 * ap->port_no;
752 u8 bwsr_stat, msc_stat;
754 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
755 pci_read_config_byte(pdev, mscreg, &msc_stat);
756 if (bwsr_stat & (1 << ap->port_no))
757 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
762 static struct scsi_host_template hpt37x_sht = {
763 .module = THIS_MODULE,
765 .ioctl = ata_scsi_ioctl,
766 .queuecommand = ata_scsi_queuecmd,
767 .can_queue = ATA_DEF_QUEUE,
768 .this_id = ATA_SHT_THIS_ID,
769 .sg_tablesize = LIBATA_MAX_PRD,
770 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
771 .emulated = ATA_SHT_EMULATED,
772 .use_clustering = ATA_SHT_USE_CLUSTERING,
773 .proc_name = DRV_NAME,
774 .dma_boundary = ATA_DMA_BOUNDARY,
775 .slave_configure = ata_scsi_slave_config,
776 .slave_destroy = ata_scsi_slave_destroy,
777 .bios_param = ata_std_bios_param,
781 * Configuration for HPT370
784 static struct ata_port_operations hpt370_port_ops = {
785 .port_disable = ata_port_disable,
786 .set_piomode = hpt370_set_piomode,
787 .set_dmamode = hpt370_set_dmamode,
788 .mode_filter = hpt370_filter,
790 .tf_load = ata_tf_load,
791 .tf_read = ata_tf_read,
792 .check_status = ata_check_status,
793 .exec_command = ata_exec_command,
794 .dev_select = ata_std_dev_select,
796 .freeze = ata_bmdma_freeze,
797 .thaw = ata_bmdma_thaw,
798 .error_handler = hpt37x_error_handler,
799 .post_internal_cmd = ata_bmdma_post_internal_cmd,
801 .bmdma_setup = ata_bmdma_setup,
802 .bmdma_start = hpt370_bmdma_start,
803 .bmdma_stop = hpt370_bmdma_stop,
804 .bmdma_status = ata_bmdma_status,
806 .qc_prep = ata_qc_prep,
807 .qc_issue = ata_qc_issue_prot,
809 .data_xfer = ata_pio_data_xfer,
811 .irq_handler = ata_interrupt,
812 .irq_clear = ata_bmdma_irq_clear,
814 .port_start = ata_port_start,
815 .port_stop = ata_port_stop,
816 .host_stop = ata_host_stop
820 * Configuration for HPT370A. Close to 370 but less filters
823 static struct ata_port_operations hpt370a_port_ops = {
824 .port_disable = ata_port_disable,
825 .set_piomode = hpt370_set_piomode,
826 .set_dmamode = hpt370_set_dmamode,
827 .mode_filter = hpt370a_filter,
829 .tf_load = ata_tf_load,
830 .tf_read = ata_tf_read,
831 .check_status = ata_check_status,
832 .exec_command = ata_exec_command,
833 .dev_select = ata_std_dev_select,
835 .freeze = ata_bmdma_freeze,
836 .thaw = ata_bmdma_thaw,
837 .error_handler = hpt37x_error_handler,
838 .post_internal_cmd = ata_bmdma_post_internal_cmd,
840 .bmdma_setup = ata_bmdma_setup,
841 .bmdma_start = hpt370_bmdma_start,
842 .bmdma_stop = hpt370_bmdma_stop,
843 .bmdma_status = ata_bmdma_status,
845 .qc_prep = ata_qc_prep,
846 .qc_issue = ata_qc_issue_prot,
848 .data_xfer = ata_pio_data_xfer,
850 .irq_handler = ata_interrupt,
851 .irq_clear = ata_bmdma_irq_clear,
853 .port_start = ata_port_start,
854 .port_stop = ata_port_stop,
855 .host_stop = ata_host_stop
859 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
860 * and DMA mode setting functionality.
863 static struct ata_port_operations hpt372_port_ops = {
864 .port_disable = ata_port_disable,
865 .set_piomode = hpt372_set_piomode,
866 .set_dmamode = hpt372_set_dmamode,
867 .mode_filter = ata_pci_default_filter,
869 .tf_load = ata_tf_load,
870 .tf_read = ata_tf_read,
871 .check_status = ata_check_status,
872 .exec_command = ata_exec_command,
873 .dev_select = ata_std_dev_select,
875 .freeze = ata_bmdma_freeze,
876 .thaw = ata_bmdma_thaw,
877 .error_handler = hpt37x_error_handler,
878 .post_internal_cmd = ata_bmdma_post_internal_cmd,
880 .bmdma_setup = ata_bmdma_setup,
881 .bmdma_start = ata_bmdma_start,
882 .bmdma_stop = hpt37x_bmdma_stop,
883 .bmdma_status = ata_bmdma_status,
885 .qc_prep = ata_qc_prep,
886 .qc_issue = ata_qc_issue_prot,
888 .data_xfer = ata_pio_data_xfer,
890 .irq_handler = ata_interrupt,
891 .irq_clear = ata_bmdma_irq_clear,
893 .port_start = ata_port_start,
894 .port_stop = ata_port_stop,
895 .host_stop = ata_host_stop
899 * Configuration for HPT374. Mode setting works like 372 and friends
900 * but we have a different cable detection procedure.
903 static struct ata_port_operations hpt374_port_ops = {
904 .port_disable = ata_port_disable,
905 .set_piomode = hpt372_set_piomode,
906 .set_dmamode = hpt372_set_dmamode,
907 .mode_filter = ata_pci_default_filter,
909 .tf_load = ata_tf_load,
910 .tf_read = ata_tf_read,
911 .check_status = ata_check_status,
912 .exec_command = ata_exec_command,
913 .dev_select = ata_std_dev_select,
915 .freeze = ata_bmdma_freeze,
916 .thaw = ata_bmdma_thaw,
917 .error_handler = hpt374_error_handler,
918 .post_internal_cmd = ata_bmdma_post_internal_cmd,
920 .bmdma_setup = ata_bmdma_setup,
921 .bmdma_start = ata_bmdma_start,
922 .bmdma_stop = hpt37x_bmdma_stop,
923 .bmdma_status = ata_bmdma_status,
925 .qc_prep = ata_qc_prep,
926 .qc_issue = ata_qc_issue_prot,
928 .data_xfer = ata_pio_data_xfer,
930 .irq_handler = ata_interrupt,
931 .irq_clear = ata_bmdma_irq_clear,
933 .port_start = ata_port_start,
934 .port_stop = ata_port_stop,
935 .host_stop = ata_host_stop
939 * htp37x_clock_slot - Turn timing to PC clock entry
940 * @freq: Reported frequency timing
943 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
947 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
949 unsigned int f = (base * freq) / 192; /* Mhz */
951 return 0; /* 33Mhz slot */
953 return 1; /* 40Mhz slot */
955 return 2; /* 50Mhz slot */
956 return 3; /* 60Mhz slot */
960 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
963 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
967 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
973 for(tries = 0; tries < 0x5000; tries++) {
975 pci_read_config_byte(dev, 0x5b, ®5b);
977 /* See if it stays set */
978 for(tries = 0; tries < 0x1000; tries ++) {
979 pci_read_config_byte(dev, 0x5b, ®5b);
981 if ((reg5b & 0x80) == 0)
984 /* Turn off tuning, we have the DPLL set */
985 pci_read_config_dword(dev, 0x5c, ®5c);
986 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
990 /* Never went stable */
994 * hpt37x_init_one - Initialise an HPT37X/302
996 * @id: Entry in match table
998 * Initialise an HPT37x device. There are some interesting complications
999 * here. Firstly the chip may report 366 and be one of several variants.
1000 * Secondly all the timings depend on the clock for the chip which we must
1001 * detect and look up
1003 * This is the known chip mappings. It may be missing a couple of later
1006 * Chip version PCI Rev Notes
1007 * HPT366 4 (HPT366) 0 Other driver
1008 * HPT366 4 (HPT366) 1 Other driver
1009 * HPT368 4 (HPT366) 2 Other driver
1010 * HPT370 4 (HPT366) 3 UDMA100
1011 * HPT370A 4 (HPT366) 4 UDMA100
1012 * HPT372 4 (HPT366) 5 UDMA133 (1)
1013 * HPT372N 4 (HPT366) 6 Other driver
1014 * HPT372A 5 (HPT372) 1 UDMA133 (1)
1015 * HPT372N 5 (HPT372) 2 Other driver
1016 * HPT302 6 (HPT302) 1 UDMA133
1017 * HPT302N 6 (HPT302) 2 Other driver
1018 * HPT371 7 (HPT371) * UDMA133
1019 * HPT374 8 (HPT374) * UDMA133 4 channel
1020 * HPT372N 9 (HPT372N) * Other driver
1022 * (1) UDMA133 support depends on the bus clock
1025 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1027 /* HPT370 - UDMA100 */
1028 static struct ata_port_info info_hpt370 = {
1030 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1034 .port_ops = &hpt370_port_ops
1036 /* HPT370A - UDMA100 */
1037 static struct ata_port_info info_hpt370a = {
1039 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1043 .port_ops = &hpt370a_port_ops
1045 /* HPT371, 372 and friends - UDMA133 */
1046 static struct ata_port_info info_hpt372 = {
1048 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1052 .port_ops = &hpt372_port_ops
1054 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
1055 static struct ata_port_info info_hpt372_50 = {
1057 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1061 .port_ops = &hpt372_port_ops
1063 /* HPT374 - UDMA133 */
1064 static struct ata_port_info info_hpt374 = {
1066 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1070 .port_ops = &hpt374_port_ops
1073 static const int MHz[4] = { 33, 40, 50, 66 };
1075 struct ata_port_info *port_info[2];
1076 struct ata_port_info *port;
1082 const struct hpt_chip *chip_table;
1085 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1088 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
1089 /* May be a later chip in disguise. Check */
1090 /* Older chips are in the HPT366 driver. Ignore them */
1093 /* N series chips have their own driver. Ignore */
1099 port = &info_hpt370;
1100 chip_table = &hpt370;
1103 port = &info_hpt370a;
1104 chip_table = &hpt370a;
1107 port = &info_hpt372;
1108 chip_table = &hpt372;
1111 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
1115 switch(dev->device) {
1116 case PCI_DEVICE_ID_TTI_HPT372:
1117 /* 372N if rev >= 2*/
1120 port = &info_hpt372;
1121 chip_table = &hpt372a;
1123 case PCI_DEVICE_ID_TTI_HPT302:
1124 /* 302N if rev > 1 */
1127 port = &info_hpt372;
1129 chip_table = &hpt302;
1131 case PCI_DEVICE_ID_TTI_HPT371:
1132 port = &info_hpt372;
1133 chip_table = &hpt371;
1135 case PCI_DEVICE_ID_TTI_HPT374:
1136 chip_table = &hpt374;
1137 port = &info_hpt374;
1140 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1144 /* Ok so this is a chip we support */
1146 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1147 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1148 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1149 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1151 pci_read_config_byte(dev, 0x5A, &irqmask);
1153 pci_write_config_byte(dev, 0x5a, irqmask);
1156 * default to pci clock. make sure MA15/16 are set to output
1157 * to prevent drives having problems with 40-pin cables. Needed
1158 * for some drives such as IBM-DTLA which will not enter ready
1159 * state on reset when PDIAG is a input.
1162 pci_write_config_byte(dev, 0x5b, 0x23);
1164 pci_read_config_dword(dev, 0x70, &freq);
1165 if ((freq >> 12) != 0xABCDE) {
1170 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1172 /* This is the process the HPT371 BIOS is reported to use */
1173 for(i = 0; i < 128; i++) {
1174 pci_read_config_byte(dev, 0x78, &sr);
1183 * Turn the frequency check into a band and then find a timing
1184 * table to match it.
1187 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1188 if (chip_table->clocks[clock_slot] == NULL) {
1190 * We need to try PLL mode instead
1192 unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192;
1193 unsigned int f_high = f_low + 2;
1196 for(adjust = 0; adjust < 8; adjust++) {
1197 if (hpt37x_calibrate_dpll(dev))
1199 /* See if it'll settle at a fractionally different clock */
1200 if ((adjust & 3) == 3) {
1204 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1207 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1210 /* Check if this works for all cases */
1211 port->private_data = (void *)hpt370_timings_66;
1213 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1215 port->private_data = (void *)chip_table->clocks[clock_slot];
1217 * Perform a final fixup. The 371 and 372 clock determines
1218 * if UDMA133 is available.
1221 if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
1222 printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
1223 if (port == &info_hpt372)
1224 port = &info_hpt372_50;
1227 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
1229 port_info[0] = port_info[1] = port;
1230 /* Now kick off ATA set up */
1231 return ata_pci_init_one(dev, port_info, 2);
1234 static const struct pci_device_id hpt37x[] = {
1235 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1236 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1237 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1238 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1239 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1244 static struct pci_driver hpt37x_pci_driver = {
1247 .probe = hpt37x_init_one,
1248 .remove = ata_pci_remove_one
1251 static int __init hpt37x_init(void)
1253 return pci_register_driver(&hpt37x_pci_driver);
1256 static void __exit hpt37x_exit(void)
1258 pci_unregister_driver(&hpt37x_pci_driver);
1261 MODULE_AUTHOR("Alan Cox");
1262 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1263 MODULE_LICENSE("GPL");
1264 MODULE_DEVICE_TABLE(pci, hpt37x);
1265 MODULE_VERSION(DRV_VERSION);
1267 module_init(hpt37x_init);
1268 module_exit(hpt37x_exit);