2 * pata-cs5535.c - CS5535 PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
6 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
7 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
8 * and Alexander Kiausch <alex.kiausch@t-online.de>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * Loosely based on the piix & svwks drivers.
26 * Available from AMD web site.
28 * Review errata to see if serializing is neccessary
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/delay.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
41 #define DRV_NAME "cs5535"
42 #define DRV_VERSION "0.2.11"
45 * The Geode (Aka Athlon GX now) uses an internal MSR based
46 * bus system for control. Demented but there you go.
49 #define MSR_ATAC_BASE 0x51300000
50 #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
51 #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
52 #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
53 #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
54 #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
55 #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
56 #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
57 #define ATAC_RESET (MSR_ATAC_BASE+0x10)
58 #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
59 #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
60 #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
61 #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
62 #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
64 #define ATAC_BM0_CMD_PRIM 0x00
65 #define ATAC_BM0_STS_PRIM 0x02
66 #define ATAC_BM0_PRD 0x04
68 #define CS5535_CABLE_DETECT 0x48
70 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
73 * cs5535_pre_reset - detect cable type
74 * @ap: Port to detect on
76 * Perform cable detection for ATA66 capable cable. Return a libata
80 static int cs5535_pre_reset(struct ata_port *ap)
83 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85 pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
87 ap->cbl = ATA_CBL_PATA80;
89 ap->cbl = ATA_CBL_PATA40;
90 return ata_std_prereset(ap);
94 * cs5535_error_handler - reset/probe
97 * Reset and configure a port
100 static void cs5535_error_handler(struct ata_port *ap)
102 ata_bmdma_drive_eh(ap, cs5535_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
106 * cs5535_set_piomode - PIO setup
108 * @adev: device on the interface
110 * Set our PIO requirements. The CS5535 is pretty clean about all this
113 static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
115 static const u16 pio_timings[5] = {
116 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
118 static const u16 pio_cmd_timings[5] = {
119 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
122 struct ata_device *pair = ata_dev_pair(adev);
124 int mode = adev->pio_mode - XFER_PIO_0;
127 /* Command timing has to be for the lowest of the pair of devices */
129 int pairmode = pair->pio_mode - XFER_PIO_0;
130 cmdmode = min(mode, pairmode);
131 /* Write the other drive timing register if it changed */
132 if (cmdmode < pairmode)
133 wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
134 pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
136 /* Write the drive timing register */
137 wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
138 pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);
140 /* Set the PIO "format 1" bit in the DMA timing register */
141 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
142 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
146 * cs5535_set_dmamode - DMA timing setup
148 * @adev: Device being configured
152 static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
154 static const u32 udma_timings[5] = {
155 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
157 static const u32 mwdma_timings[3] = {
158 0x7F0FFFF3, 0x7F035352, 0x7F024241
161 int mode = adev->dma_mode;
163 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
165 if (mode >= XFER_UDMA_0)
166 reg |= udma_timings[mode - XFER_UDMA_0];
168 reg |= mwdma_timings[mode - XFER_MW_DMA_0];
169 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
172 static struct scsi_host_template cs5535_sht = {
173 .module = THIS_MODULE,
175 .ioctl = ata_scsi_ioctl,
176 .queuecommand = ata_scsi_queuecmd,
177 .can_queue = ATA_DEF_QUEUE,
178 .this_id = ATA_SHT_THIS_ID,
179 .sg_tablesize = LIBATA_MAX_PRD,
180 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
181 .emulated = ATA_SHT_EMULATED,
182 .use_clustering = ATA_SHT_USE_CLUSTERING,
183 .proc_name = DRV_NAME,
184 .dma_boundary = ATA_DMA_BOUNDARY,
185 .slave_configure = ata_scsi_slave_config,
186 .slave_destroy = ata_scsi_slave_destroy,
187 .bios_param = ata_std_bios_param,
188 .resume = ata_scsi_device_resume,
189 .suspend = ata_scsi_device_suspend,
192 static struct ata_port_operations cs5535_port_ops = {
193 .port_disable = ata_port_disable,
194 .set_piomode = cs5535_set_piomode,
195 .set_dmamode = cs5535_set_dmamode,
196 .mode_filter = ata_pci_default_filter,
198 .tf_load = ata_tf_load,
199 .tf_read = ata_tf_read,
200 .check_status = ata_check_status,
201 .exec_command = ata_exec_command,
202 .dev_select = ata_std_dev_select,
204 .freeze = ata_bmdma_freeze,
205 .thaw = ata_bmdma_thaw,
206 .error_handler = cs5535_error_handler,
207 .post_internal_cmd = ata_bmdma_post_internal_cmd,
209 .bmdma_setup = ata_bmdma_setup,
210 .bmdma_start = ata_bmdma_start,
211 .bmdma_stop = ata_bmdma_stop,
212 .bmdma_status = ata_bmdma_status,
214 .qc_prep = ata_qc_prep,
215 .qc_issue = ata_qc_issue_prot,
217 .data_xfer = ata_data_xfer,
219 .irq_handler = ata_interrupt,
220 .irq_clear = ata_bmdma_irq_clear,
221 .irq_on = ata_irq_on,
222 .irq_ack = ata_irq_ack,
224 .port_start = ata_port_start,
228 * cs5535_init_one - Initialise a CS5530
230 * @id: Entry in match table
232 * Install a driver for the newly found CS5530 companion chip. Most of
233 * this is just housekeeping. We have to set the chip up correctly and
234 * turn off various bits of emulation magic.
237 static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
239 static struct ata_port_info info = {
241 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
245 .port_ops = &cs5535_port_ops
247 struct ata_port_info *ports[1] = { &info };
251 /* Check the BIOS set the initial timing clock. If not set the
253 rdmsr(ATAC_CH0D0_PIO, timings, dummy);
254 if (CS5535_BAD_PIO(timings))
255 wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
256 rdmsr(ATAC_CH0D1_PIO, timings, dummy);
257 if (CS5535_BAD_PIO(timings))
258 wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
259 return ata_pci_init_one(dev, ports, 1);
262 static const struct pci_device_id cs5535[] = {
263 { PCI_VDEVICE(NS, 0x002D), },
268 static struct pci_driver cs5535_pci_driver = {
271 .probe = cs5535_init_one,
272 .remove = ata_pci_remove_one,
273 .suspend = ata_pci_device_suspend,
274 .resume = ata_pci_device_resume,
277 static int __init cs5535_init(void)
279 return pci_register_driver(&cs5535_pci_driver);
282 static void __exit cs5535_exit(void)
284 pci_unregister_driver(&cs5535_pci_driver);
287 MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
288 MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
289 MODULE_LICENSE("GPL");
290 MODULE_DEVICE_TABLE(pci, cs5535);
291 MODULE_VERSION(DRV_VERSION);
293 module_init(cs5535_init);
294 module_exit(cs5535_exit);