2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
49 static int ahci_skip_host_reset;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_error_handler(struct ata_port *ap);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
123 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
125 struct device_attribute *ahci_shost_attrs[] = {
126 &dev_attr_link_power_management_policy,
127 &dev_attr_em_message_type,
128 &dev_attr_em_message,
129 &dev_attr_ahci_host_caps,
130 &dev_attr_ahci_host_cap2,
131 &dev_attr_ahci_host_version,
132 &dev_attr_ahci_port_cmd,
134 &dev_attr_em_message_supported,
137 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
139 struct device_attribute *ahci_sdev_attrs[] = {
140 &dev_attr_sw_activity,
141 &dev_attr_unload_heads,
144 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
146 struct ata_port_operations ahci_ops = {
147 .inherits = &sata_pmp_port_ops,
149 .qc_defer = ahci_pmp_qc_defer,
150 .qc_prep = ahci_qc_prep,
151 .qc_issue = ahci_qc_issue,
152 .qc_fill_rtf = ahci_qc_fill_rtf,
154 .freeze = ahci_freeze,
156 .softreset = ahci_softreset,
157 .hardreset = ahci_hardreset,
158 .postreset = ahci_postreset,
159 .pmp_softreset = ahci_softreset,
160 .error_handler = ahci_error_handler,
161 .post_internal_cmd = ahci_post_internal_cmd,
162 .dev_config = ahci_dev_config,
164 .scr_read = ahci_scr_read,
165 .scr_write = ahci_scr_write,
166 .pmp_attach = ahci_pmp_attach,
167 .pmp_detach = ahci_pmp_detach,
169 .set_lpm = ahci_set_lpm,
170 .em_show = ahci_led_show,
171 .em_store = ahci_led_store,
172 .sw_activity_show = ahci_activity_show,
173 .sw_activity_store = ahci_activity_store,
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
181 EXPORT_SYMBOL_GPL(ahci_ops);
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189 int ahci_em_messages = 1;
190 EXPORT_SYMBOL_GPL(ahci_em_messages);
191 module_param(ahci_em_messages, int, 0444);
192 /* add other LED protocol types when they become supported */
193 MODULE_PARM_DESC(ahci_em_messages,
194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
196 static void ahci_enable_ahci(void __iomem *mmio)
201 /* turn on AHCI_EN */
202 tmp = readl(mmio + HOST_CTL);
203 if (tmp & HOST_AHCI_EN)
206 /* Some controllers need AHCI_EN to be written multiple times.
207 * Try a few times before giving up.
209 for (i = 0; i < 5; i++) {
211 writel(tmp, mmio + HOST_CTL);
212 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
213 if (tmp & HOST_AHCI_EN)
221 static ssize_t ahci_show_host_caps(struct device *dev,
222 struct device_attribute *attr, char *buf)
224 struct Scsi_Host *shost = class_to_shost(dev);
225 struct ata_port *ap = ata_shost_to_port(shost);
226 struct ahci_host_priv *hpriv = ap->host->private_data;
228 return sprintf(buf, "%x\n", hpriv->cap);
231 static ssize_t ahci_show_host_cap2(struct device *dev,
232 struct device_attribute *attr, char *buf)
234 struct Scsi_Host *shost = class_to_shost(dev);
235 struct ata_port *ap = ata_shost_to_port(shost);
236 struct ahci_host_priv *hpriv = ap->host->private_data;
238 return sprintf(buf, "%x\n", hpriv->cap2);
241 static ssize_t ahci_show_host_version(struct device *dev,
242 struct device_attribute *attr, char *buf)
244 struct Scsi_Host *shost = class_to_shost(dev);
245 struct ata_port *ap = ata_shost_to_port(shost);
246 struct ahci_host_priv *hpriv = ap->host->private_data;
247 void __iomem *mmio = hpriv->mmio;
249 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
252 static ssize_t ahci_show_port_cmd(struct device *dev,
253 struct device_attribute *attr, char *buf)
255 struct Scsi_Host *shost = class_to_shost(dev);
256 struct ata_port *ap = ata_shost_to_port(shost);
257 void __iomem *port_mmio = ahci_port_base(ap);
259 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
262 static ssize_t ahci_read_em_buffer(struct device *dev,
263 struct device_attribute *attr, char *buf)
265 struct Scsi_Host *shost = class_to_shost(dev);
266 struct ata_port *ap = ata_shost_to_port(shost);
267 struct ahci_host_priv *hpriv = ap->host->private_data;
268 void __iomem *mmio = hpriv->mmio;
269 void __iomem *em_mmio = mmio + hpriv->em_loc;
275 spin_lock_irqsave(ap->lock, flags);
277 em_ctl = readl(mmio + HOST_EM_CTL);
278 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
279 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
280 spin_unlock_irqrestore(ap->lock, flags);
284 if (!(em_ctl & EM_CTL_MR)) {
285 spin_unlock_irqrestore(ap->lock, flags);
289 if (!(em_ctl & EM_CTL_SMB))
290 em_mmio += hpriv->em_buf_sz;
292 count = hpriv->em_buf_sz;
294 /* the count should not be larger than PAGE_SIZE */
295 if (count > PAGE_SIZE) {
296 if (printk_ratelimit())
298 "EM read buffer size too large: "
299 "buffer size %u, page size %lu\n",
300 hpriv->em_buf_sz, PAGE_SIZE);
304 for (i = 0; i < count; i += 4) {
305 msg = readl(em_mmio + i);
307 buf[i + 1] = (msg >> 8) & 0xff;
308 buf[i + 2] = (msg >> 16) & 0xff;
309 buf[i + 3] = (msg >> 24) & 0xff;
312 spin_unlock_irqrestore(ap->lock, flags);
317 static ssize_t ahci_store_em_buffer(struct device *dev,
318 struct device_attribute *attr,
319 const char *buf, size_t size)
321 struct Scsi_Host *shost = class_to_shost(dev);
322 struct ata_port *ap = ata_shost_to_port(shost);
323 struct ahci_host_priv *hpriv = ap->host->private_data;
324 void __iomem *mmio = hpriv->mmio;
325 void __iomem *em_mmio = mmio + hpriv->em_loc;
326 const unsigned char *msg_buf = buf;
331 /* check size validity */
332 if (!(ap->flags & ATA_FLAG_EM) ||
333 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
334 size % 4 || size > hpriv->em_buf_sz)
337 spin_lock_irqsave(ap->lock, flags);
339 em_ctl = readl(mmio + HOST_EM_CTL);
340 if (em_ctl & EM_CTL_TM) {
341 spin_unlock_irqrestore(ap->lock, flags);
345 for (i = 0; i < size; i += 4) {
346 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
347 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
348 writel(msg, em_mmio + i);
351 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
353 spin_unlock_irqrestore(ap->lock, flags);
358 static ssize_t ahci_show_em_supported(struct device *dev,
359 struct device_attribute *attr, char *buf)
361 struct Scsi_Host *shost = class_to_shost(dev);
362 struct ata_port *ap = ata_shost_to_port(shost);
363 struct ahci_host_priv *hpriv = ap->host->private_data;
364 void __iomem *mmio = hpriv->mmio;
367 em_ctl = readl(mmio + HOST_EM_CTL);
369 return sprintf(buf, "%s%s%s%s\n",
370 em_ctl & EM_CTL_LED ? "led " : "",
371 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
372 em_ctl & EM_CTL_SES ? "ses-2 " : "",
373 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
377 * ahci_save_initial_config - Save and fixup initial config values
378 * @dev: target AHCI device
379 * @hpriv: host private area to store config values
380 * @force_port_map: force port map to a specified value
381 * @mask_port_map: mask out particular bits from port map
383 * Some registers containing configuration info might be setup by
384 * BIOS and might be cleared on reset. This function saves the
385 * initial values of those registers into @hpriv such that they
386 * can be restored after controller reset.
388 * If inconsistent, config values are fixed up by this function.
393 void ahci_save_initial_config(struct device *dev,
394 struct ahci_host_priv *hpriv,
395 unsigned int force_port_map,
396 unsigned int mask_port_map)
398 void __iomem *mmio = hpriv->mmio;
399 u32 cap, cap2, vers, port_map;
402 /* make sure AHCI mode is enabled before accessing CAP */
403 ahci_enable_ahci(mmio);
405 /* Values prefixed with saved_ are written back to host after
406 * reset. Values without are used for driver operation.
408 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
409 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
411 /* CAP2 register is only defined for AHCI 1.2 and later */
412 vers = readl(mmio + HOST_VERSION);
413 if ((vers >> 16) > 1 ||
414 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
415 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
417 hpriv->saved_cap2 = cap2 = 0;
419 /* some chips have errata preventing 64bit use */
420 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
421 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
425 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
426 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
427 cap &= ~HOST_CAP_NCQ;
430 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
431 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
435 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
436 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
437 cap &= ~HOST_CAP_PMP;
440 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
442 "controller can't do SNTF, turning off CAP_SNTF\n");
443 cap &= ~HOST_CAP_SNTF;
446 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
447 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
451 if (force_port_map && port_map != force_port_map) {
452 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
453 port_map, force_port_map);
454 port_map = force_port_map;
458 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
460 port_map & mask_port_map);
461 port_map &= mask_port_map;
464 /* cross check port_map and cap.n_ports */
468 for (i = 0; i < AHCI_MAX_PORTS; i++)
469 if (port_map & (1 << i))
472 /* If PI has more ports than n_ports, whine, clear
473 * port_map and let it be generated from n_ports.
475 if (map_ports > ahci_nr_ports(cap)) {
477 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
478 port_map, ahci_nr_ports(cap));
483 /* fabricate port_map from cap.nr_ports */
485 port_map = (1 << ahci_nr_ports(cap)) - 1;
486 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
488 /* write the fixed up value to the PI register */
489 hpriv->saved_port_map = port_map;
492 /* record values to use during operation */
495 hpriv->port_map = port_map;
497 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
500 * ahci_restore_initial_config - Restore initial config
501 * @host: target ATA host
503 * Restore initial config stored by ahci_save_initial_config().
508 static void ahci_restore_initial_config(struct ata_host *host)
510 struct ahci_host_priv *hpriv = host->private_data;
511 void __iomem *mmio = hpriv->mmio;
513 writel(hpriv->saved_cap, mmio + HOST_CAP);
514 if (hpriv->saved_cap2)
515 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
516 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
517 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
520 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
522 static const int offset[] = {
523 [SCR_STATUS] = PORT_SCR_STAT,
524 [SCR_CONTROL] = PORT_SCR_CTL,
525 [SCR_ERROR] = PORT_SCR_ERR,
526 [SCR_ACTIVE] = PORT_SCR_ACT,
527 [SCR_NOTIFICATION] = PORT_SCR_NTF,
529 struct ahci_host_priv *hpriv = ap->host->private_data;
531 if (sc_reg < ARRAY_SIZE(offset) &&
532 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
533 return offset[sc_reg];
537 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
539 void __iomem *port_mmio = ahci_port_base(link->ap);
540 int offset = ahci_scr_offset(link->ap, sc_reg);
543 *val = readl(port_mmio + offset);
549 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
551 void __iomem *port_mmio = ahci_port_base(link->ap);
552 int offset = ahci_scr_offset(link->ap, sc_reg);
555 writel(val, port_mmio + offset);
561 void ahci_start_engine(struct ata_port *ap)
563 void __iomem *port_mmio = ahci_port_base(ap);
567 tmp = readl(port_mmio + PORT_CMD);
568 tmp |= PORT_CMD_START;
569 writel(tmp, port_mmio + PORT_CMD);
570 readl(port_mmio + PORT_CMD); /* flush */
572 EXPORT_SYMBOL_GPL(ahci_start_engine);
574 int ahci_stop_engine(struct ata_port *ap)
576 void __iomem *port_mmio = ahci_port_base(ap);
579 tmp = readl(port_mmio + PORT_CMD);
581 /* check if the HBA is idle */
582 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
585 /* setting HBA to idle */
586 tmp &= ~PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
589 /* wait for engine to stop. This could be as long as 500 msec */
590 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
591 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
592 if (tmp & PORT_CMD_LIST_ON)
597 EXPORT_SYMBOL_GPL(ahci_stop_engine);
599 static void ahci_start_fis_rx(struct ata_port *ap)
601 void __iomem *port_mmio = ahci_port_base(ap);
602 struct ahci_host_priv *hpriv = ap->host->private_data;
603 struct ahci_port_priv *pp = ap->private_data;
606 /* set FIS registers */
607 if (hpriv->cap & HOST_CAP_64)
608 writel((pp->cmd_slot_dma >> 16) >> 16,
609 port_mmio + PORT_LST_ADDR_HI);
610 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
612 if (hpriv->cap & HOST_CAP_64)
613 writel((pp->rx_fis_dma >> 16) >> 16,
614 port_mmio + PORT_FIS_ADDR_HI);
615 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
617 /* enable FIS reception */
618 tmp = readl(port_mmio + PORT_CMD);
619 tmp |= PORT_CMD_FIS_RX;
620 writel(tmp, port_mmio + PORT_CMD);
623 readl(port_mmio + PORT_CMD);
626 static int ahci_stop_fis_rx(struct ata_port *ap)
628 void __iomem *port_mmio = ahci_port_base(ap);
631 /* disable FIS reception */
632 tmp = readl(port_mmio + PORT_CMD);
633 tmp &= ~PORT_CMD_FIS_RX;
634 writel(tmp, port_mmio + PORT_CMD);
636 /* wait for completion, spec says 500ms, give it 1000 */
637 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
638 PORT_CMD_FIS_ON, 10, 1000);
639 if (tmp & PORT_CMD_FIS_ON)
645 static void ahci_power_up(struct ata_port *ap)
647 struct ahci_host_priv *hpriv = ap->host->private_data;
648 void __iomem *port_mmio = ahci_port_base(ap);
651 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
654 if (hpriv->cap & HOST_CAP_SSS) {
655 cmd |= PORT_CMD_SPIN_UP;
656 writel(cmd, port_mmio + PORT_CMD);
660 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
663 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
666 struct ata_port *ap = link->ap;
667 struct ahci_host_priv *hpriv = ap->host->private_data;
668 struct ahci_port_priv *pp = ap->private_data;
669 void __iomem *port_mmio = ahci_port_base(ap);
671 if (policy != ATA_LPM_MAX_POWER) {
673 * Disable interrupts on Phy Ready. This keeps us from
674 * getting woken up due to spurious phy ready
677 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
678 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
680 sata_link_scr_lpm(link, policy, false);
683 if (hpriv->cap & HOST_CAP_ALPM) {
684 u32 cmd = readl(port_mmio + PORT_CMD);
686 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
687 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
688 cmd |= PORT_CMD_ICC_ACTIVE;
690 writel(cmd, port_mmio + PORT_CMD);
691 readl(port_mmio + PORT_CMD);
693 /* wait 10ms to be sure we've come out of LPM state */
696 cmd |= PORT_CMD_ALPE;
697 if (policy == ATA_LPM_MIN_POWER)
700 /* write out new cmd value */
701 writel(cmd, port_mmio + PORT_CMD);
705 if (policy == ATA_LPM_MAX_POWER) {
706 sata_link_scr_lpm(link, policy, false);
708 /* turn PHYRDY IRQ back on */
709 pp->intr_mask |= PORT_IRQ_PHYRDY;
710 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
717 static void ahci_power_down(struct ata_port *ap)
719 struct ahci_host_priv *hpriv = ap->host->private_data;
720 void __iomem *port_mmio = ahci_port_base(ap);
723 if (!(hpriv->cap & HOST_CAP_SSS))
726 /* put device into listen mode, first set PxSCTL.DET to 0 */
727 scontrol = readl(port_mmio + PORT_SCR_CTL);
729 writel(scontrol, port_mmio + PORT_SCR_CTL);
731 /* then set PxCMD.SUD to 0 */
732 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
733 cmd &= ~PORT_CMD_SPIN_UP;
734 writel(cmd, port_mmio + PORT_CMD);
738 static void ahci_start_port(struct ata_port *ap)
740 struct ahci_port_priv *pp = ap->private_data;
741 struct ata_link *link;
742 struct ahci_em_priv *emp;
746 /* enable FIS reception */
747 ahci_start_fis_rx(ap);
750 ahci_start_engine(ap);
753 if (ap->flags & ATA_FLAG_EM) {
754 ata_for_each_link(link, ap, EDGE) {
755 emp = &pp->em_priv[link->pmp];
757 /* EM Transmit bit maybe busy during init */
758 for (i = 0; i < EM_MAX_RETRY; i++) {
759 rc = ahci_transmit_led_message(ap,
770 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
771 ata_for_each_link(link, ap, EDGE)
772 ahci_init_sw_activity(link);
776 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
781 rc = ahci_stop_engine(ap);
783 *emsg = "failed to stop engine";
787 /* disable FIS reception */
788 rc = ahci_stop_fis_rx(ap);
790 *emsg = "failed stop FIS RX";
797 int ahci_reset_controller(struct ata_host *host)
799 struct ahci_host_priv *hpriv = host->private_data;
800 void __iomem *mmio = hpriv->mmio;
803 /* we must be in AHCI mode, before using anything
804 * AHCI-specific, such as HOST_RESET.
806 ahci_enable_ahci(mmio);
808 /* global controller reset */
809 if (!ahci_skip_host_reset) {
810 tmp = readl(mmio + HOST_CTL);
811 if ((tmp & HOST_RESET) == 0) {
812 writel(tmp | HOST_RESET, mmio + HOST_CTL);
813 readl(mmio + HOST_CTL); /* flush */
817 * to perform host reset, OS should set HOST_RESET
818 * and poll until this bit is read to be "0".
819 * reset must complete within 1 second, or
820 * the hardware should be considered fried.
822 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
823 HOST_RESET, 10, 1000);
825 if (tmp & HOST_RESET) {
826 dev_err(host->dev, "controller reset failed (0x%x)\n",
831 /* turn on AHCI mode */
832 ahci_enable_ahci(mmio);
834 /* Some registers might be cleared on reset. Restore
837 ahci_restore_initial_config(host);
839 dev_info(host->dev, "skipping global host reset\n");
843 EXPORT_SYMBOL_GPL(ahci_reset_controller);
845 static void ahci_sw_activity(struct ata_link *link)
847 struct ata_port *ap = link->ap;
848 struct ahci_port_priv *pp = ap->private_data;
849 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
851 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
855 if (!timer_pending(&emp->timer))
856 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
859 static void ahci_sw_activity_blink(unsigned long arg)
861 struct ata_link *link = (struct ata_link *)arg;
862 struct ata_port *ap = link->ap;
863 struct ahci_port_priv *pp = ap->private_data;
864 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
865 unsigned long led_message = emp->led_state;
866 u32 activity_led_state;
869 led_message &= EM_MSG_LED_VALUE;
870 led_message |= ap->port_no | (link->pmp << 8);
872 /* check to see if we've had activity. If so,
873 * toggle state of LED and reset timer. If not,
874 * turn LED to desired idle state.
876 spin_lock_irqsave(ap->lock, flags);
877 if (emp->saved_activity != emp->activity) {
878 emp->saved_activity = emp->activity;
879 /* get the current LED state */
880 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
882 if (activity_led_state)
883 activity_led_state = 0;
885 activity_led_state = 1;
887 /* clear old state */
888 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
891 led_message |= (activity_led_state << 16);
892 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
895 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
896 if (emp->blink_policy == BLINK_OFF)
897 led_message |= (1 << 16);
899 spin_unlock_irqrestore(ap->lock, flags);
900 ahci_transmit_led_message(ap, led_message, 4);
903 static void ahci_init_sw_activity(struct ata_link *link)
905 struct ata_port *ap = link->ap;
906 struct ahci_port_priv *pp = ap->private_data;
907 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
909 /* init activity stats, setup timer */
910 emp->saved_activity = emp->activity = 0;
911 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
913 /* check our blink policy and set flag for link if it's enabled */
914 if (emp->blink_policy)
915 link->flags |= ATA_LFLAG_SW_ACTIVITY;
918 int ahci_reset_em(struct ata_host *host)
920 struct ahci_host_priv *hpriv = host->private_data;
921 void __iomem *mmio = hpriv->mmio;
924 em_ctl = readl(mmio + HOST_EM_CTL);
925 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
928 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
931 EXPORT_SYMBOL_GPL(ahci_reset_em);
933 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
936 struct ahci_host_priv *hpriv = ap->host->private_data;
937 struct ahci_port_priv *pp = ap->private_data;
938 void __iomem *mmio = hpriv->mmio;
940 u32 message[] = {0, 0};
943 struct ahci_em_priv *emp;
945 /* get the slot number from the message */
946 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
947 if (pmp < EM_MAX_SLOTS)
948 emp = &pp->em_priv[pmp];
952 spin_lock_irqsave(ap->lock, flags);
955 * if we are still busy transmitting a previous message,
958 em_ctl = readl(mmio + HOST_EM_CTL);
959 if (em_ctl & EM_CTL_TM) {
960 spin_unlock_irqrestore(ap->lock, flags);
964 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
966 * create message header - this is all zero except for
967 * the message size, which is 4 bytes.
969 message[0] |= (4 << 8);
971 /* ignore 0:4 of byte zero, fill in port info yourself */
972 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
974 /* write message to EM_LOC */
975 writel(message[0], mmio + hpriv->em_loc);
976 writel(message[1], mmio + hpriv->em_loc+4);
979 * tell hardware to transmit the message
981 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
984 /* save off new led state for port/slot */
985 emp->led_state = state;
987 spin_unlock_irqrestore(ap->lock, flags);
991 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
993 struct ahci_port_priv *pp = ap->private_data;
994 struct ata_link *link;
995 struct ahci_em_priv *emp;
998 ata_for_each_link(link, ap, EDGE) {
999 emp = &pp->em_priv[link->pmp];
1000 rc += sprintf(buf, "%lx\n", emp->led_state);
1005 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1010 struct ahci_port_priv *pp = ap->private_data;
1011 struct ahci_em_priv *emp;
1013 state = simple_strtoul(buf, NULL, 0);
1015 /* get the slot number from the message */
1016 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1017 if (pmp < EM_MAX_SLOTS)
1018 emp = &pp->em_priv[pmp];
1022 /* mask off the activity bits if we are in sw_activity
1023 * mode, user should turn off sw_activity before setting
1024 * activity led through em_message
1026 if (emp->blink_policy)
1027 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1029 return ahci_transmit_led_message(ap, state, size);
1032 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1034 struct ata_link *link = dev->link;
1035 struct ata_port *ap = link->ap;
1036 struct ahci_port_priv *pp = ap->private_data;
1037 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1038 u32 port_led_state = emp->led_state;
1040 /* save the desired Activity LED behavior */
1043 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1045 /* set the LED to OFF */
1046 port_led_state &= EM_MSG_LED_VALUE_OFF;
1047 port_led_state |= (ap->port_no | (link->pmp << 8));
1048 ahci_transmit_led_message(ap, port_led_state, 4);
1050 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1051 if (val == BLINK_OFF) {
1052 /* set LED to ON for idle */
1053 port_led_state &= EM_MSG_LED_VALUE_OFF;
1054 port_led_state |= (ap->port_no | (link->pmp << 8));
1055 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1056 ahci_transmit_led_message(ap, port_led_state, 4);
1059 emp->blink_policy = val;
1063 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1065 struct ata_link *link = dev->link;
1066 struct ata_port *ap = link->ap;
1067 struct ahci_port_priv *pp = ap->private_data;
1068 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1070 /* display the saved value of activity behavior for this
1073 return sprintf(buf, "%d\n", emp->blink_policy);
1076 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1077 int port_no, void __iomem *mmio,
1078 void __iomem *port_mmio)
1080 const char *emsg = NULL;
1084 /* make sure port is not active */
1085 rc = ahci_deinit_port(ap, &emsg);
1087 dev_warn(dev, "%s (%d)\n", emsg, rc);
1090 tmp = readl(port_mmio + PORT_SCR_ERR);
1091 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1092 writel(tmp, port_mmio + PORT_SCR_ERR);
1094 /* clear port IRQ */
1095 tmp = readl(port_mmio + PORT_IRQ_STAT);
1096 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1098 writel(tmp, port_mmio + PORT_IRQ_STAT);
1100 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1103 void ahci_init_controller(struct ata_host *host)
1105 struct ahci_host_priv *hpriv = host->private_data;
1106 void __iomem *mmio = hpriv->mmio;
1108 void __iomem *port_mmio;
1111 for (i = 0; i < host->n_ports; i++) {
1112 struct ata_port *ap = host->ports[i];
1114 port_mmio = ahci_port_base(ap);
1115 if (ata_port_is_dummy(ap))
1118 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1121 tmp = readl(mmio + HOST_CTL);
1122 VPRINTK("HOST_CTL 0x%x\n", tmp);
1123 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1124 tmp = readl(mmio + HOST_CTL);
1125 VPRINTK("HOST_CTL 0x%x\n", tmp);
1127 EXPORT_SYMBOL_GPL(ahci_init_controller);
1129 static void ahci_dev_config(struct ata_device *dev)
1131 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1133 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1134 dev->max_sectors = 255;
1136 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1140 static unsigned int ahci_dev_classify(struct ata_port *ap)
1142 void __iomem *port_mmio = ahci_port_base(ap);
1143 struct ata_taskfile tf;
1146 tmp = readl(port_mmio + PORT_SIG);
1147 tf.lbah = (tmp >> 24) & 0xff;
1148 tf.lbam = (tmp >> 16) & 0xff;
1149 tf.lbal = (tmp >> 8) & 0xff;
1150 tf.nsect = (tmp) & 0xff;
1152 return ata_dev_classify(&tf);
1155 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1158 dma_addr_t cmd_tbl_dma;
1160 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1162 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1163 pp->cmd_slot[tag].status = 0;
1164 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1165 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1167 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1169 int ahci_kick_engine(struct ata_port *ap)
1171 void __iomem *port_mmio = ahci_port_base(ap);
1172 struct ahci_host_priv *hpriv = ap->host->private_data;
1173 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1178 rc = ahci_stop_engine(ap);
1183 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1185 busy = status & (ATA_BUSY | ATA_DRQ);
1186 if (!busy && !sata_pmp_attached(ap)) {
1191 if (!(hpriv->cap & HOST_CAP_CLO)) {
1197 tmp = readl(port_mmio + PORT_CMD);
1198 tmp |= PORT_CMD_CLO;
1199 writel(tmp, port_mmio + PORT_CMD);
1202 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1203 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1204 if (tmp & PORT_CMD_CLO)
1207 /* restart engine */
1209 ahci_start_engine(ap);
1212 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1214 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1215 struct ata_taskfile *tf, int is_cmd, u16 flags,
1216 unsigned long timeout_msec)
1218 const u32 cmd_fis_len = 5; /* five dwords */
1219 struct ahci_port_priv *pp = ap->private_data;
1220 void __iomem *port_mmio = ahci_port_base(ap);
1221 u8 *fis = pp->cmd_tbl;
1224 /* prep the command */
1225 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1226 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1229 writel(1, port_mmio + PORT_CMD_ISSUE);
1232 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1233 0x1, 0x1, 1, timeout_msec);
1235 ahci_kick_engine(ap);
1239 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1244 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1245 int pmp, unsigned long deadline,
1246 int (*check_ready)(struct ata_link *link))
1248 struct ata_port *ap = link->ap;
1249 struct ahci_host_priv *hpriv = ap->host->private_data;
1250 struct ahci_port_priv *pp = ap->private_data;
1251 const char *reason = NULL;
1252 unsigned long now, msecs;
1253 struct ata_taskfile tf;
1254 bool fbs_disabled = false;
1259 /* prepare for SRST (AHCI-1.1 10.4.1) */
1260 rc = ahci_kick_engine(ap);
1261 if (rc && rc != -EOPNOTSUPP)
1262 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1265 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1266 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1267 * that is attached to port multiplier.
1269 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1270 ahci_disable_fbs(ap);
1271 fbs_disabled = true;
1274 ata_tf_init(link->device, &tf);
1276 /* issue the first D2H Register FIS */
1279 if (time_after(deadline, now))
1280 msecs = jiffies_to_msecs(deadline - now);
1283 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1284 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1286 reason = "1st FIS failed";
1290 /* spec says at least 5us, but be generous and sleep for 1ms */
1293 /* issue the second D2H Register FIS */
1294 tf.ctl &= ~ATA_SRST;
1295 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1297 /* wait for link to become ready */
1298 rc = ata_wait_after_reset(link, deadline, check_ready);
1299 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1301 * Workaround for cases where link online status can't
1302 * be trusted. Treat device readiness timeout as link
1305 ata_link_info(link, "device not ready, treating as offline\n");
1306 *class = ATA_DEV_NONE;
1308 /* link occupied, -ENODEV too is an error */
1309 reason = "device not ready";
1312 *class = ahci_dev_classify(ap);
1314 /* re-enable FBS if disabled before */
1316 ahci_enable_fbs(ap);
1318 DPRINTK("EXIT, class=%u\n", *class);
1322 ata_link_err(link, "softreset failed (%s)\n", reason);
1326 int ahci_check_ready(struct ata_link *link)
1328 void __iomem *port_mmio = ahci_port_base(link->ap);
1329 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1331 return ata_check_ready(status);
1333 EXPORT_SYMBOL_GPL(ahci_check_ready);
1335 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1336 unsigned long deadline)
1338 int pmp = sata_srst_pmp(link);
1342 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1344 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1346 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1348 void __iomem *port_mmio = ahci_port_base(link->ap);
1349 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1350 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1353 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1354 * which can save timeout delay.
1356 if (irq_status & PORT_IRQ_BAD_PMP)
1359 return ata_check_ready(status);
1362 int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1363 unsigned long deadline)
1365 struct ata_port *ap = link->ap;
1366 void __iomem *port_mmio = ahci_port_base(ap);
1367 int pmp = sata_srst_pmp(link);
1373 rc = ahci_do_softreset(link, class, pmp, deadline,
1374 ahci_bad_pmp_check_ready);
1377 * Soft reset fails with IPMS set when PMP is enabled but
1378 * SATA HDD/ODD is connected to SATA port, do soft reset
1382 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1383 if (irq_sts & PORT_IRQ_BAD_PMP) {
1384 ata_link_printk(link, KERN_WARNING,
1385 "applying PMP SRST workaround "
1387 rc = ahci_do_softreset(link, class, 0, deadline,
1395 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1396 unsigned long deadline)
1398 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1399 struct ata_port *ap = link->ap;
1400 struct ahci_port_priv *pp = ap->private_data;
1401 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1402 struct ata_taskfile tf;
1408 ahci_stop_engine(ap);
1410 /* clear D2H reception area to properly wait for D2H FIS */
1411 ata_tf_init(link->device, &tf);
1413 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1415 rc = sata_link_hardreset(link, timing, deadline, &online,
1418 ahci_start_engine(ap);
1421 *class = ahci_dev_classify(ap);
1423 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1427 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1429 struct ata_port *ap = link->ap;
1430 void __iomem *port_mmio = ahci_port_base(ap);
1433 ata_std_postreset(link, class);
1435 /* Make sure port's ATAPI bit is set appropriately */
1436 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1437 if (*class == ATA_DEV_ATAPI)
1438 new_tmp |= PORT_CMD_ATAPI;
1440 new_tmp &= ~PORT_CMD_ATAPI;
1441 if (new_tmp != tmp) {
1442 writel(new_tmp, port_mmio + PORT_CMD);
1443 readl(port_mmio + PORT_CMD); /* flush */
1447 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1449 struct scatterlist *sg;
1450 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1456 * Next, the S/G list.
1458 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1459 dma_addr_t addr = sg_dma_address(sg);
1460 u32 sg_len = sg_dma_len(sg);
1462 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1463 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1464 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1470 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1472 struct ata_port *ap = qc->ap;
1473 struct ahci_port_priv *pp = ap->private_data;
1475 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1476 return ata_std_qc_defer(qc);
1478 return sata_pmp_qc_defer_cmd_switch(qc);
1481 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1483 struct ata_port *ap = qc->ap;
1484 struct ahci_port_priv *pp = ap->private_data;
1485 int is_atapi = ata_is_atapi(qc->tf.protocol);
1488 const u32 cmd_fis_len = 5; /* five dwords */
1489 unsigned int n_elem;
1492 * Fill in command table information. First, the header,
1493 * a SATA Register - Host to Device command FIS.
1495 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1497 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1499 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1500 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1504 if (qc->flags & ATA_QCFLAG_DMAMAP)
1505 n_elem = ahci_fill_sg(qc, cmd_tbl);
1508 * Fill in command slot information.
1510 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1511 if (qc->tf.flags & ATA_TFLAG_WRITE)
1512 opts |= AHCI_CMD_WRITE;
1514 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1516 ahci_fill_cmd_slot(pp, qc->tag, opts);
1519 static void ahci_fbs_dec_intr(struct ata_port *ap)
1521 struct ahci_port_priv *pp = ap->private_data;
1522 void __iomem *port_mmio = ahci_port_base(ap);
1523 u32 fbs = readl(port_mmio + PORT_FBS);
1527 BUG_ON(!pp->fbs_enabled);
1529 /* time to wait for DEC is not specified by AHCI spec,
1530 * add a retry loop for safety.
1532 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1533 fbs = readl(port_mmio + PORT_FBS);
1534 while ((fbs & PORT_FBS_DEC) && retries--) {
1536 fbs = readl(port_mmio + PORT_FBS);
1539 if (fbs & PORT_FBS_DEC)
1540 dev_err(ap->host->dev, "failed to clear device error\n");
1543 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1545 struct ahci_host_priv *hpriv = ap->host->private_data;
1546 struct ahci_port_priv *pp = ap->private_data;
1547 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1548 struct ata_link *link = NULL;
1549 struct ata_queued_cmd *active_qc;
1550 struct ata_eh_info *active_ehi;
1551 bool fbs_need_dec = false;
1554 /* determine active link with error */
1555 if (pp->fbs_enabled) {
1556 void __iomem *port_mmio = ahci_port_base(ap);
1557 u32 fbs = readl(port_mmio + PORT_FBS);
1558 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1560 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1561 link = &ap->pmp_link[pmp];
1562 fbs_need_dec = true;
1566 ata_for_each_link(link, ap, EDGE)
1567 if (ata_link_active(link))
1573 active_qc = ata_qc_from_tag(ap, link->active_tag);
1574 active_ehi = &link->eh_info;
1576 /* record irq stat */
1577 ata_ehi_clear_desc(host_ehi);
1578 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1580 /* AHCI needs SError cleared; otherwise, it might lock up */
1581 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1582 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1583 host_ehi->serror |= serror;
1585 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1586 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1587 irq_stat &= ~PORT_IRQ_IF_ERR;
1589 if (irq_stat & PORT_IRQ_TF_ERR) {
1590 /* If qc is active, charge it; otherwise, the active
1591 * link. There's no active qc on NCQ errors. It will
1592 * be determined by EH by reading log page 10h.
1595 active_qc->err_mask |= AC_ERR_DEV;
1597 active_ehi->err_mask |= AC_ERR_DEV;
1599 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1600 host_ehi->serror &= ~SERR_INTERNAL;
1603 if (irq_stat & PORT_IRQ_UNK_FIS) {
1604 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1606 active_ehi->err_mask |= AC_ERR_HSM;
1607 active_ehi->action |= ATA_EH_RESET;
1608 ata_ehi_push_desc(active_ehi,
1609 "unknown FIS %08x %08x %08x %08x" ,
1610 unk[0], unk[1], unk[2], unk[3]);
1613 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1614 active_ehi->err_mask |= AC_ERR_HSM;
1615 active_ehi->action |= ATA_EH_RESET;
1616 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1619 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1620 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1621 host_ehi->action |= ATA_EH_RESET;
1622 ata_ehi_push_desc(host_ehi, "host bus error");
1625 if (irq_stat & PORT_IRQ_IF_ERR) {
1627 active_ehi->err_mask |= AC_ERR_DEV;
1629 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1630 host_ehi->action |= ATA_EH_RESET;
1633 ata_ehi_push_desc(host_ehi, "interface fatal error");
1636 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1637 ata_ehi_hotplugged(host_ehi);
1638 ata_ehi_push_desc(host_ehi, "%s",
1639 irq_stat & PORT_IRQ_CONNECT ?
1640 "connection status changed" : "PHY RDY changed");
1643 /* okay, let's hand over to EH */
1645 if (irq_stat & PORT_IRQ_FREEZE)
1646 ata_port_freeze(ap);
1647 else if (fbs_need_dec) {
1648 ata_link_abort(link);
1649 ahci_fbs_dec_intr(ap);
1654 static void ahci_port_intr(struct ata_port *ap)
1656 void __iomem *port_mmio = ahci_port_base(ap);
1657 struct ata_eh_info *ehi = &ap->link.eh_info;
1658 struct ahci_port_priv *pp = ap->private_data;
1659 struct ahci_host_priv *hpriv = ap->host->private_data;
1660 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1661 u32 status, qc_active = 0;
1664 status = readl(port_mmio + PORT_IRQ_STAT);
1665 writel(status, port_mmio + PORT_IRQ_STAT);
1667 /* ignore BAD_PMP while resetting */
1668 if (unlikely(resetting))
1669 status &= ~PORT_IRQ_BAD_PMP;
1671 /* if LPM is enabled, PHYRDY doesn't mean anything */
1672 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
1673 status &= ~PORT_IRQ_PHYRDY;
1674 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1677 if (unlikely(status & PORT_IRQ_ERROR)) {
1678 ahci_error_intr(ap, status);
1682 if (status & PORT_IRQ_SDB_FIS) {
1683 /* If SNotification is available, leave notification
1684 * handling to sata_async_notification(). If not,
1685 * emulate it by snooping SDB FIS RX area.
1687 * Snooping FIS RX area is probably cheaper than
1688 * poking SNotification but some constrollers which
1689 * implement SNotification, ICH9 for example, don't
1690 * store AN SDB FIS into receive area.
1692 if (hpriv->cap & HOST_CAP_SNTF)
1693 sata_async_notification(ap);
1695 /* If the 'N' bit in word 0 of the FIS is set,
1696 * we just received asynchronous notification.
1697 * Tell libata about it.
1699 * Lack of SNotification should not appear in
1700 * ahci 1.2, so the workaround is unnecessary
1701 * when FBS is enabled.
1703 if (pp->fbs_enabled)
1706 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1707 u32 f0 = le32_to_cpu(f[0]);
1709 sata_async_notification(ap);
1714 /* pp->active_link is not reliable once FBS is enabled, both
1715 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1716 * NCQ and non-NCQ commands may be in flight at the same time.
1718 if (pp->fbs_enabled) {
1719 if (ap->qc_active) {
1720 qc_active = readl(port_mmio + PORT_SCR_ACT);
1721 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1724 /* pp->active_link is valid iff any command is in flight */
1725 if (ap->qc_active && pp->active_link->sactive)
1726 qc_active = readl(port_mmio + PORT_SCR_ACT);
1728 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1732 rc = ata_qc_complete_multiple(ap, qc_active);
1734 /* while resetting, invalid completions are expected */
1735 if (unlikely(rc < 0 && !resetting)) {
1736 ehi->err_mask |= AC_ERR_HSM;
1737 ehi->action |= ATA_EH_RESET;
1738 ata_port_freeze(ap);
1742 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1744 struct ata_host *host = dev_instance;
1745 struct ahci_host_priv *hpriv;
1746 unsigned int i, handled = 0;
1748 u32 irq_stat, irq_masked;
1752 hpriv = host->private_data;
1755 /* sigh. 0xffffffff is a valid return from h/w */
1756 irq_stat = readl(mmio + HOST_IRQ_STAT);
1760 irq_masked = irq_stat & hpriv->port_map;
1762 spin_lock(&host->lock);
1764 for (i = 0; i < host->n_ports; i++) {
1765 struct ata_port *ap;
1767 if (!(irq_masked & (1 << i)))
1770 ap = host->ports[i];
1773 VPRINTK("port %u\n", i);
1775 VPRINTK("port %u (no irq)\n", i);
1776 if (ata_ratelimit())
1778 "interrupt on disabled port %u\n", i);
1784 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1785 * it should be cleared after all the port events are cleared;
1786 * otherwise, it will raise a spurious interrupt after each
1787 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1790 * Also, use the unmasked value to clear interrupt as spurious
1791 * pending event on a dummy port might cause screaming IRQ.
1793 writel(irq_stat, mmio + HOST_IRQ_STAT);
1795 spin_unlock(&host->lock);
1799 return IRQ_RETVAL(handled);
1801 EXPORT_SYMBOL_GPL(ahci_interrupt);
1803 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1805 struct ata_port *ap = qc->ap;
1806 void __iomem *port_mmio = ahci_port_base(ap);
1807 struct ahci_port_priv *pp = ap->private_data;
1809 /* Keep track of the currently active link. It will be used
1810 * in completion path to determine whether NCQ phase is in
1813 pp->active_link = qc->dev->link;
1815 if (qc->tf.protocol == ATA_PROT_NCQ)
1816 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1818 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1819 u32 fbs = readl(port_mmio + PORT_FBS);
1820 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1821 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1822 writel(fbs, port_mmio + PORT_FBS);
1823 pp->fbs_last_dev = qc->dev->link->pmp;
1826 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1828 ahci_sw_activity(qc->dev->link);
1833 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1835 struct ahci_port_priv *pp = qc->ap->private_data;
1836 u8 *rx_fis = pp->rx_fis;
1838 if (pp->fbs_enabled)
1839 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1842 * After a successful execution of an ATA PIO data-in command,
1843 * the device doesn't send D2H Reg FIS to update the TF and
1844 * the host should take TF and E_Status from the preceding PIO
1847 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1848 !(qc->flags & ATA_QCFLAG_FAILED)) {
1849 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1850 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1852 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1857 static void ahci_freeze(struct ata_port *ap)
1859 void __iomem *port_mmio = ahci_port_base(ap);
1862 writel(0, port_mmio + PORT_IRQ_MASK);
1865 static void ahci_thaw(struct ata_port *ap)
1867 struct ahci_host_priv *hpriv = ap->host->private_data;
1868 void __iomem *mmio = hpriv->mmio;
1869 void __iomem *port_mmio = ahci_port_base(ap);
1871 struct ahci_port_priv *pp = ap->private_data;
1874 tmp = readl(port_mmio + PORT_IRQ_STAT);
1875 writel(tmp, port_mmio + PORT_IRQ_STAT);
1876 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1878 /* turn IRQ back on */
1879 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1882 static void ahci_error_handler(struct ata_port *ap)
1884 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1885 /* restart engine */
1886 ahci_stop_engine(ap);
1887 ahci_start_engine(ap);
1890 sata_pmp_error_handler(ap);
1892 if (!ata_dev_enabled(ap->link.device))
1893 ahci_stop_engine(ap);
1896 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1898 struct ata_port *ap = qc->ap;
1900 /* make DMA engine forget about the failed command */
1901 if (qc->flags & ATA_QCFLAG_FAILED)
1902 ahci_kick_engine(ap);
1905 static void ahci_enable_fbs(struct ata_port *ap)
1907 struct ahci_port_priv *pp = ap->private_data;
1908 void __iomem *port_mmio = ahci_port_base(ap);
1912 if (!pp->fbs_supported)
1915 fbs = readl(port_mmio + PORT_FBS);
1916 if (fbs & PORT_FBS_EN) {
1917 pp->fbs_enabled = true;
1918 pp->fbs_last_dev = -1; /* initialization */
1922 rc = ahci_stop_engine(ap);
1926 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1927 fbs = readl(port_mmio + PORT_FBS);
1928 if (fbs & PORT_FBS_EN) {
1929 dev_info(ap->host->dev, "FBS is enabled\n");
1930 pp->fbs_enabled = true;
1931 pp->fbs_last_dev = -1; /* initialization */
1933 dev_err(ap->host->dev, "Failed to enable FBS\n");
1935 ahci_start_engine(ap);
1938 static void ahci_disable_fbs(struct ata_port *ap)
1940 struct ahci_port_priv *pp = ap->private_data;
1941 void __iomem *port_mmio = ahci_port_base(ap);
1945 if (!pp->fbs_supported)
1948 fbs = readl(port_mmio + PORT_FBS);
1949 if ((fbs & PORT_FBS_EN) == 0) {
1950 pp->fbs_enabled = false;
1954 rc = ahci_stop_engine(ap);
1958 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1959 fbs = readl(port_mmio + PORT_FBS);
1960 if (fbs & PORT_FBS_EN)
1961 dev_err(ap->host->dev, "Failed to disable FBS\n");
1963 dev_info(ap->host->dev, "FBS is disabled\n");
1964 pp->fbs_enabled = false;
1967 ahci_start_engine(ap);
1970 static void ahci_pmp_attach(struct ata_port *ap)
1972 void __iomem *port_mmio = ahci_port_base(ap);
1973 struct ahci_port_priv *pp = ap->private_data;
1976 cmd = readl(port_mmio + PORT_CMD);
1977 cmd |= PORT_CMD_PMP;
1978 writel(cmd, port_mmio + PORT_CMD);
1980 ahci_enable_fbs(ap);
1982 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1985 * We must not change the port interrupt mask register if the
1986 * port is marked frozen, the value in pp->intr_mask will be
1987 * restored later when the port is thawed.
1989 * Note that during initialization, the port is marked as
1990 * frozen since the irq handler is not yet registered.
1992 if (!(ap->pflags & ATA_PFLAG_FROZEN))
1993 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1996 static void ahci_pmp_detach(struct ata_port *ap)
1998 void __iomem *port_mmio = ahci_port_base(ap);
1999 struct ahci_port_priv *pp = ap->private_data;
2002 ahci_disable_fbs(ap);
2004 cmd = readl(port_mmio + PORT_CMD);
2005 cmd &= ~PORT_CMD_PMP;
2006 writel(cmd, port_mmio + PORT_CMD);
2008 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2010 /* see comment above in ahci_pmp_attach() */
2011 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2012 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2015 int ahci_port_resume(struct ata_port *ap)
2018 ahci_start_port(ap);
2020 if (sata_pmp_attached(ap))
2021 ahci_pmp_attach(ap);
2023 ahci_pmp_detach(ap);
2027 EXPORT_SYMBOL_GPL(ahci_port_resume);
2030 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2032 const char *emsg = NULL;
2035 rc = ahci_deinit_port(ap, &emsg);
2037 ahci_power_down(ap);
2039 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2040 ahci_start_port(ap);
2047 static int ahci_port_start(struct ata_port *ap)
2049 struct ahci_host_priv *hpriv = ap->host->private_data;
2050 struct device *dev = ap->host->dev;
2051 struct ahci_port_priv *pp;
2054 size_t dma_sz, rx_fis_sz;
2056 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2060 /* check FBS capability */
2061 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2062 void __iomem *port_mmio = ahci_port_base(ap);
2063 u32 cmd = readl(port_mmio + PORT_CMD);
2064 if (cmd & PORT_CMD_FBSCP)
2065 pp->fbs_supported = true;
2066 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2067 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2069 pp->fbs_supported = true;
2071 dev_warn(dev, "port %d is not capable of FBS\n",
2075 if (pp->fbs_supported) {
2076 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2077 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2079 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2080 rx_fis_sz = AHCI_RX_FIS_SZ;
2083 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2086 memset(mem, 0, dma_sz);
2089 * First item in chunk of DMA memory: 32-slot command table,
2090 * 32 bytes each in size
2093 pp->cmd_slot_dma = mem_dma;
2095 mem += AHCI_CMD_SLOT_SZ;
2096 mem_dma += AHCI_CMD_SLOT_SZ;
2099 * Second item: Received-FIS area
2102 pp->rx_fis_dma = mem_dma;
2105 mem_dma += rx_fis_sz;
2108 * Third item: data area for storing a single command
2109 * and its scatter-gather table
2112 pp->cmd_tbl_dma = mem_dma;
2115 * Save off initial list of interrupts to be enabled.
2116 * This could be changed later
2118 pp->intr_mask = DEF_PORT_IRQ;
2120 ap->private_data = pp;
2122 /* engage engines, captain */
2123 return ahci_port_resume(ap);
2126 static void ahci_port_stop(struct ata_port *ap)
2128 const char *emsg = NULL;
2131 /* de-initialize port */
2132 rc = ahci_deinit_port(ap, &emsg);
2134 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2137 void ahci_print_info(struct ata_host *host, const char *scc_s)
2139 struct ahci_host_priv *hpriv = host->private_data;
2140 void __iomem *mmio = hpriv->mmio;
2141 u32 vers, cap, cap2, impl, speed;
2142 const char *speed_s;
2144 vers = readl(mmio + HOST_VERSION);
2147 impl = hpriv->port_map;
2149 speed = (cap >> 20) & 0xf;
2152 else if (speed == 2)
2154 else if (speed == 3)
2160 "AHCI %02x%02x.%02x%02x "
2161 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2164 (vers >> 24) & 0xff,
2165 (vers >> 16) & 0xff,
2169 ((cap >> 8) & 0x1f) + 1,
2182 cap & HOST_CAP_64 ? "64bit " : "",
2183 cap & HOST_CAP_NCQ ? "ncq " : "",
2184 cap & HOST_CAP_SNTF ? "sntf " : "",
2185 cap & HOST_CAP_MPS ? "ilck " : "",
2186 cap & HOST_CAP_SSS ? "stag " : "",
2187 cap & HOST_CAP_ALPM ? "pm " : "",
2188 cap & HOST_CAP_LED ? "led " : "",
2189 cap & HOST_CAP_CLO ? "clo " : "",
2190 cap & HOST_CAP_ONLY ? "only " : "",
2191 cap & HOST_CAP_PMP ? "pmp " : "",
2192 cap & HOST_CAP_FBS ? "fbs " : "",
2193 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2194 cap & HOST_CAP_SSC ? "slum " : "",
2195 cap & HOST_CAP_PART ? "part " : "",
2196 cap & HOST_CAP_CCC ? "ccc " : "",
2197 cap & HOST_CAP_EMS ? "ems " : "",
2198 cap & HOST_CAP_SXS ? "sxs " : "",
2199 cap2 & HOST_CAP2_APST ? "apst " : "",
2200 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2201 cap2 & HOST_CAP2_BOH ? "boh " : ""
2204 EXPORT_SYMBOL_GPL(ahci_print_info);
2206 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2207 struct ata_port_info *pi)
2210 void __iomem *mmio = hpriv->mmio;
2211 u32 em_loc = readl(mmio + HOST_EM_LOC);
2212 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2214 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2217 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2221 hpriv->em_loc = ((em_loc >> 16) * 4);
2222 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2223 hpriv->em_msg_type = messages;
2224 pi->flags |= ATA_FLAG_EM;
2225 if (!(em_ctl & EM_CTL_ALHD))
2226 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2229 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2231 MODULE_AUTHOR("Jeff Garzik");
2232 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2233 MODULE_LICENSE("GPL");