2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
121 /* constants for mapping table */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
130 PIIX_AHCI_DEVICE = 6,
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
136 enum piix_controller_ids {
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
149 ich8m_apple_sata, /* locks up on second port enable */
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
157 const u16 port_enable;
161 struct piix_host_priv {
167 static int piix_init_one(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
169 static void piix_remove_one(struct pci_dev *pdev);
170 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
171 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
172 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
173 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
174 static int ich_pata_cable_detect(struct ata_port *ap);
175 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
176 static int piix_sidpr_scr_read(struct ata_link *link,
177 unsigned int reg, u32 *val);
178 static int piix_sidpr_scr_write(struct ata_link *link,
179 unsigned int reg, u32 val);
180 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
182 static bool piix_irq_check(struct ata_port *ap);
183 static int piix_port_start(struct ata_port *ap);
185 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
186 static int piix_pci_device_resume(struct pci_dev *pdev);
189 static unsigned int in_module_init = 1;
191 static const struct pci_device_id piix_pci_tbl[] = {
192 /* Intel PIIX3 for the 430HX etc */
193 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
195 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
196 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
197 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
198 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
200 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
202 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
204 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
205 /* Intel ICH (i810, i815, i840) UDMA 66*/
206 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
207 /* Intel ICH0 : UDMA 33*/
208 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
210 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
212 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* Intel ICH3 (E7500/1) UDMA 100 */
216 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
220 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
225 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
226 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
227 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ICH6 (and 6) (i915) UDMA 100 */
229 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH7/7-R (i945, i975) UDMA 100*/
231 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
232 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
233 /* ICH8 Mobile PATA Controller */
234 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
239 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
241 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
242 /* 6300ESB (ICH5 variant with broken PCS present bits) */
243 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
244 /* 6300ESB pretending RAID */
245 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
246 /* 82801FB/FW (ICH6/ICH6W) */
247 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* 82801FR/FRW (ICH6R/ICH6RW) */
249 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
251 * Attach iff the controller is in IDE mode. */
252 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
253 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
254 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
255 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
256 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
257 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
258 /* Enterprise Southbridge 2 (631xESB/632xESB) */
259 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
260 /* SATA Controller 1 IDE (ICH8) */
261 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller 2 IDE (ICH8) */
263 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* Mobile SATA Controller IDE (ICH8M), Apple */
265 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
266 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
267 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
268 /* Mobile SATA Controller IDE (ICH8M) */
269 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (ICH9) */
271 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH9) */
273 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH9) */
275 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH9M) */
277 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH9M) */
279 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH9M) */
281 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (Tolapai) */
283 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
284 /* SATA Controller IDE (ICH10) */
285 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (ICH10) */
289 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
299 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (PCH) */
301 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
304 /* SATA Controller IDE (CPT) */
305 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (CPT) */
307 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (PBG) */
313 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Panther Point) */
317 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
318 /* SATA Controller IDE (Panther Point) */
319 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
324 /* SATA Controller IDE (Lynx Point) */
325 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
326 /* SATA Controller IDE (Lynx Point) */
327 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
328 /* SATA Controller IDE (Lynx Point) */
329 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
330 /* SATA Controller IDE (Lynx Point) */
331 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
332 /* SATA Controller IDE (Lynx Point-LP) */
333 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
334 /* SATA Controller IDE (Lynx Point-LP) */
335 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
336 /* SATA Controller IDE (Lynx Point-LP) */
337 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
338 /* SATA Controller IDE (Lynx Point-LP) */
339 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
340 /* SATA Controller IDE (DH89xxCC) */
341 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
342 /* SATA Controller IDE (Avoton) */
343 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
344 /* SATA Controller IDE (Avoton) */
345 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
346 /* SATA Controller IDE (Avoton) */
347 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
348 /* SATA Controller IDE (Avoton) */
349 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
350 { } /* terminate list */
353 static struct pci_driver piix_pci_driver = {
355 .id_table = piix_pci_tbl,
356 .probe = piix_init_one,
357 .remove = piix_remove_one,
359 .suspend = piix_pci_device_suspend,
360 .resume = piix_pci_device_resume,
364 static struct scsi_host_template piix_sht = {
365 ATA_BMDMA_SHT(DRV_NAME),
368 static struct ata_port_operations piix_sata_ops = {
369 .inherits = &ata_bmdma32_port_ops,
370 .sff_irq_check = piix_irq_check,
371 .port_start = piix_port_start,
374 static struct ata_port_operations piix_pata_ops = {
375 .inherits = &piix_sata_ops,
376 .cable_detect = ata_cable_40wire,
377 .set_piomode = piix_set_piomode,
378 .set_dmamode = piix_set_dmamode,
379 .prereset = piix_pata_prereset,
382 static struct ata_port_operations piix_vmw_ops = {
383 .inherits = &piix_pata_ops,
384 .bmdma_status = piix_vmw_bmdma_status,
387 static struct ata_port_operations ich_pata_ops = {
388 .inherits = &piix_pata_ops,
389 .cable_detect = ich_pata_cable_detect,
390 .set_dmamode = ich_set_dmamode,
393 static struct device_attribute *piix_sidpr_shost_attrs[] = {
394 &dev_attr_link_power_management_policy,
398 static struct scsi_host_template piix_sidpr_sht = {
399 ATA_BMDMA_SHT(DRV_NAME),
400 .shost_attrs = piix_sidpr_shost_attrs,
403 static struct ata_port_operations piix_sidpr_sata_ops = {
404 .inherits = &piix_sata_ops,
405 .hardreset = sata_std_hardreset,
406 .scr_read = piix_sidpr_scr_read,
407 .scr_write = piix_sidpr_scr_write,
408 .set_lpm = piix_sidpr_set_lpm,
411 static const struct piix_map_db ich5_map_db = {
415 /* PM PS SM SS MAP */
416 { P0, NA, P1, NA }, /* 000b */
417 { P1, NA, P0, NA }, /* 001b */
420 { P0, P1, IDE, IDE }, /* 100b */
421 { P1, P0, IDE, IDE }, /* 101b */
422 { IDE, IDE, P0, P1 }, /* 110b */
423 { IDE, IDE, P1, P0 }, /* 111b */
427 static const struct piix_map_db ich6_map_db = {
431 /* PM PS SM SS MAP */
432 { P0, P2, P1, P3 }, /* 00b */
433 { IDE, IDE, P1, P3 }, /* 01b */
434 { P0, P2, IDE, IDE }, /* 10b */
439 static const struct piix_map_db ich6m_map_db = {
443 /* Map 01b isn't specified in the doc but some notebooks use
444 * it anyway. MAP 01b have been spotted on both ICH6M and
448 /* PM PS SM SS MAP */
449 { P0, P2, NA, NA }, /* 00b */
450 { IDE, IDE, P1, P3 }, /* 01b */
451 { P0, P2, IDE, IDE }, /* 10b */
456 static const struct piix_map_db ich8_map_db = {
460 /* PM PS SM SS MAP */
461 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
463 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
468 static const struct piix_map_db ich8_2port_map_db = {
472 /* PM PS SM SS MAP */
473 { P0, NA, P1, NA }, /* 00b */
474 { RV, RV, RV, RV }, /* 01b */
475 { RV, RV, RV, RV }, /* 10b */
480 static const struct piix_map_db ich8m_apple_map_db = {
484 /* PM PS SM SS MAP */
485 { P0, NA, NA, NA }, /* 00b */
487 { P0, P2, IDE, IDE }, /* 10b */
492 static const struct piix_map_db tolapai_map_db = {
496 /* PM PS SM SS MAP */
497 { P0, NA, P1, NA }, /* 00b */
498 { RV, RV, RV, RV }, /* 01b */
499 { RV, RV, RV, RV }, /* 10b */
504 static const struct piix_map_db *piix_map_db_table[] = {
505 [ich5_sata] = &ich5_map_db,
506 [ich6_sata] = &ich6_map_db,
507 [ich6m_sata] = &ich6m_map_db,
508 [ich8_sata] = &ich8_map_db,
509 [ich8_2port_sata] = &ich8_2port_map_db,
510 [ich8m_apple_sata] = &ich8m_apple_map_db,
511 [tolapai_sata] = &tolapai_map_db,
512 [ich8_sata_snb] = &ich8_map_db,
515 static struct ata_port_info piix_port_info[] = {
516 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
518 .flags = PIIX_PATA_FLAGS,
519 .pio_mask = ATA_PIO4,
520 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
521 .port_ops = &piix_pata_ops,
524 [piix_pata_33] = /* PIIX4 at 33MHz */
526 .flags = PIIX_PATA_FLAGS,
527 .pio_mask = ATA_PIO4,
528 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
529 .udma_mask = ATA_UDMA2,
530 .port_ops = &piix_pata_ops,
533 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
535 .flags = PIIX_PATA_FLAGS,
536 .pio_mask = ATA_PIO4,
537 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
538 .udma_mask = ATA_UDMA2,
539 .port_ops = &ich_pata_ops,
542 [ich_pata_66] = /* ICH controllers up to 66MHz */
544 .flags = PIIX_PATA_FLAGS,
545 .pio_mask = ATA_PIO4,
546 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
547 .udma_mask = ATA_UDMA4,
548 .port_ops = &ich_pata_ops,
553 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
554 .pio_mask = ATA_PIO4,
555 .mwdma_mask = ATA_MWDMA12_ONLY,
556 .udma_mask = ATA_UDMA5,
557 .port_ops = &ich_pata_ops,
560 [ich_pata_100_nomwdma1] =
562 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
563 .pio_mask = ATA_PIO4,
564 .mwdma_mask = ATA_MWDMA2_ONLY,
565 .udma_mask = ATA_UDMA5,
566 .port_ops = &ich_pata_ops,
571 .flags = PIIX_SATA_FLAGS,
572 .pio_mask = ATA_PIO4,
573 .mwdma_mask = ATA_MWDMA2,
574 .udma_mask = ATA_UDMA6,
575 .port_ops = &piix_sata_ops,
580 .flags = PIIX_SATA_FLAGS,
581 .pio_mask = ATA_PIO4,
582 .mwdma_mask = ATA_MWDMA2,
583 .udma_mask = ATA_UDMA6,
584 .port_ops = &piix_sata_ops,
589 .flags = PIIX_SATA_FLAGS,
590 .pio_mask = ATA_PIO4,
591 .mwdma_mask = ATA_MWDMA2,
592 .udma_mask = ATA_UDMA6,
593 .port_ops = &piix_sata_ops,
598 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
599 .pio_mask = ATA_PIO4,
600 .mwdma_mask = ATA_MWDMA2,
601 .udma_mask = ATA_UDMA6,
602 .port_ops = &piix_sata_ops,
607 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
608 .pio_mask = ATA_PIO4,
609 .mwdma_mask = ATA_MWDMA2,
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &piix_sata_ops,
616 .flags = PIIX_SATA_FLAGS,
617 .pio_mask = ATA_PIO4,
618 .mwdma_mask = ATA_MWDMA2,
619 .udma_mask = ATA_UDMA6,
620 .port_ops = &piix_sata_ops,
625 .flags = PIIX_SATA_FLAGS,
626 .pio_mask = ATA_PIO4,
627 .mwdma_mask = ATA_MWDMA2,
628 .udma_mask = ATA_UDMA6,
629 .port_ops = &piix_sata_ops,
634 .flags = PIIX_PATA_FLAGS,
635 .pio_mask = ATA_PIO4,
636 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
637 .udma_mask = ATA_UDMA2,
638 .port_ops = &piix_vmw_ops,
642 * some Sandybridge chipsets have broken 32 mode up to now,
643 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
647 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
648 .pio_mask = ATA_PIO4,
649 .mwdma_mask = ATA_MWDMA2,
650 .udma_mask = ATA_UDMA6,
651 .port_ops = &piix_sata_ops,
656 static struct pci_bits piix_enable_bits[] = {
657 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
658 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
661 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
662 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
663 MODULE_LICENSE("GPL");
664 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
665 MODULE_VERSION(DRV_VERSION);
674 * List of laptops that use short cables rather than 80 wire
677 static const struct ich_laptop ich_laptop[] = {
678 /* devid, subvendor, subdev */
679 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
680 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
681 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
682 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
683 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
684 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
685 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
686 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
687 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
688 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
689 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
690 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
691 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
692 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
697 static int piix_port_start(struct ata_port *ap)
699 if (!(ap->flags & PIIX_FLAG_PIO16))
700 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
702 return ata_bmdma_port_start(ap);
706 * ich_pata_cable_detect - Probe host controller cable detect info
707 * @ap: Port for which cable detect info is desired
709 * Read 80c cable indicator from ATA PCI device's PCI config
710 * register. This register is normally set by firmware (BIOS).
713 * None (inherited from caller).
716 static int ich_pata_cable_detect(struct ata_port *ap)
718 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
719 struct piix_host_priv *hpriv = ap->host->private_data;
720 const struct ich_laptop *lap = &ich_laptop[0];
723 /* Check for specials - Acer Aspire 5602WLMi */
724 while (lap->device) {
725 if (lap->device == pdev->device &&
726 lap->subvendor == pdev->subsystem_vendor &&
727 lap->subdevice == pdev->subsystem_device)
728 return ATA_CBL_PATA40_SHORT;
733 /* check BIOS cable detect results */
734 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
735 if ((hpriv->saved_iocfg & mask) == 0)
736 return ATA_CBL_PATA40;
737 return ATA_CBL_PATA80;
741 * piix_pata_prereset - prereset for PATA host controller
743 * @deadline: deadline jiffies for the operation
746 * None (inherited from caller).
748 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
750 struct ata_port *ap = link->ap;
751 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
753 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
755 return ata_sff_prereset(link, deadline);
758 static DEFINE_SPINLOCK(piix_lock);
760 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
763 struct pci_dev *dev = to_pci_dev(ap->host->dev);
765 unsigned int is_slave = (adev->devno != 0);
766 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
767 unsigned int slave_port = 0x44;
774 * See Intel Document 298600-004 for the timing programing rules
775 * for ICH controllers.
778 static const /* ISP RTC */
779 u8 timings[][2] = { { 0, 0 },
786 control |= 1; /* TIME1 enable */
787 if (ata_pio_need_iordy(adev))
788 control |= 2; /* IE enable */
789 /* Intel specifies that the PPE functionality is for disk only */
790 if (adev->class == ATA_DEV_ATA)
791 control |= 4; /* PPE enable */
793 * If the drive MWDMA is faster than it can do PIO then
794 * we must force PIO into PIO0
796 if (adev->pio_mode < XFER_PIO_0 + pio)
797 /* Enable DMA timing only */
798 control |= 8; /* PIO cycles in PIO0 */
800 spin_lock_irqsave(&piix_lock, flags);
802 /* PIO configuration clears DTE unconditionally. It will be
803 * programmed in set_dmamode which is guaranteed to be called
804 * after set_piomode if any DMA mode is available.
806 pci_read_config_word(dev, master_port, &master_data);
808 /* clear TIME1|IE1|PPE1|DTE1 */
809 master_data &= 0xff0f;
810 /* enable PPE1, IE1 and TIME1 as needed */
811 master_data |= (control << 4);
812 pci_read_config_byte(dev, slave_port, &slave_data);
813 slave_data &= (ap->port_no ? 0x0f : 0xf0);
814 /* Load the timing nibble for this slave */
815 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
816 << (ap->port_no ? 4 : 0);
818 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
819 master_data &= 0xccf0;
820 /* Enable PPE, IE and TIME as appropriate */
821 master_data |= control;
822 /* load ISP and RCT */
824 (timings[pio][0] << 12) |
825 (timings[pio][1] << 8);
828 /* Enable SITRE (separate slave timing register) */
829 master_data |= 0x4000;
830 pci_write_config_word(dev, master_port, master_data);
832 pci_write_config_byte(dev, slave_port, slave_data);
834 /* Ensure the UDMA bit is off - it will be turned back on if
838 pci_read_config_byte(dev, 0x48, &udma_enable);
839 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
840 pci_write_config_byte(dev, 0x48, udma_enable);
843 spin_unlock_irqrestore(&piix_lock, flags);
847 * piix_set_piomode - Initialize host controller PATA PIO timings
848 * @ap: Port whose timings we are configuring
849 * @adev: Drive in question
851 * Set PIO mode for device, in host controller PCI config space.
854 * None (inherited from caller).
857 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
859 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
863 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
864 * @ap: Port whose timings we are configuring
865 * @adev: Drive in question
866 * @isich: set if the chip is an ICH device
868 * Set UDMA mode for device, in host controller PCI config space.
871 * None (inherited from caller).
874 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
876 struct pci_dev *dev = to_pci_dev(ap->host->dev);
878 u8 speed = adev->dma_mode;
879 int devid = adev->devno + 2 * ap->port_no;
882 if (speed >= XFER_UDMA_0) {
883 unsigned int udma = speed - XFER_UDMA_0;
886 int u_clock, u_speed;
888 spin_lock_irqsave(&piix_lock, flags);
890 pci_read_config_byte(dev, 0x48, &udma_enable);
893 * UDMA is handled by a combination of clock switching and
894 * selection of dividers
896 * Handy rule: Odd modes are UDMATIMx 01, even are 02
897 * except UDMA0 which is 00
899 u_speed = min(2 - (udma & 1), udma);
901 u_clock = 0x1000; /* 100Mhz */
903 u_clock = 1; /* 66Mhz */
905 u_clock = 0; /* 33Mhz */
907 udma_enable |= (1 << devid);
909 /* Load the CT/RP selection */
910 pci_read_config_word(dev, 0x4A, &udma_timing);
911 udma_timing &= ~(3 << (4 * devid));
912 udma_timing |= u_speed << (4 * devid);
913 pci_write_config_word(dev, 0x4A, udma_timing);
916 /* Select a 33/66/100Mhz clock */
917 pci_read_config_word(dev, 0x54, &ideconf);
918 ideconf &= ~(0x1001 << devid);
919 ideconf |= u_clock << devid;
920 /* For ICH or later we should set bit 10 for better
921 performance (WR_PingPong_En) */
922 pci_write_config_word(dev, 0x54, ideconf);
925 pci_write_config_byte(dev, 0x48, udma_enable);
927 spin_unlock_irqrestore(&piix_lock, flags);
929 /* MWDMA is driven by the PIO timings. */
930 unsigned int mwdma = speed - XFER_MW_DMA_0;
931 const unsigned int needed_pio[3] = {
932 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
934 int pio = needed_pio[mwdma] - XFER_PIO_0;
936 /* XFER_PIO_0 is never used currently */
937 piix_set_timings(ap, adev, pio);
942 * piix_set_dmamode - Initialize host controller PATA DMA timings
943 * @ap: Port whose timings we are configuring
946 * Set MW/UDMA mode for device, in host controller PCI config space.
949 * None (inherited from caller).
952 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
954 do_pata_set_dmamode(ap, adev, 0);
958 * ich_set_dmamode - Initialize host controller PATA DMA timings
959 * @ap: Port whose timings we are configuring
962 * Set MW/UDMA mode for device, in host controller PCI config space.
965 * None (inherited from caller).
968 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
970 do_pata_set_dmamode(ap, adev, 1);
974 * Serial ATA Index/Data Pair Superset Registers access
976 * Beginning from ICH8, there's a sane way to access SCRs using index
977 * and data register pair located at BAR5 which means that we have
978 * separate SCRs for master and slave. This is handled using libata
979 * slave_link facility.
981 static const int piix_sidx_map[] = {
987 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
989 struct ata_port *ap = link->ap;
990 struct piix_host_priv *hpriv = ap->host->private_data;
992 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
993 hpriv->sidpr + PIIX_SIDPR_IDX);
996 static int piix_sidpr_scr_read(struct ata_link *link,
997 unsigned int reg, u32 *val)
999 struct piix_host_priv *hpriv = link->ap->host->private_data;
1001 if (reg >= ARRAY_SIZE(piix_sidx_map))
1004 piix_sidpr_sel(link, reg);
1005 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1009 static int piix_sidpr_scr_write(struct ata_link *link,
1010 unsigned int reg, u32 val)
1012 struct piix_host_priv *hpriv = link->ap->host->private_data;
1014 if (reg >= ARRAY_SIZE(piix_sidx_map))
1017 piix_sidpr_sel(link, reg);
1018 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1022 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1025 return sata_link_scr_lpm(link, policy, false);
1028 static bool piix_irq_check(struct ata_port *ap)
1030 if (unlikely(!ap->ioaddr.bmdma_addr))
1033 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1037 static int piix_broken_suspend(void)
1039 static const struct dmi_system_id sysids[] = {
1041 .ident = "TECRA M3",
1043 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1044 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1048 .ident = "TECRA M3",
1050 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1051 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1055 .ident = "TECRA M4",
1057 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1062 .ident = "TECRA M4",
1064 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1065 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1069 .ident = "TECRA M5",
1071 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1072 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1076 .ident = "TECRA M6",
1078 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1079 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1083 .ident = "TECRA M7",
1085 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1086 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1090 .ident = "TECRA A8",
1092 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1093 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1097 .ident = "Satellite R20",
1099 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1104 .ident = "Satellite R25",
1106 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1107 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1111 .ident = "Satellite U200",
1113 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1114 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1118 .ident = "Satellite U200",
1120 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1121 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1125 .ident = "Satellite Pro U200",
1127 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1128 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1132 .ident = "Satellite U205",
1134 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1135 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1139 .ident = "SATELLITE U205",
1141 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1142 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1146 .ident = "Portege M500",
1148 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1149 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1153 .ident = "VGN-BX297XP",
1155 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1160 { } /* terminate list */
1162 static const char *oemstrs[] = {
1167 if (dmi_check_system(sysids))
1170 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1171 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1174 /* TECRA M4 sometimes forgets its identify and reports bogus
1175 * DMI information. As the bogus information is a bit
1176 * generic, match as many entries as possible. This manual
1177 * matching is necessary because dmi_system_id.matches is
1178 * limited to four entries.
1180 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1181 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1182 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1183 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1184 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1185 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1186 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1192 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1194 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1195 unsigned long flags;
1198 rc = ata_host_suspend(host, mesg);
1202 /* Some braindamaged ACPI suspend implementations expect the
1203 * controller to be awake on entry; otherwise, it burns cpu
1204 * cycles and power trying to do something to the sleeping
1207 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1208 pci_save_state(pdev);
1210 /* mark its power state as "unknown", since we don't
1211 * know if e.g. the BIOS will change its device state
1214 if (pdev->current_state == PCI_D0)
1215 pdev->current_state = PCI_UNKNOWN;
1217 /* tell resume that it's waking up from broken suspend */
1218 spin_lock_irqsave(&host->lock, flags);
1219 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1220 spin_unlock_irqrestore(&host->lock, flags);
1222 ata_pci_device_do_suspend(pdev, mesg);
1227 static int piix_pci_device_resume(struct pci_dev *pdev)
1229 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1230 unsigned long flags;
1233 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1234 spin_lock_irqsave(&host->lock, flags);
1235 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1236 spin_unlock_irqrestore(&host->lock, flags);
1238 pci_set_power_state(pdev, PCI_D0);
1239 pci_restore_state(pdev);
1241 /* PCI device wasn't disabled during suspend. Use
1242 * pci_reenable_device() to avoid affecting the enable
1245 rc = pci_reenable_device(pdev);
1248 "failed to enable device after resume (%d)\n",
1251 rc = ata_pci_device_do_resume(pdev);
1254 ata_host_resume(host);
1260 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1262 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1265 #define AHCI_PCI_BAR 5
1266 #define AHCI_GLOBAL_CTL 0x04
1267 #define AHCI_ENABLE (1 << 31)
1268 static int piix_disable_ahci(struct pci_dev *pdev)
1274 /* BUG: pci_enable_device has not yet been called. This
1275 * works because this device is usually set up by BIOS.
1278 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1279 !pci_resource_len(pdev, AHCI_PCI_BAR))
1282 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1286 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1287 if (tmp & AHCI_ENABLE) {
1288 tmp &= ~AHCI_ENABLE;
1289 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1291 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1292 if (tmp & AHCI_ENABLE)
1296 pci_iounmap(pdev, mmio);
1301 * piix_check_450nx_errata - Check for problem 450NX setup
1302 * @ata_dev: the PCI device to check
1304 * Check for the present of 450NX errata #19 and errata #25. If
1305 * they are found return an error code so we can turn off DMA
1308 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1310 struct pci_dev *pdev = NULL;
1312 int no_piix_dma = 0;
1314 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1315 /* Look for 450NX PXB. Check for problem configurations
1316 A PCI quirk checks bit 6 already */
1317 pci_read_config_word(pdev, 0x41, &cfg);
1318 /* Only on the original revision: IDE DMA can hang */
1319 if (pdev->revision == 0x00)
1321 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1322 else if (cfg & (1<<14) && pdev->revision < 5)
1326 dev_warn(&ata_dev->dev,
1327 "450NX errata present, disabling IDE DMA%s\n",
1328 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1334 static void __devinit piix_init_pcs(struct ata_host *host,
1335 const struct piix_map_db *map_db)
1337 struct pci_dev *pdev = to_pci_dev(host->dev);
1340 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1342 new_pcs = pcs | map_db->port_enable;
1344 if (new_pcs != pcs) {
1345 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1346 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1351 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1352 struct ata_port_info *pinfo,
1353 const struct piix_map_db *map_db)
1356 int i, invalid_map = 0;
1359 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1361 map = map_db->map[map_value & map_db->mask];
1363 dev_info(&pdev->dev, "MAP [");
1364 for (i = 0; i < 4; i++) {
1376 WARN_ON((i & 1) || map[i + 1] != IDE);
1377 pinfo[i / 2] = piix_port_info[ich_pata_100];
1379 pr_cont(" IDE IDE");
1383 pr_cont(" P%d", map[i]);
1385 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1392 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1397 static bool piix_no_sidpr(struct ata_host *host)
1399 struct pci_dev *pdev = to_pci_dev(host->dev);
1402 * Samsung DB-P70 only has three ATA ports exposed and
1403 * curiously the unconnected first port reports link online
1404 * while not responding to SRST protocol causing excessive
1407 * Unfortunately, the system doesn't carry enough DMI
1408 * information to identify the machine but does have subsystem
1409 * vendor and device set. As it's unclear whether the
1410 * subsystem vendor/device is used only for this specific
1411 * board, the port can't be disabled solely with the
1412 * information; however, turning off SIDPR access works around
1413 * the problem. Turn it off.
1415 * This problem is reported in bnc#441240.
1417 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1419 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1420 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1421 pdev->subsystem_device == 0xb049) {
1423 "Samsung DB-P70 detected, disabling SIDPR\n");
1430 static int __devinit piix_init_sidpr(struct ata_host *host)
1432 struct pci_dev *pdev = to_pci_dev(host->dev);
1433 struct piix_host_priv *hpriv = host->private_data;
1434 struct ata_link *link0 = &host->ports[0]->link;
1438 /* check for availability */
1439 for (i = 0; i < 4; i++)
1440 if (hpriv->map[i] == IDE)
1443 /* is it blacklisted? */
1444 if (piix_no_sidpr(host))
1447 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1450 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1451 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1454 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1457 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1459 /* SCR access via SIDPR doesn't work on some configurations.
1460 * Give it a test drive by inhibiting power save modes which
1463 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1465 /* if IPM is already 3, SCR access is probably working. Don't
1466 * un-inhibit power save modes as BIOS might have inhibited
1467 * them for a reason.
1469 if ((scontrol & 0xf00) != 0x300) {
1471 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1472 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1474 if ((scontrol & 0xf00) != 0x300) {
1476 "SCR access via SIDPR is available but doesn't work\n");
1481 /* okay, SCRs available, set ops and ask libata for slave_link */
1482 for (i = 0; i < 2; i++) {
1483 struct ata_port *ap = host->ports[i];
1485 ap->ops = &piix_sidpr_sata_ops;
1487 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1488 rc = ata_slave_link_init(ap);
1497 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1499 static const struct dmi_system_id sysids[] = {
1501 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1502 * isn't used to boot the system which
1503 * disables the channel.
1507 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1508 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1512 { } /* terminate list */
1514 struct pci_dev *pdev = to_pci_dev(host->dev);
1515 struct piix_host_priv *hpriv = host->private_data;
1517 if (!dmi_check_system(sysids))
1520 /* The datasheet says that bit 18 is NOOP but certain systems
1521 * seem to use it to disable a channel. Clear the bit on the
1524 if (hpriv->saved_iocfg & (1 << 18)) {
1525 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1526 pci_write_config_dword(pdev, PIIX_IOCFG,
1527 hpriv->saved_iocfg & ~(1 << 18));
1531 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1533 static const struct dmi_system_id broken_systems[] = {
1535 .ident = "HP Compaq 2510p",
1537 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1538 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1540 /* PCI slot number of the controller */
1541 .driver_data = (void *)0x1FUL,
1544 .ident = "HP Compaq nc6000",
1546 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1547 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1549 /* PCI slot number of the controller */
1550 .driver_data = (void *)0x1FUL,
1553 { } /* terminate list */
1555 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1558 unsigned long slot = (unsigned long)dmi->driver_data;
1559 /* apply the quirk only to on-board controllers */
1560 return slot == PCI_SLOT(pdev->devfn);
1567 * piix_init_one - Register PIIX ATA PCI device with kernel services
1568 * @pdev: PCI device to register
1569 * @ent: Entry in piix_pci_tbl matching with @pdev
1571 * Called from kernel PCI layer. We probe for combined mode (sigh),
1572 * and then hand over control to libata, for it to do the rest.
1575 * Inherited from PCI layer (may sleep).
1578 * Zero on success, or -ERRNO value.
1581 static int __devinit piix_init_one(struct pci_dev *pdev,
1582 const struct pci_device_id *ent)
1584 struct device *dev = &pdev->dev;
1585 struct ata_port_info port_info[2];
1586 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1587 struct scsi_host_template *sht = &piix_sht;
1588 unsigned long port_flags;
1589 struct ata_host *host;
1590 struct piix_host_priv *hpriv;
1593 ata_print_version_once(&pdev->dev, DRV_VERSION);
1595 /* no hotplugging support for later devices (FIXME) */
1596 if (!in_module_init && ent->driver_data >= ich5_sata)
1599 if (piix_broken_system_poweroff(pdev)) {
1600 piix_port_info[ent->driver_data].flags |=
1601 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1602 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1603 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1604 "on poweroff and hibernation\n");
1607 port_info[0] = piix_port_info[ent->driver_data];
1608 port_info[1] = piix_port_info[ent->driver_data];
1610 port_flags = port_info[0].flags;
1612 /* enable device and prepare host */
1613 rc = pcim_enable_device(pdev);
1617 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1621 /* Save IOCFG, this will be used for cable detection, quirk
1622 * detection and restoration on detach. This is necessary
1623 * because some ACPI implementations mess up cable related
1624 * bits on _STM. Reported on kernel bz#11879.
1626 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1628 /* ICH6R may be driven by either ata_piix or ahci driver
1629 * regardless of BIOS configuration. Make sure AHCI mode is
1632 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1633 rc = piix_disable_ahci(pdev);
1638 /* SATA map init can change port_info, do it before prepping host */
1639 if (port_flags & ATA_FLAG_SATA)
1640 hpriv->map = piix_init_sata_map(pdev, port_info,
1641 piix_map_db_table[ent->driver_data]);
1643 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1646 host->private_data = hpriv;
1648 /* initialize controller */
1649 if (port_flags & ATA_FLAG_SATA) {
1650 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1651 rc = piix_init_sidpr(host);
1654 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1655 sht = &piix_sidpr_sht;
1658 /* apply IOCFG bit18 quirk */
1659 piix_iocfg_bit18_quirk(host);
1661 /* On ICH5, some BIOSen disable the interrupt using the
1662 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1663 * On ICH6, this bit has the same effect, but only when
1664 * MSI is disabled (and it is disabled, as we don't use
1665 * message-signalled interrupts currently).
1667 if (port_flags & PIIX_FLAG_CHECKINTR)
1670 if (piix_check_450nx_errata(pdev)) {
1671 /* This writes into the master table but it does not
1672 really matter for this errata as we will apply it to
1673 all the PIIX devices on the board */
1674 host->ports[0]->mwdma_mask = 0;
1675 host->ports[0]->udma_mask = 0;
1676 host->ports[1]->mwdma_mask = 0;
1677 host->ports[1]->udma_mask = 0;
1679 host->flags |= ATA_HOST_PARALLEL_SCAN;
1681 pci_set_master(pdev);
1682 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1685 static void piix_remove_one(struct pci_dev *pdev)
1687 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1688 struct piix_host_priv *hpriv = host->private_data;
1690 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1692 ata_pci_remove_one(pdev);
1695 static int __init piix_init(void)
1699 DPRINTK("pci_register_driver\n");
1700 rc = pci_register_driver(&piix_pci_driver);
1710 static void __exit piix_exit(void)
1712 pci_unregister_driver(&piix_pci_driver);
1715 module_init(piix_init);
1716 module_exit(piix_exit);