2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
121 /* constants for mapping table */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
130 PIIX_AHCI_DEVICE = 6,
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
136 enum piix_controller_ids {
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
149 ich8m_apple_sata, /* locks up on second port enable */
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
159 const u16 port_enable;
163 struct piix_host_priv {
169 static int piix_init_one(struct pci_dev *pdev,
170 const struct pci_device_id *ent);
171 static void piix_remove_one(struct pci_dev *pdev);
172 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
173 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
174 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
175 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
176 static int ich_pata_cable_detect(struct ata_port *ap);
177 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
178 static int piix_sidpr_scr_read(struct ata_link *link,
179 unsigned int reg, u32 *val);
180 static int piix_sidpr_scr_write(struct ata_link *link,
181 unsigned int reg, u32 val);
182 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
184 static bool piix_irq_check(struct ata_port *ap);
185 static int piix_port_start(struct ata_port *ap);
187 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
188 static int piix_pci_device_resume(struct pci_dev *pdev);
191 static unsigned int in_module_init = 1;
193 static const struct pci_device_id piix_pci_tbl[] = {
194 /* Intel PIIX3 for the 430HX etc */
195 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
197 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
198 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
199 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
200 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
202 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
204 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
206 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
207 /* Intel ICH (i810, i815, i840) UDMA 66*/
208 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
209 /* Intel ICH0 : UDMA 33*/
210 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
212 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
214 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* Intel ICH3 (E7500/1) UDMA 100 */
218 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
222 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
225 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
227 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
229 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH6 (and 6) (i915) UDMA 100 */
231 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
232 /* ICH7/7-R (i945, i975) UDMA 100*/
233 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
234 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
235 /* ICH8 Mobile PATA Controller */
236 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
241 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
243 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
244 /* 6300ESB (ICH5 variant with broken PCS present bits) */
245 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
246 /* 6300ESB pretending RAID */
247 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
248 /* 82801FB/FW (ICH6/ICH6W) */
249 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 82801FR/FRW (ICH6R/ICH6RW) */
251 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
252 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
253 * Attach iff the controller is in IDE mode. */
254 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
255 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
256 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
257 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
258 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
259 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
260 /* Enterprise Southbridge 2 (631xESB/632xESB) */
261 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
262 /* SATA Controller 1 IDE (ICH8) */
263 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller 2 IDE (ICH8) */
265 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* Mobile SATA Controller IDE (ICH8M), Apple */
267 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
268 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
269 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
270 /* Mobile SATA Controller IDE (ICH8M) */
271 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH9) */
273 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (ICH9) */
275 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH9) */
277 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH9M) */
279 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH9M) */
281 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282 /* SATA Controller IDE (ICH9M) */
283 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (Tolapai) */
285 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288 /* SATA Controller IDE (ICH10) */
289 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
292 /* SATA Controller IDE (ICH10) */
293 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
299 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
300 /* SATA Controller IDE (PCH) */
301 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 /* SATA Controller IDE (PCH) */
305 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
306 /* SATA Controller IDE (CPT) */
307 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (CPT) */
313 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
316 /* SATA Controller IDE (PBG) */
317 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
318 /* SATA Controller IDE (Panther Point) */
319 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
324 /* SATA Controller IDE (Panther Point) */
325 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
326 /* SATA Controller IDE (Lynx Point) */
327 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
328 /* SATA Controller IDE (Lynx Point) */
329 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
330 /* SATA Controller IDE (Lynx Point) */
331 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
332 /* SATA Controller IDE (Lynx Point) */
333 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
334 /* SATA Controller IDE (Lynx Point-LP) */
335 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
336 /* SATA Controller IDE (Lynx Point-LP) */
337 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
338 /* SATA Controller IDE (Lynx Point-LP) */
339 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
340 /* SATA Controller IDE (Lynx Point-LP) */
341 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
342 /* SATA Controller IDE (DH89xxCC) */
343 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
344 /* SATA Controller IDE (Avoton) */
345 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
346 /* SATA Controller IDE (Avoton) */
347 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
348 /* SATA Controller IDE (Avoton) */
349 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
350 /* SATA Controller IDE (Avoton) */
351 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
352 /* SATA Controller IDE (Wellsburg) */
353 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
354 /* SATA Controller IDE (Wellsburg) */
355 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
356 /* SATA Controller IDE (Wellsburg) */
357 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
358 /* SATA Controller IDE (Wellsburg) */
359 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
360 /* SATA Controller IDE (BayTrail) */
361 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
362 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
363 /* SATA Controller IDE (Coleto Creek) */
364 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
365 /* SATA Controller IDE (9 Series) */
366 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
367 /* SATA Controller IDE (9 Series) */
368 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
369 /* SATA Controller IDE (9 Series) */
370 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
371 /* SATA Controller IDE (9 Series) */
372 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
374 { } /* terminate list */
377 static struct pci_driver piix_pci_driver = {
379 .id_table = piix_pci_tbl,
380 .probe = piix_init_one,
381 .remove = piix_remove_one,
383 .suspend = piix_pci_device_suspend,
384 .resume = piix_pci_device_resume,
388 static struct scsi_host_template piix_sht = {
389 ATA_BMDMA_SHT(DRV_NAME),
392 static struct ata_port_operations piix_sata_ops = {
393 .inherits = &ata_bmdma32_port_ops,
394 .sff_irq_check = piix_irq_check,
395 .port_start = piix_port_start,
398 static struct ata_port_operations piix_pata_ops = {
399 .inherits = &piix_sata_ops,
400 .cable_detect = ata_cable_40wire,
401 .set_piomode = piix_set_piomode,
402 .set_dmamode = piix_set_dmamode,
403 .prereset = piix_pata_prereset,
406 static struct ata_port_operations piix_vmw_ops = {
407 .inherits = &piix_pata_ops,
408 .bmdma_status = piix_vmw_bmdma_status,
411 static struct ata_port_operations ich_pata_ops = {
412 .inherits = &piix_pata_ops,
413 .cable_detect = ich_pata_cable_detect,
414 .set_dmamode = ich_set_dmamode,
417 static struct device_attribute *piix_sidpr_shost_attrs[] = {
418 &dev_attr_link_power_management_policy,
422 static struct scsi_host_template piix_sidpr_sht = {
423 ATA_BMDMA_SHT(DRV_NAME),
424 .shost_attrs = piix_sidpr_shost_attrs,
427 static struct ata_port_operations piix_sidpr_sata_ops = {
428 .inherits = &piix_sata_ops,
429 .hardreset = sata_std_hardreset,
430 .scr_read = piix_sidpr_scr_read,
431 .scr_write = piix_sidpr_scr_write,
432 .set_lpm = piix_sidpr_set_lpm,
435 static const struct piix_map_db ich5_map_db = {
439 /* PM PS SM SS MAP */
440 { P0, NA, P1, NA }, /* 000b */
441 { P1, NA, P0, NA }, /* 001b */
444 { P0, P1, IDE, IDE }, /* 100b */
445 { P1, P0, IDE, IDE }, /* 101b */
446 { IDE, IDE, P0, P1 }, /* 110b */
447 { IDE, IDE, P1, P0 }, /* 111b */
451 static const struct piix_map_db ich6_map_db = {
455 /* PM PS SM SS MAP */
456 { P0, P2, P1, P3 }, /* 00b */
457 { IDE, IDE, P1, P3 }, /* 01b */
458 { P0, P2, IDE, IDE }, /* 10b */
463 static const struct piix_map_db ich6m_map_db = {
467 /* Map 01b isn't specified in the doc but some notebooks use
468 * it anyway. MAP 01b have been spotted on both ICH6M and
472 /* PM PS SM SS MAP */
473 { P0, P2, NA, NA }, /* 00b */
474 { IDE, IDE, P1, P3 }, /* 01b */
475 { P0, P2, IDE, IDE }, /* 10b */
480 static const struct piix_map_db ich8_map_db = {
484 /* PM PS SM SS MAP */
485 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
487 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
492 static const struct piix_map_db ich8_2port_map_db = {
496 /* PM PS SM SS MAP */
497 { P0, NA, P1, NA }, /* 00b */
498 { RV, RV, RV, RV }, /* 01b */
499 { RV, RV, RV, RV }, /* 10b */
504 static const struct piix_map_db ich8m_apple_map_db = {
508 /* PM PS SM SS MAP */
509 { P0, NA, NA, NA }, /* 00b */
511 { P0, P2, IDE, IDE }, /* 10b */
516 static const struct piix_map_db tolapai_map_db = {
520 /* PM PS SM SS MAP */
521 { P0, NA, P1, NA }, /* 00b */
522 { RV, RV, RV, RV }, /* 01b */
523 { RV, RV, RV, RV }, /* 10b */
528 static const struct piix_map_db *piix_map_db_table[] = {
529 [ich5_sata] = &ich5_map_db,
530 [ich6_sata] = &ich6_map_db,
531 [ich6m_sata] = &ich6m_map_db,
532 [ich8_sata] = &ich8_map_db,
533 [ich8_2port_sata] = &ich8_2port_map_db,
534 [ich8m_apple_sata] = &ich8m_apple_map_db,
535 [tolapai_sata] = &tolapai_map_db,
536 [ich8_sata_snb] = &ich8_map_db,
537 [ich8_2port_sata_snb] = &ich8_2port_map_db,
538 [ich8_2port_sata_byt] = &ich8_2port_map_db,
541 static struct ata_port_info piix_port_info[] = {
542 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
544 .flags = PIIX_PATA_FLAGS,
545 .pio_mask = ATA_PIO4,
546 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
547 .port_ops = &piix_pata_ops,
550 [piix_pata_33] = /* PIIX4 at 33MHz */
552 .flags = PIIX_PATA_FLAGS,
553 .pio_mask = ATA_PIO4,
554 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
555 .udma_mask = ATA_UDMA2,
556 .port_ops = &piix_pata_ops,
559 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
561 .flags = PIIX_PATA_FLAGS,
562 .pio_mask = ATA_PIO4,
563 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
564 .udma_mask = ATA_UDMA2,
565 .port_ops = &ich_pata_ops,
568 [ich_pata_66] = /* ICH controllers up to 66MHz */
570 .flags = PIIX_PATA_FLAGS,
571 .pio_mask = ATA_PIO4,
572 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
573 .udma_mask = ATA_UDMA4,
574 .port_ops = &ich_pata_ops,
579 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
580 .pio_mask = ATA_PIO4,
581 .mwdma_mask = ATA_MWDMA12_ONLY,
582 .udma_mask = ATA_UDMA5,
583 .port_ops = &ich_pata_ops,
586 [ich_pata_100_nomwdma1] =
588 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
589 .pio_mask = ATA_PIO4,
590 .mwdma_mask = ATA_MWDMA2_ONLY,
591 .udma_mask = ATA_UDMA5,
592 .port_ops = &ich_pata_ops,
597 .flags = PIIX_SATA_FLAGS,
598 .pio_mask = ATA_PIO4,
599 .mwdma_mask = ATA_MWDMA2,
600 .udma_mask = ATA_UDMA6,
601 .port_ops = &piix_sata_ops,
606 .flags = PIIX_SATA_FLAGS,
607 .pio_mask = ATA_PIO4,
608 .mwdma_mask = ATA_MWDMA2,
609 .udma_mask = ATA_UDMA6,
610 .port_ops = &piix_sata_ops,
615 .flags = PIIX_SATA_FLAGS,
616 .pio_mask = ATA_PIO4,
617 .mwdma_mask = ATA_MWDMA2,
618 .udma_mask = ATA_UDMA6,
619 .port_ops = &piix_sata_ops,
624 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
625 .pio_mask = ATA_PIO4,
626 .mwdma_mask = ATA_MWDMA2,
627 .udma_mask = ATA_UDMA6,
628 .port_ops = &piix_sata_ops,
633 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
634 .pio_mask = ATA_PIO4,
635 .mwdma_mask = ATA_MWDMA2,
636 .udma_mask = ATA_UDMA6,
637 .port_ops = &piix_sata_ops,
642 .flags = PIIX_SATA_FLAGS,
643 .pio_mask = ATA_PIO4,
644 .mwdma_mask = ATA_MWDMA2,
645 .udma_mask = ATA_UDMA6,
646 .port_ops = &piix_sata_ops,
651 .flags = PIIX_SATA_FLAGS,
652 .pio_mask = ATA_PIO4,
653 .mwdma_mask = ATA_MWDMA2,
654 .udma_mask = ATA_UDMA6,
655 .port_ops = &piix_sata_ops,
660 .flags = PIIX_PATA_FLAGS,
661 .pio_mask = ATA_PIO4,
662 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
663 .udma_mask = ATA_UDMA2,
664 .port_ops = &piix_vmw_ops,
668 * some Sandybridge chipsets have broken 32 mode up to now,
669 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
673 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
674 .pio_mask = ATA_PIO4,
675 .mwdma_mask = ATA_MWDMA2,
676 .udma_mask = ATA_UDMA6,
677 .port_ops = &piix_sata_ops,
680 [ich8_2port_sata_snb] =
682 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
684 .pio_mask = ATA_PIO4,
685 .mwdma_mask = ATA_MWDMA2,
686 .udma_mask = ATA_UDMA6,
687 .port_ops = &piix_sata_ops,
690 [ich8_2port_sata_byt] =
692 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
693 .pio_mask = ATA_PIO4,
694 .mwdma_mask = ATA_MWDMA2,
695 .udma_mask = ATA_UDMA6,
696 .port_ops = &piix_sata_ops,
701 static struct pci_bits piix_enable_bits[] = {
702 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
703 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
706 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
707 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
708 MODULE_LICENSE("GPL");
709 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
710 MODULE_VERSION(DRV_VERSION);
719 * List of laptops that use short cables rather than 80 wire
722 static const struct ich_laptop ich_laptop[] = {
723 /* devid, subvendor, subdev */
724 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
725 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
726 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
727 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
728 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
729 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
730 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
731 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
732 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
733 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
734 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
735 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
736 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
737 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
742 static int piix_port_start(struct ata_port *ap)
744 if (!(ap->flags & PIIX_FLAG_PIO16))
745 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
747 return ata_bmdma_port_start(ap);
751 * ich_pata_cable_detect - Probe host controller cable detect info
752 * @ap: Port for which cable detect info is desired
754 * Read 80c cable indicator from ATA PCI device's PCI config
755 * register. This register is normally set by firmware (BIOS).
758 * None (inherited from caller).
761 static int ich_pata_cable_detect(struct ata_port *ap)
763 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
764 struct piix_host_priv *hpriv = ap->host->private_data;
765 const struct ich_laptop *lap = &ich_laptop[0];
768 /* Check for specials - Acer Aspire 5602WLMi */
769 while (lap->device) {
770 if (lap->device == pdev->device &&
771 lap->subvendor == pdev->subsystem_vendor &&
772 lap->subdevice == pdev->subsystem_device)
773 return ATA_CBL_PATA40_SHORT;
778 /* check BIOS cable detect results */
779 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
780 if ((hpriv->saved_iocfg & mask) == 0)
781 return ATA_CBL_PATA40;
782 return ATA_CBL_PATA80;
786 * piix_pata_prereset - prereset for PATA host controller
788 * @deadline: deadline jiffies for the operation
791 * None (inherited from caller).
793 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
795 struct ata_port *ap = link->ap;
796 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
798 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
800 return ata_sff_prereset(link, deadline);
803 static DEFINE_SPINLOCK(piix_lock);
805 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
808 struct pci_dev *dev = to_pci_dev(ap->host->dev);
810 unsigned int is_slave = (adev->devno != 0);
811 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
812 unsigned int slave_port = 0x44;
819 * See Intel Document 298600-004 for the timing programing rules
820 * for ICH controllers.
823 static const /* ISP RTC */
824 u8 timings[][2] = { { 0, 0 },
831 control |= 1; /* TIME1 enable */
832 if (ata_pio_need_iordy(adev))
833 control |= 2; /* IE enable */
834 /* Intel specifies that the PPE functionality is for disk only */
835 if (adev->class == ATA_DEV_ATA)
836 control |= 4; /* PPE enable */
838 * If the drive MWDMA is faster than it can do PIO then
839 * we must force PIO into PIO0
841 if (adev->pio_mode < XFER_PIO_0 + pio)
842 /* Enable DMA timing only */
843 control |= 8; /* PIO cycles in PIO0 */
845 spin_lock_irqsave(&piix_lock, flags);
847 /* PIO configuration clears DTE unconditionally. It will be
848 * programmed in set_dmamode which is guaranteed to be called
849 * after set_piomode if any DMA mode is available.
851 pci_read_config_word(dev, master_port, &master_data);
853 /* clear TIME1|IE1|PPE1|DTE1 */
854 master_data &= 0xff0f;
855 /* enable PPE1, IE1 and TIME1 as needed */
856 master_data |= (control << 4);
857 pci_read_config_byte(dev, slave_port, &slave_data);
858 slave_data &= (ap->port_no ? 0x0f : 0xf0);
859 /* Load the timing nibble for this slave */
860 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
861 << (ap->port_no ? 4 : 0);
863 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
864 master_data &= 0xccf0;
865 /* Enable PPE, IE and TIME as appropriate */
866 master_data |= control;
867 /* load ISP and RCT */
869 (timings[pio][0] << 12) |
870 (timings[pio][1] << 8);
873 /* Enable SITRE (separate slave timing register) */
874 master_data |= 0x4000;
875 pci_write_config_word(dev, master_port, master_data);
877 pci_write_config_byte(dev, slave_port, slave_data);
879 /* Ensure the UDMA bit is off - it will be turned back on if
883 pci_read_config_byte(dev, 0x48, &udma_enable);
884 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
885 pci_write_config_byte(dev, 0x48, udma_enable);
888 spin_unlock_irqrestore(&piix_lock, flags);
892 * piix_set_piomode - Initialize host controller PATA PIO timings
893 * @ap: Port whose timings we are configuring
894 * @adev: Drive in question
896 * Set PIO mode for device, in host controller PCI config space.
899 * None (inherited from caller).
902 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
904 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
908 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
909 * @ap: Port whose timings we are configuring
910 * @adev: Drive in question
911 * @isich: set if the chip is an ICH device
913 * Set UDMA mode for device, in host controller PCI config space.
916 * None (inherited from caller).
919 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
921 struct pci_dev *dev = to_pci_dev(ap->host->dev);
923 u8 speed = adev->dma_mode;
924 int devid = adev->devno + 2 * ap->port_no;
927 if (speed >= XFER_UDMA_0) {
928 unsigned int udma = speed - XFER_UDMA_0;
931 int u_clock, u_speed;
933 spin_lock_irqsave(&piix_lock, flags);
935 pci_read_config_byte(dev, 0x48, &udma_enable);
938 * UDMA is handled by a combination of clock switching and
939 * selection of dividers
941 * Handy rule: Odd modes are UDMATIMx 01, even are 02
942 * except UDMA0 which is 00
944 u_speed = min(2 - (udma & 1), udma);
946 u_clock = 0x1000; /* 100Mhz */
948 u_clock = 1; /* 66Mhz */
950 u_clock = 0; /* 33Mhz */
952 udma_enable |= (1 << devid);
954 /* Load the CT/RP selection */
955 pci_read_config_word(dev, 0x4A, &udma_timing);
956 udma_timing &= ~(3 << (4 * devid));
957 udma_timing |= u_speed << (4 * devid);
958 pci_write_config_word(dev, 0x4A, udma_timing);
961 /* Select a 33/66/100Mhz clock */
962 pci_read_config_word(dev, 0x54, &ideconf);
963 ideconf &= ~(0x1001 << devid);
964 ideconf |= u_clock << devid;
965 /* For ICH or later we should set bit 10 for better
966 performance (WR_PingPong_En) */
967 pci_write_config_word(dev, 0x54, ideconf);
970 pci_write_config_byte(dev, 0x48, udma_enable);
972 spin_unlock_irqrestore(&piix_lock, flags);
974 /* MWDMA is driven by the PIO timings. */
975 unsigned int mwdma = speed - XFER_MW_DMA_0;
976 const unsigned int needed_pio[3] = {
977 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
979 int pio = needed_pio[mwdma] - XFER_PIO_0;
981 /* XFER_PIO_0 is never used currently */
982 piix_set_timings(ap, adev, pio);
987 * piix_set_dmamode - Initialize host controller PATA DMA timings
988 * @ap: Port whose timings we are configuring
991 * Set MW/UDMA mode for device, in host controller PCI config space.
994 * None (inherited from caller).
997 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
999 do_pata_set_dmamode(ap, adev, 0);
1003 * ich_set_dmamode - Initialize host controller PATA DMA timings
1004 * @ap: Port whose timings we are configuring
1007 * Set MW/UDMA mode for device, in host controller PCI config space.
1010 * None (inherited from caller).
1013 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
1015 do_pata_set_dmamode(ap, adev, 1);
1019 * Serial ATA Index/Data Pair Superset Registers access
1021 * Beginning from ICH8, there's a sane way to access SCRs using index
1022 * and data register pair located at BAR5 which means that we have
1023 * separate SCRs for master and slave. This is handled using libata
1024 * slave_link facility.
1026 static const int piix_sidx_map[] = {
1032 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
1034 struct ata_port *ap = link->ap;
1035 struct piix_host_priv *hpriv = ap->host->private_data;
1037 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
1038 hpriv->sidpr + PIIX_SIDPR_IDX);
1041 static int piix_sidpr_scr_read(struct ata_link *link,
1042 unsigned int reg, u32 *val)
1044 struct piix_host_priv *hpriv = link->ap->host->private_data;
1046 if (reg >= ARRAY_SIZE(piix_sidx_map))
1049 piix_sidpr_sel(link, reg);
1050 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1054 static int piix_sidpr_scr_write(struct ata_link *link,
1055 unsigned int reg, u32 val)
1057 struct piix_host_priv *hpriv = link->ap->host->private_data;
1059 if (reg >= ARRAY_SIZE(piix_sidx_map))
1062 piix_sidpr_sel(link, reg);
1063 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1067 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1070 return sata_link_scr_lpm(link, policy, false);
1073 static bool piix_irq_check(struct ata_port *ap)
1075 if (unlikely(!ap->ioaddr.bmdma_addr))
1078 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1082 static int piix_broken_suspend(void)
1084 static const struct dmi_system_id sysids[] = {
1086 .ident = "TECRA M3",
1088 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1089 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1093 .ident = "TECRA M3",
1095 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1096 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1100 .ident = "TECRA M4",
1102 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1103 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1107 .ident = "TECRA M4",
1109 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1110 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1114 .ident = "TECRA M5",
1116 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1117 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1121 .ident = "TECRA M6",
1123 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1124 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1128 .ident = "TECRA M7",
1130 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1131 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1135 .ident = "TECRA A8",
1137 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1138 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1142 .ident = "Satellite R20",
1144 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1145 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1149 .ident = "Satellite R25",
1151 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1152 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1156 .ident = "Satellite U200",
1158 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1159 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1163 .ident = "Satellite U200",
1165 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1166 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1170 .ident = "Satellite Pro U200",
1172 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1173 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1177 .ident = "Satellite U205",
1179 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1180 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1184 .ident = "SATELLITE U205",
1186 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1187 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1191 .ident = "Portege M500",
1193 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1194 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1198 .ident = "VGN-BX297XP",
1200 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1201 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1205 { } /* terminate list */
1207 static const char *oemstrs[] = {
1212 if (dmi_check_system(sysids))
1215 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1216 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1219 /* TECRA M4 sometimes forgets its identify and reports bogus
1220 * DMI information. As the bogus information is a bit
1221 * generic, match as many entries as possible. This manual
1222 * matching is necessary because dmi_system_id.matches is
1223 * limited to four entries.
1225 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1226 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1227 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1228 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1229 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1230 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1231 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1237 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1239 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1240 unsigned long flags;
1243 rc = ata_host_suspend(host, mesg);
1247 /* Some braindamaged ACPI suspend implementations expect the
1248 * controller to be awake on entry; otherwise, it burns cpu
1249 * cycles and power trying to do something to the sleeping
1252 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1253 pci_save_state(pdev);
1255 /* mark its power state as "unknown", since we don't
1256 * know if e.g. the BIOS will change its device state
1259 if (pdev->current_state == PCI_D0)
1260 pdev->current_state = PCI_UNKNOWN;
1262 /* tell resume that it's waking up from broken suspend */
1263 spin_lock_irqsave(&host->lock, flags);
1264 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1265 spin_unlock_irqrestore(&host->lock, flags);
1267 ata_pci_device_do_suspend(pdev, mesg);
1272 static int piix_pci_device_resume(struct pci_dev *pdev)
1274 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1275 unsigned long flags;
1278 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1279 spin_lock_irqsave(&host->lock, flags);
1280 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1281 spin_unlock_irqrestore(&host->lock, flags);
1283 pci_set_power_state(pdev, PCI_D0);
1284 pci_restore_state(pdev);
1286 /* PCI device wasn't disabled during suspend. Use
1287 * pci_reenable_device() to avoid affecting the enable
1290 rc = pci_reenable_device(pdev);
1293 "failed to enable device after resume (%d)\n",
1296 rc = ata_pci_device_do_resume(pdev);
1299 ata_host_resume(host);
1305 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1307 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1310 #define AHCI_PCI_BAR 5
1311 #define AHCI_GLOBAL_CTL 0x04
1312 #define AHCI_ENABLE (1 << 31)
1313 static int piix_disable_ahci(struct pci_dev *pdev)
1319 /* BUG: pci_enable_device has not yet been called. This
1320 * works because this device is usually set up by BIOS.
1323 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1324 !pci_resource_len(pdev, AHCI_PCI_BAR))
1327 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1331 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1332 if (tmp & AHCI_ENABLE) {
1333 tmp &= ~AHCI_ENABLE;
1334 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1336 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1337 if (tmp & AHCI_ENABLE)
1341 pci_iounmap(pdev, mmio);
1346 * piix_check_450nx_errata - Check for problem 450NX setup
1347 * @ata_dev: the PCI device to check
1349 * Check for the present of 450NX errata #19 and errata #25. If
1350 * they are found return an error code so we can turn off DMA
1353 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1355 struct pci_dev *pdev = NULL;
1357 int no_piix_dma = 0;
1359 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1360 /* Look for 450NX PXB. Check for problem configurations
1361 A PCI quirk checks bit 6 already */
1362 pci_read_config_word(pdev, 0x41, &cfg);
1363 /* Only on the original revision: IDE DMA can hang */
1364 if (pdev->revision == 0x00)
1366 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1367 else if (cfg & (1<<14) && pdev->revision < 5)
1371 dev_warn(&ata_dev->dev,
1372 "450NX errata present, disabling IDE DMA%s\n",
1373 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1379 static void __devinit piix_init_pcs(struct ata_host *host,
1380 const struct piix_map_db *map_db)
1382 struct pci_dev *pdev = to_pci_dev(host->dev);
1385 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1387 new_pcs = pcs | map_db->port_enable;
1389 if (new_pcs != pcs) {
1390 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1391 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1396 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1397 struct ata_port_info *pinfo,
1398 const struct piix_map_db *map_db)
1401 int i, invalid_map = 0;
1404 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1406 map = map_db->map[map_value & map_db->mask];
1408 dev_info(&pdev->dev, "MAP [");
1409 for (i = 0; i < 4; i++) {
1421 WARN_ON((i & 1) || map[i + 1] != IDE);
1422 pinfo[i / 2] = piix_port_info[ich_pata_100];
1424 pr_cont(" IDE IDE");
1428 pr_cont(" P%d", map[i]);
1430 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1437 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1442 static bool piix_no_sidpr(struct ata_host *host)
1444 struct pci_dev *pdev = to_pci_dev(host->dev);
1447 * Samsung DB-P70 only has three ATA ports exposed and
1448 * curiously the unconnected first port reports link online
1449 * while not responding to SRST protocol causing excessive
1452 * Unfortunately, the system doesn't carry enough DMI
1453 * information to identify the machine but does have subsystem
1454 * vendor and device set. As it's unclear whether the
1455 * subsystem vendor/device is used only for this specific
1456 * board, the port can't be disabled solely with the
1457 * information; however, turning off SIDPR access works around
1458 * the problem. Turn it off.
1460 * This problem is reported in bnc#441240.
1462 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1464 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1465 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1466 pdev->subsystem_device == 0xb049) {
1468 "Samsung DB-P70 detected, disabling SIDPR\n");
1475 static int __devinit piix_init_sidpr(struct ata_host *host)
1477 struct pci_dev *pdev = to_pci_dev(host->dev);
1478 struct piix_host_priv *hpriv = host->private_data;
1479 struct ata_link *link0 = &host->ports[0]->link;
1483 /* check for availability */
1484 for (i = 0; i < 4; i++)
1485 if (hpriv->map[i] == IDE)
1488 /* is it blacklisted? */
1489 if (piix_no_sidpr(host))
1492 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1495 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1496 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1499 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1502 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1504 /* SCR access via SIDPR doesn't work on some configurations.
1505 * Give it a test drive by inhibiting power save modes which
1508 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1510 /* if IPM is already 3, SCR access is probably working. Don't
1511 * un-inhibit power save modes as BIOS might have inhibited
1512 * them for a reason.
1514 if ((scontrol & 0xf00) != 0x300) {
1516 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1517 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1519 if ((scontrol & 0xf00) != 0x300) {
1521 "SCR access via SIDPR is available but doesn't work\n");
1526 /* okay, SCRs available, set ops and ask libata for slave_link */
1527 for (i = 0; i < 2; i++) {
1528 struct ata_port *ap = host->ports[i];
1530 ap->ops = &piix_sidpr_sata_ops;
1532 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1533 rc = ata_slave_link_init(ap);
1542 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1544 static const struct dmi_system_id sysids[] = {
1546 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1547 * isn't used to boot the system which
1548 * disables the channel.
1552 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1553 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1557 { } /* terminate list */
1559 struct pci_dev *pdev = to_pci_dev(host->dev);
1560 struct piix_host_priv *hpriv = host->private_data;
1562 if (!dmi_check_system(sysids))
1565 /* The datasheet says that bit 18 is NOOP but certain systems
1566 * seem to use it to disable a channel. Clear the bit on the
1569 if (hpriv->saved_iocfg & (1 << 18)) {
1570 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1571 pci_write_config_dword(pdev, PIIX_IOCFG,
1572 hpriv->saved_iocfg & ~(1 << 18));
1576 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1578 static const struct dmi_system_id broken_systems[] = {
1580 .ident = "HP Compaq 2510p",
1582 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1583 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1585 /* PCI slot number of the controller */
1586 .driver_data = (void *)0x1FUL,
1589 .ident = "HP Compaq nc6000",
1591 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1592 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1594 /* PCI slot number of the controller */
1595 .driver_data = (void *)0x1FUL,
1598 { } /* terminate list */
1600 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1603 unsigned long slot = (unsigned long)dmi->driver_data;
1604 /* apply the quirk only to on-board controllers */
1605 return slot == PCI_SLOT(pdev->devfn);
1612 * piix_init_one - Register PIIX ATA PCI device with kernel services
1613 * @pdev: PCI device to register
1614 * @ent: Entry in piix_pci_tbl matching with @pdev
1616 * Called from kernel PCI layer. We probe for combined mode (sigh),
1617 * and then hand over control to libata, for it to do the rest.
1620 * Inherited from PCI layer (may sleep).
1623 * Zero on success, or -ERRNO value.
1626 static int __devinit piix_init_one(struct pci_dev *pdev,
1627 const struct pci_device_id *ent)
1629 struct device *dev = &pdev->dev;
1630 struct ata_port_info port_info[2];
1631 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1632 struct scsi_host_template *sht = &piix_sht;
1633 unsigned long port_flags;
1634 struct ata_host *host;
1635 struct piix_host_priv *hpriv;
1638 ata_print_version_once(&pdev->dev, DRV_VERSION);
1640 /* no hotplugging support for later devices (FIXME) */
1641 if (!in_module_init && ent->driver_data >= ich5_sata)
1644 if (piix_broken_system_poweroff(pdev)) {
1645 piix_port_info[ent->driver_data].flags |=
1646 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1647 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1648 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1649 "on poweroff and hibernation\n");
1652 port_info[0] = piix_port_info[ent->driver_data];
1653 port_info[1] = piix_port_info[ent->driver_data];
1655 port_flags = port_info[0].flags;
1657 /* enable device and prepare host */
1658 rc = pcim_enable_device(pdev);
1662 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1666 /* Save IOCFG, this will be used for cable detection, quirk
1667 * detection and restoration on detach. This is necessary
1668 * because some ACPI implementations mess up cable related
1669 * bits on _STM. Reported on kernel bz#11879.
1671 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1673 /* ICH6R may be driven by either ata_piix or ahci driver
1674 * regardless of BIOS configuration. Make sure AHCI mode is
1677 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1678 rc = piix_disable_ahci(pdev);
1683 /* SATA map init can change port_info, do it before prepping host */
1684 if (port_flags & ATA_FLAG_SATA)
1685 hpriv->map = piix_init_sata_map(pdev, port_info,
1686 piix_map_db_table[ent->driver_data]);
1688 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1691 host->private_data = hpriv;
1693 /* initialize controller */
1694 if (port_flags & ATA_FLAG_SATA) {
1695 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1696 rc = piix_init_sidpr(host);
1699 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1700 sht = &piix_sidpr_sht;
1703 /* apply IOCFG bit18 quirk */
1704 piix_iocfg_bit18_quirk(host);
1706 /* On ICH5, some BIOSen disable the interrupt using the
1707 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1708 * On ICH6, this bit has the same effect, but only when
1709 * MSI is disabled (and it is disabled, as we don't use
1710 * message-signalled interrupts currently).
1712 if (port_flags & PIIX_FLAG_CHECKINTR)
1715 if (piix_check_450nx_errata(pdev)) {
1716 /* This writes into the master table but it does not
1717 really matter for this errata as we will apply it to
1718 all the PIIX devices on the board */
1719 host->ports[0]->mwdma_mask = 0;
1720 host->ports[0]->udma_mask = 0;
1721 host->ports[1]->mwdma_mask = 0;
1722 host->ports[1]->udma_mask = 0;
1724 host->flags |= ATA_HOST_PARALLEL_SCAN;
1726 pci_set_master(pdev);
1727 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1730 static void piix_remove_one(struct pci_dev *pdev)
1732 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1733 struct piix_host_priv *hpriv = host->private_data;
1735 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1737 ata_pci_remove_one(pdev);
1740 static int __init piix_init(void)
1744 DPRINTK("pci_register_driver\n");
1745 rc = pci_register_driver(&piix_pci_driver);
1755 static void __exit piix_exit(void)
1757 pci_unregister_driver(&piix_pci_driver);
1760 module_init(piix_init);
1761 module_exit(piix_exit);