2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
121 /* constants for mapping table */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
130 PIIX_AHCI_DEVICE = 6,
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
136 enum piix_controller_ids {
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
149 ich8m_apple_sata, /* locks up on second port enable */
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
159 const u16 port_enable;
163 struct piix_host_priv {
169 static int piix_init_one(struct pci_dev *pdev,
170 const struct pci_device_id *ent);
171 static void piix_remove_one(struct pci_dev *pdev);
172 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
173 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
174 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
175 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
176 static int ich_pata_cable_detect(struct ata_port *ap);
177 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
178 static int piix_sidpr_scr_read(struct ata_link *link,
179 unsigned int reg, u32 *val);
180 static int piix_sidpr_scr_write(struct ata_link *link,
181 unsigned int reg, u32 val);
182 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
184 static bool piix_irq_check(struct ata_port *ap);
185 static int piix_port_start(struct ata_port *ap);
187 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
188 static int piix_pci_device_resume(struct pci_dev *pdev);
191 static unsigned int in_module_init = 1;
193 static const struct pci_device_id piix_pci_tbl[] = {
194 /* Intel PIIX3 for the 430HX etc */
195 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
197 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
198 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
199 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
200 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
202 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
204 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
206 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
207 /* Intel ICH (i810, i815, i840) UDMA 66*/
208 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
209 /* Intel ICH0 : UDMA 33*/
210 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
212 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
214 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* Intel ICH3 (E7500/1) UDMA 100 */
218 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
222 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
225 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
227 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
229 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH6 (and 6) (i915) UDMA 100 */
231 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
232 /* ICH7/7-R (i945, i975) UDMA 100*/
233 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
234 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
235 /* ICH8 Mobile PATA Controller */
236 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
241 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
243 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
244 /* 6300ESB (ICH5 variant with broken PCS present bits) */
245 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
246 /* 6300ESB pretending RAID */
247 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
248 /* 82801FB/FW (ICH6/ICH6W) */
249 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 82801FR/FRW (ICH6R/ICH6RW) */
251 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
252 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
253 * Attach iff the controller is in IDE mode. */
254 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
255 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
256 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
257 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
258 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
259 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
260 /* Enterprise Southbridge 2 (631xESB/632xESB) */
261 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
262 /* SATA Controller 1 IDE (ICH8) */
263 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller 2 IDE (ICH8) */
265 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* Mobile SATA Controller IDE (ICH8M), Apple */
267 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
268 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
269 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
270 /* Mobile SATA Controller IDE (ICH8M) */
271 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH9) */
273 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (ICH9) */
275 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH9) */
277 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH9M) */
279 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH9M) */
281 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282 /* SATA Controller IDE (ICH9M) */
283 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (Tolapai) */
285 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288 /* SATA Controller IDE (ICH10) */
289 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
292 /* SATA Controller IDE (ICH10) */
293 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
299 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
300 /* SATA Controller IDE (PCH) */
301 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 /* SATA Controller IDE (PCH) */
305 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
306 /* SATA Controller IDE (CPT) */
307 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (CPT) */
313 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
316 /* SATA Controller IDE (PBG) */
317 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
318 /* SATA Controller IDE (Panther Point) */
319 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
324 /* SATA Controller IDE (Panther Point) */
325 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
326 /* SATA Controller IDE (Lynx Point) */
327 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
328 /* SATA Controller IDE (Lynx Point) */
329 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
330 /* SATA Controller IDE (Lynx Point) */
331 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
332 /* SATA Controller IDE (Lynx Point) */
333 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
334 /* SATA Controller IDE (Lynx Point-LP) */
335 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
336 /* SATA Controller IDE (Lynx Point-LP) */
337 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
338 /* SATA Controller IDE (Lynx Point-LP) */
339 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
340 /* SATA Controller IDE (Lynx Point-LP) */
341 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
342 /* SATA Controller IDE (DH89xxCC) */
343 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
344 /* SATA Controller IDE (Avoton) */
345 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
346 /* SATA Controller IDE (Avoton) */
347 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
348 /* SATA Controller IDE (Avoton) */
349 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
350 /* SATA Controller IDE (Avoton) */
351 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
352 /* SATA Controller IDE (Wellsburg) */
353 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
354 /* SATA Controller IDE (Wellsburg) */
355 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
356 /* SATA Controller IDE (Wellsburg) */
357 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
358 /* SATA Controller IDE (Wellsburg) */
359 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
360 /* SATA Controller IDE (BayTrail) */
361 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
362 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
363 /* SATA Controller IDE (Coleto Creek) */
364 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
366 { } /* terminate list */
369 static struct pci_driver piix_pci_driver = {
371 .id_table = piix_pci_tbl,
372 .probe = piix_init_one,
373 .remove = piix_remove_one,
375 .suspend = piix_pci_device_suspend,
376 .resume = piix_pci_device_resume,
380 static struct scsi_host_template piix_sht = {
381 ATA_BMDMA_SHT(DRV_NAME),
384 static struct ata_port_operations piix_sata_ops = {
385 .inherits = &ata_bmdma32_port_ops,
386 .sff_irq_check = piix_irq_check,
387 .port_start = piix_port_start,
390 static struct ata_port_operations piix_pata_ops = {
391 .inherits = &piix_sata_ops,
392 .cable_detect = ata_cable_40wire,
393 .set_piomode = piix_set_piomode,
394 .set_dmamode = piix_set_dmamode,
395 .prereset = piix_pata_prereset,
398 static struct ata_port_operations piix_vmw_ops = {
399 .inherits = &piix_pata_ops,
400 .bmdma_status = piix_vmw_bmdma_status,
403 static struct ata_port_operations ich_pata_ops = {
404 .inherits = &piix_pata_ops,
405 .cable_detect = ich_pata_cable_detect,
406 .set_dmamode = ich_set_dmamode,
409 static struct device_attribute *piix_sidpr_shost_attrs[] = {
410 &dev_attr_link_power_management_policy,
414 static struct scsi_host_template piix_sidpr_sht = {
415 ATA_BMDMA_SHT(DRV_NAME),
416 .shost_attrs = piix_sidpr_shost_attrs,
419 static struct ata_port_operations piix_sidpr_sata_ops = {
420 .inherits = &piix_sata_ops,
421 .hardreset = sata_std_hardreset,
422 .scr_read = piix_sidpr_scr_read,
423 .scr_write = piix_sidpr_scr_write,
424 .set_lpm = piix_sidpr_set_lpm,
427 static const struct piix_map_db ich5_map_db = {
431 /* PM PS SM SS MAP */
432 { P0, NA, P1, NA }, /* 000b */
433 { P1, NA, P0, NA }, /* 001b */
436 { P0, P1, IDE, IDE }, /* 100b */
437 { P1, P0, IDE, IDE }, /* 101b */
438 { IDE, IDE, P0, P1 }, /* 110b */
439 { IDE, IDE, P1, P0 }, /* 111b */
443 static const struct piix_map_db ich6_map_db = {
447 /* PM PS SM SS MAP */
448 { P0, P2, P1, P3 }, /* 00b */
449 { IDE, IDE, P1, P3 }, /* 01b */
450 { P0, P2, IDE, IDE }, /* 10b */
455 static const struct piix_map_db ich6m_map_db = {
459 /* Map 01b isn't specified in the doc but some notebooks use
460 * it anyway. MAP 01b have been spotted on both ICH6M and
464 /* PM PS SM SS MAP */
465 { P0, P2, NA, NA }, /* 00b */
466 { IDE, IDE, P1, P3 }, /* 01b */
467 { P0, P2, IDE, IDE }, /* 10b */
472 static const struct piix_map_db ich8_map_db = {
476 /* PM PS SM SS MAP */
477 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
479 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
484 static const struct piix_map_db ich8_2port_map_db = {
488 /* PM PS SM SS MAP */
489 { P0, NA, P1, NA }, /* 00b */
490 { RV, RV, RV, RV }, /* 01b */
491 { RV, RV, RV, RV }, /* 10b */
496 static const struct piix_map_db ich8m_apple_map_db = {
500 /* PM PS SM SS MAP */
501 { P0, NA, NA, NA }, /* 00b */
503 { P0, P2, IDE, IDE }, /* 10b */
508 static const struct piix_map_db tolapai_map_db = {
512 /* PM PS SM SS MAP */
513 { P0, NA, P1, NA }, /* 00b */
514 { RV, RV, RV, RV }, /* 01b */
515 { RV, RV, RV, RV }, /* 10b */
520 static const struct piix_map_db *piix_map_db_table[] = {
521 [ich5_sata] = &ich5_map_db,
522 [ich6_sata] = &ich6_map_db,
523 [ich6m_sata] = &ich6m_map_db,
524 [ich8_sata] = &ich8_map_db,
525 [ich8_2port_sata] = &ich8_2port_map_db,
526 [ich8m_apple_sata] = &ich8m_apple_map_db,
527 [tolapai_sata] = &tolapai_map_db,
528 [ich8_sata_snb] = &ich8_map_db,
529 [ich8_2port_sata_snb] = &ich8_2port_map_db,
530 [ich8_2port_sata_byt] = &ich8_2port_map_db,
533 static struct ata_port_info piix_port_info[] = {
534 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
536 .flags = PIIX_PATA_FLAGS,
537 .pio_mask = ATA_PIO4,
538 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
539 .port_ops = &piix_pata_ops,
542 [piix_pata_33] = /* PIIX4 at 33MHz */
544 .flags = PIIX_PATA_FLAGS,
545 .pio_mask = ATA_PIO4,
546 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
547 .udma_mask = ATA_UDMA2,
548 .port_ops = &piix_pata_ops,
551 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
553 .flags = PIIX_PATA_FLAGS,
554 .pio_mask = ATA_PIO4,
555 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
556 .udma_mask = ATA_UDMA2,
557 .port_ops = &ich_pata_ops,
560 [ich_pata_66] = /* ICH controllers up to 66MHz */
562 .flags = PIIX_PATA_FLAGS,
563 .pio_mask = ATA_PIO4,
564 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
565 .udma_mask = ATA_UDMA4,
566 .port_ops = &ich_pata_ops,
571 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
572 .pio_mask = ATA_PIO4,
573 .mwdma_mask = ATA_MWDMA12_ONLY,
574 .udma_mask = ATA_UDMA5,
575 .port_ops = &ich_pata_ops,
578 [ich_pata_100_nomwdma1] =
580 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
581 .pio_mask = ATA_PIO4,
582 .mwdma_mask = ATA_MWDMA2_ONLY,
583 .udma_mask = ATA_UDMA5,
584 .port_ops = &ich_pata_ops,
589 .flags = PIIX_SATA_FLAGS,
590 .pio_mask = ATA_PIO4,
591 .mwdma_mask = ATA_MWDMA2,
592 .udma_mask = ATA_UDMA6,
593 .port_ops = &piix_sata_ops,
598 .flags = PIIX_SATA_FLAGS,
599 .pio_mask = ATA_PIO4,
600 .mwdma_mask = ATA_MWDMA2,
601 .udma_mask = ATA_UDMA6,
602 .port_ops = &piix_sata_ops,
607 .flags = PIIX_SATA_FLAGS,
608 .pio_mask = ATA_PIO4,
609 .mwdma_mask = ATA_MWDMA2,
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &piix_sata_ops,
616 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
617 .pio_mask = ATA_PIO4,
618 .mwdma_mask = ATA_MWDMA2,
619 .udma_mask = ATA_UDMA6,
620 .port_ops = &piix_sata_ops,
625 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
626 .pio_mask = ATA_PIO4,
627 .mwdma_mask = ATA_MWDMA2,
628 .udma_mask = ATA_UDMA6,
629 .port_ops = &piix_sata_ops,
634 .flags = PIIX_SATA_FLAGS,
635 .pio_mask = ATA_PIO4,
636 .mwdma_mask = ATA_MWDMA2,
637 .udma_mask = ATA_UDMA6,
638 .port_ops = &piix_sata_ops,
643 .flags = PIIX_SATA_FLAGS,
644 .pio_mask = ATA_PIO4,
645 .mwdma_mask = ATA_MWDMA2,
646 .udma_mask = ATA_UDMA6,
647 .port_ops = &piix_sata_ops,
652 .flags = PIIX_PATA_FLAGS,
653 .pio_mask = ATA_PIO4,
654 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
655 .udma_mask = ATA_UDMA2,
656 .port_ops = &piix_vmw_ops,
660 * some Sandybridge chipsets have broken 32 mode up to now,
661 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
665 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
666 .pio_mask = ATA_PIO4,
667 .mwdma_mask = ATA_MWDMA2,
668 .udma_mask = ATA_UDMA6,
669 .port_ops = &piix_sata_ops,
672 [ich8_2port_sata_snb] =
674 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
676 .pio_mask = ATA_PIO4,
677 .mwdma_mask = ATA_MWDMA2,
678 .udma_mask = ATA_UDMA6,
679 .port_ops = &piix_sata_ops,
682 [ich8_2port_sata_byt] =
684 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
685 .pio_mask = ATA_PIO4,
686 .mwdma_mask = ATA_MWDMA2,
687 .udma_mask = ATA_UDMA6,
688 .port_ops = &piix_sata_ops,
693 static struct pci_bits piix_enable_bits[] = {
694 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
695 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
698 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
699 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
700 MODULE_LICENSE("GPL");
701 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
702 MODULE_VERSION(DRV_VERSION);
711 * List of laptops that use short cables rather than 80 wire
714 static const struct ich_laptop ich_laptop[] = {
715 /* devid, subvendor, subdev */
716 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
717 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
718 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
719 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
720 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
721 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
722 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
723 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
724 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
725 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
726 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
727 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
728 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
729 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
734 static int piix_port_start(struct ata_port *ap)
736 if (!(ap->flags & PIIX_FLAG_PIO16))
737 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
739 return ata_bmdma_port_start(ap);
743 * ich_pata_cable_detect - Probe host controller cable detect info
744 * @ap: Port for which cable detect info is desired
746 * Read 80c cable indicator from ATA PCI device's PCI config
747 * register. This register is normally set by firmware (BIOS).
750 * None (inherited from caller).
753 static int ich_pata_cable_detect(struct ata_port *ap)
755 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
756 struct piix_host_priv *hpriv = ap->host->private_data;
757 const struct ich_laptop *lap = &ich_laptop[0];
760 /* Check for specials - Acer Aspire 5602WLMi */
761 while (lap->device) {
762 if (lap->device == pdev->device &&
763 lap->subvendor == pdev->subsystem_vendor &&
764 lap->subdevice == pdev->subsystem_device)
765 return ATA_CBL_PATA40_SHORT;
770 /* check BIOS cable detect results */
771 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
772 if ((hpriv->saved_iocfg & mask) == 0)
773 return ATA_CBL_PATA40;
774 return ATA_CBL_PATA80;
778 * piix_pata_prereset - prereset for PATA host controller
780 * @deadline: deadline jiffies for the operation
783 * None (inherited from caller).
785 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
787 struct ata_port *ap = link->ap;
788 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
790 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
792 return ata_sff_prereset(link, deadline);
795 static DEFINE_SPINLOCK(piix_lock);
797 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
800 struct pci_dev *dev = to_pci_dev(ap->host->dev);
802 unsigned int is_slave = (adev->devno != 0);
803 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
804 unsigned int slave_port = 0x44;
811 * See Intel Document 298600-004 for the timing programing rules
812 * for ICH controllers.
815 static const /* ISP RTC */
816 u8 timings[][2] = { { 0, 0 },
823 control |= 1; /* TIME1 enable */
824 if (ata_pio_need_iordy(adev))
825 control |= 2; /* IE enable */
826 /* Intel specifies that the PPE functionality is for disk only */
827 if (adev->class == ATA_DEV_ATA)
828 control |= 4; /* PPE enable */
830 * If the drive MWDMA is faster than it can do PIO then
831 * we must force PIO into PIO0
833 if (adev->pio_mode < XFER_PIO_0 + pio)
834 /* Enable DMA timing only */
835 control |= 8; /* PIO cycles in PIO0 */
837 spin_lock_irqsave(&piix_lock, flags);
839 /* PIO configuration clears DTE unconditionally. It will be
840 * programmed in set_dmamode which is guaranteed to be called
841 * after set_piomode if any DMA mode is available.
843 pci_read_config_word(dev, master_port, &master_data);
845 /* clear TIME1|IE1|PPE1|DTE1 */
846 master_data &= 0xff0f;
847 /* enable PPE1, IE1 and TIME1 as needed */
848 master_data |= (control << 4);
849 pci_read_config_byte(dev, slave_port, &slave_data);
850 slave_data &= (ap->port_no ? 0x0f : 0xf0);
851 /* Load the timing nibble for this slave */
852 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
853 << (ap->port_no ? 4 : 0);
855 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
856 master_data &= 0xccf0;
857 /* Enable PPE, IE and TIME as appropriate */
858 master_data |= control;
859 /* load ISP and RCT */
861 (timings[pio][0] << 12) |
862 (timings[pio][1] << 8);
865 /* Enable SITRE (separate slave timing register) */
866 master_data |= 0x4000;
867 pci_write_config_word(dev, master_port, master_data);
869 pci_write_config_byte(dev, slave_port, slave_data);
871 /* Ensure the UDMA bit is off - it will be turned back on if
875 pci_read_config_byte(dev, 0x48, &udma_enable);
876 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
877 pci_write_config_byte(dev, 0x48, udma_enable);
880 spin_unlock_irqrestore(&piix_lock, flags);
884 * piix_set_piomode - Initialize host controller PATA PIO timings
885 * @ap: Port whose timings we are configuring
886 * @adev: Drive in question
888 * Set PIO mode for device, in host controller PCI config space.
891 * None (inherited from caller).
894 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
896 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
900 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
901 * @ap: Port whose timings we are configuring
902 * @adev: Drive in question
903 * @isich: set if the chip is an ICH device
905 * Set UDMA mode for device, in host controller PCI config space.
908 * None (inherited from caller).
911 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
913 struct pci_dev *dev = to_pci_dev(ap->host->dev);
915 u8 speed = adev->dma_mode;
916 int devid = adev->devno + 2 * ap->port_no;
919 if (speed >= XFER_UDMA_0) {
920 unsigned int udma = speed - XFER_UDMA_0;
923 int u_clock, u_speed;
925 spin_lock_irqsave(&piix_lock, flags);
927 pci_read_config_byte(dev, 0x48, &udma_enable);
930 * UDMA is handled by a combination of clock switching and
931 * selection of dividers
933 * Handy rule: Odd modes are UDMATIMx 01, even are 02
934 * except UDMA0 which is 00
936 u_speed = min(2 - (udma & 1), udma);
938 u_clock = 0x1000; /* 100Mhz */
940 u_clock = 1; /* 66Mhz */
942 u_clock = 0; /* 33Mhz */
944 udma_enable |= (1 << devid);
946 /* Load the CT/RP selection */
947 pci_read_config_word(dev, 0x4A, &udma_timing);
948 udma_timing &= ~(3 << (4 * devid));
949 udma_timing |= u_speed << (4 * devid);
950 pci_write_config_word(dev, 0x4A, udma_timing);
953 /* Select a 33/66/100Mhz clock */
954 pci_read_config_word(dev, 0x54, &ideconf);
955 ideconf &= ~(0x1001 << devid);
956 ideconf |= u_clock << devid;
957 /* For ICH or later we should set bit 10 for better
958 performance (WR_PingPong_En) */
959 pci_write_config_word(dev, 0x54, ideconf);
962 pci_write_config_byte(dev, 0x48, udma_enable);
964 spin_unlock_irqrestore(&piix_lock, flags);
966 /* MWDMA is driven by the PIO timings. */
967 unsigned int mwdma = speed - XFER_MW_DMA_0;
968 const unsigned int needed_pio[3] = {
969 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
971 int pio = needed_pio[mwdma] - XFER_PIO_0;
973 /* XFER_PIO_0 is never used currently */
974 piix_set_timings(ap, adev, pio);
979 * piix_set_dmamode - Initialize host controller PATA DMA timings
980 * @ap: Port whose timings we are configuring
983 * Set MW/UDMA mode for device, in host controller PCI config space.
986 * None (inherited from caller).
989 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
991 do_pata_set_dmamode(ap, adev, 0);
995 * ich_set_dmamode - Initialize host controller PATA DMA timings
996 * @ap: Port whose timings we are configuring
999 * Set MW/UDMA mode for device, in host controller PCI config space.
1002 * None (inherited from caller).
1005 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
1007 do_pata_set_dmamode(ap, adev, 1);
1011 * Serial ATA Index/Data Pair Superset Registers access
1013 * Beginning from ICH8, there's a sane way to access SCRs using index
1014 * and data register pair located at BAR5 which means that we have
1015 * separate SCRs for master and slave. This is handled using libata
1016 * slave_link facility.
1018 static const int piix_sidx_map[] = {
1024 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
1026 struct ata_port *ap = link->ap;
1027 struct piix_host_priv *hpriv = ap->host->private_data;
1029 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
1030 hpriv->sidpr + PIIX_SIDPR_IDX);
1033 static int piix_sidpr_scr_read(struct ata_link *link,
1034 unsigned int reg, u32 *val)
1036 struct piix_host_priv *hpriv = link->ap->host->private_data;
1038 if (reg >= ARRAY_SIZE(piix_sidx_map))
1041 piix_sidpr_sel(link, reg);
1042 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1046 static int piix_sidpr_scr_write(struct ata_link *link,
1047 unsigned int reg, u32 val)
1049 struct piix_host_priv *hpriv = link->ap->host->private_data;
1051 if (reg >= ARRAY_SIZE(piix_sidx_map))
1054 piix_sidpr_sel(link, reg);
1055 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1059 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1062 return sata_link_scr_lpm(link, policy, false);
1065 static bool piix_irq_check(struct ata_port *ap)
1067 if (unlikely(!ap->ioaddr.bmdma_addr))
1070 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1074 static int piix_broken_suspend(void)
1076 static const struct dmi_system_id sysids[] = {
1078 .ident = "TECRA M3",
1080 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1081 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1085 .ident = "TECRA M3",
1087 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1088 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1092 .ident = "TECRA M4",
1094 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1095 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1099 .ident = "TECRA M4",
1101 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1102 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1106 .ident = "TECRA M5",
1108 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1109 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1113 .ident = "TECRA M6",
1115 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1120 .ident = "TECRA M7",
1122 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1123 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1127 .ident = "TECRA A8",
1129 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1130 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1134 .ident = "Satellite R20",
1136 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1137 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1141 .ident = "Satellite R25",
1143 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1144 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1148 .ident = "Satellite U200",
1150 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1151 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1155 .ident = "Satellite U200",
1157 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1162 .ident = "Satellite Pro U200",
1164 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1169 .ident = "Satellite U205",
1171 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1172 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1176 .ident = "SATELLITE U205",
1178 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1179 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1183 .ident = "Portege M500",
1185 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1186 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1190 .ident = "VGN-BX297XP",
1192 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1193 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1197 { } /* terminate list */
1199 static const char *oemstrs[] = {
1204 if (dmi_check_system(sysids))
1207 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1208 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1211 /* TECRA M4 sometimes forgets its identify and reports bogus
1212 * DMI information. As the bogus information is a bit
1213 * generic, match as many entries as possible. This manual
1214 * matching is necessary because dmi_system_id.matches is
1215 * limited to four entries.
1217 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1218 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1219 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1220 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1221 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1222 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1223 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1229 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1231 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1232 unsigned long flags;
1235 rc = ata_host_suspend(host, mesg);
1239 /* Some braindamaged ACPI suspend implementations expect the
1240 * controller to be awake on entry; otherwise, it burns cpu
1241 * cycles and power trying to do something to the sleeping
1244 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1245 pci_save_state(pdev);
1247 /* mark its power state as "unknown", since we don't
1248 * know if e.g. the BIOS will change its device state
1251 if (pdev->current_state == PCI_D0)
1252 pdev->current_state = PCI_UNKNOWN;
1254 /* tell resume that it's waking up from broken suspend */
1255 spin_lock_irqsave(&host->lock, flags);
1256 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1257 spin_unlock_irqrestore(&host->lock, flags);
1259 ata_pci_device_do_suspend(pdev, mesg);
1264 static int piix_pci_device_resume(struct pci_dev *pdev)
1266 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1267 unsigned long flags;
1270 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1271 spin_lock_irqsave(&host->lock, flags);
1272 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1273 spin_unlock_irqrestore(&host->lock, flags);
1275 pci_set_power_state(pdev, PCI_D0);
1276 pci_restore_state(pdev);
1278 /* PCI device wasn't disabled during suspend. Use
1279 * pci_reenable_device() to avoid affecting the enable
1282 rc = pci_reenable_device(pdev);
1285 "failed to enable device after resume (%d)\n",
1288 rc = ata_pci_device_do_resume(pdev);
1291 ata_host_resume(host);
1297 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1299 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1302 #define AHCI_PCI_BAR 5
1303 #define AHCI_GLOBAL_CTL 0x04
1304 #define AHCI_ENABLE (1 << 31)
1305 static int piix_disable_ahci(struct pci_dev *pdev)
1311 /* BUG: pci_enable_device has not yet been called. This
1312 * works because this device is usually set up by BIOS.
1315 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1316 !pci_resource_len(pdev, AHCI_PCI_BAR))
1319 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1323 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1324 if (tmp & AHCI_ENABLE) {
1325 tmp &= ~AHCI_ENABLE;
1326 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1328 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1329 if (tmp & AHCI_ENABLE)
1333 pci_iounmap(pdev, mmio);
1338 * piix_check_450nx_errata - Check for problem 450NX setup
1339 * @ata_dev: the PCI device to check
1341 * Check for the present of 450NX errata #19 and errata #25. If
1342 * they are found return an error code so we can turn off DMA
1345 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1347 struct pci_dev *pdev = NULL;
1349 int no_piix_dma = 0;
1351 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1352 /* Look for 450NX PXB. Check for problem configurations
1353 A PCI quirk checks bit 6 already */
1354 pci_read_config_word(pdev, 0x41, &cfg);
1355 /* Only on the original revision: IDE DMA can hang */
1356 if (pdev->revision == 0x00)
1358 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1359 else if (cfg & (1<<14) && pdev->revision < 5)
1363 dev_warn(&ata_dev->dev,
1364 "450NX errata present, disabling IDE DMA%s\n",
1365 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1371 static void __devinit piix_init_pcs(struct ata_host *host,
1372 const struct piix_map_db *map_db)
1374 struct pci_dev *pdev = to_pci_dev(host->dev);
1377 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1379 new_pcs = pcs | map_db->port_enable;
1381 if (new_pcs != pcs) {
1382 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1383 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1388 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1389 struct ata_port_info *pinfo,
1390 const struct piix_map_db *map_db)
1393 int i, invalid_map = 0;
1396 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1398 map = map_db->map[map_value & map_db->mask];
1400 dev_info(&pdev->dev, "MAP [");
1401 for (i = 0; i < 4; i++) {
1413 WARN_ON((i & 1) || map[i + 1] != IDE);
1414 pinfo[i / 2] = piix_port_info[ich_pata_100];
1416 pr_cont(" IDE IDE");
1420 pr_cont(" P%d", map[i]);
1422 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1429 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1434 static bool piix_no_sidpr(struct ata_host *host)
1436 struct pci_dev *pdev = to_pci_dev(host->dev);
1439 * Samsung DB-P70 only has three ATA ports exposed and
1440 * curiously the unconnected first port reports link online
1441 * while not responding to SRST protocol causing excessive
1444 * Unfortunately, the system doesn't carry enough DMI
1445 * information to identify the machine but does have subsystem
1446 * vendor and device set. As it's unclear whether the
1447 * subsystem vendor/device is used only for this specific
1448 * board, the port can't be disabled solely with the
1449 * information; however, turning off SIDPR access works around
1450 * the problem. Turn it off.
1452 * This problem is reported in bnc#441240.
1454 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1456 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1457 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1458 pdev->subsystem_device == 0xb049) {
1460 "Samsung DB-P70 detected, disabling SIDPR\n");
1467 static int __devinit piix_init_sidpr(struct ata_host *host)
1469 struct pci_dev *pdev = to_pci_dev(host->dev);
1470 struct piix_host_priv *hpriv = host->private_data;
1471 struct ata_link *link0 = &host->ports[0]->link;
1475 /* check for availability */
1476 for (i = 0; i < 4; i++)
1477 if (hpriv->map[i] == IDE)
1480 /* is it blacklisted? */
1481 if (piix_no_sidpr(host))
1484 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1487 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1488 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1491 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1494 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1496 /* SCR access via SIDPR doesn't work on some configurations.
1497 * Give it a test drive by inhibiting power save modes which
1500 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1502 /* if IPM is already 3, SCR access is probably working. Don't
1503 * un-inhibit power save modes as BIOS might have inhibited
1504 * them for a reason.
1506 if ((scontrol & 0xf00) != 0x300) {
1508 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1509 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1511 if ((scontrol & 0xf00) != 0x300) {
1513 "SCR access via SIDPR is available but doesn't work\n");
1518 /* okay, SCRs available, set ops and ask libata for slave_link */
1519 for (i = 0; i < 2; i++) {
1520 struct ata_port *ap = host->ports[i];
1522 ap->ops = &piix_sidpr_sata_ops;
1524 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1525 rc = ata_slave_link_init(ap);
1534 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1536 static const struct dmi_system_id sysids[] = {
1538 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1539 * isn't used to boot the system which
1540 * disables the channel.
1544 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1545 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1549 { } /* terminate list */
1551 struct pci_dev *pdev = to_pci_dev(host->dev);
1552 struct piix_host_priv *hpriv = host->private_data;
1554 if (!dmi_check_system(sysids))
1557 /* The datasheet says that bit 18 is NOOP but certain systems
1558 * seem to use it to disable a channel. Clear the bit on the
1561 if (hpriv->saved_iocfg & (1 << 18)) {
1562 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1563 pci_write_config_dword(pdev, PIIX_IOCFG,
1564 hpriv->saved_iocfg & ~(1 << 18));
1568 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1570 static const struct dmi_system_id broken_systems[] = {
1572 .ident = "HP Compaq 2510p",
1574 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1575 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1577 /* PCI slot number of the controller */
1578 .driver_data = (void *)0x1FUL,
1581 .ident = "HP Compaq nc6000",
1583 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1584 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1586 /* PCI slot number of the controller */
1587 .driver_data = (void *)0x1FUL,
1590 { } /* terminate list */
1592 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1595 unsigned long slot = (unsigned long)dmi->driver_data;
1596 /* apply the quirk only to on-board controllers */
1597 return slot == PCI_SLOT(pdev->devfn);
1604 * piix_init_one - Register PIIX ATA PCI device with kernel services
1605 * @pdev: PCI device to register
1606 * @ent: Entry in piix_pci_tbl matching with @pdev
1608 * Called from kernel PCI layer. We probe for combined mode (sigh),
1609 * and then hand over control to libata, for it to do the rest.
1612 * Inherited from PCI layer (may sleep).
1615 * Zero on success, or -ERRNO value.
1618 static int __devinit piix_init_one(struct pci_dev *pdev,
1619 const struct pci_device_id *ent)
1621 struct device *dev = &pdev->dev;
1622 struct ata_port_info port_info[2];
1623 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1624 struct scsi_host_template *sht = &piix_sht;
1625 unsigned long port_flags;
1626 struct ata_host *host;
1627 struct piix_host_priv *hpriv;
1630 ata_print_version_once(&pdev->dev, DRV_VERSION);
1632 /* no hotplugging support for later devices (FIXME) */
1633 if (!in_module_init && ent->driver_data >= ich5_sata)
1636 if (piix_broken_system_poweroff(pdev)) {
1637 piix_port_info[ent->driver_data].flags |=
1638 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1639 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1640 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1641 "on poweroff and hibernation\n");
1644 port_info[0] = piix_port_info[ent->driver_data];
1645 port_info[1] = piix_port_info[ent->driver_data];
1647 port_flags = port_info[0].flags;
1649 /* enable device and prepare host */
1650 rc = pcim_enable_device(pdev);
1654 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1658 /* Save IOCFG, this will be used for cable detection, quirk
1659 * detection and restoration on detach. This is necessary
1660 * because some ACPI implementations mess up cable related
1661 * bits on _STM. Reported on kernel bz#11879.
1663 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1665 /* ICH6R may be driven by either ata_piix or ahci driver
1666 * regardless of BIOS configuration. Make sure AHCI mode is
1669 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1670 rc = piix_disable_ahci(pdev);
1675 /* SATA map init can change port_info, do it before prepping host */
1676 if (port_flags & ATA_FLAG_SATA)
1677 hpriv->map = piix_init_sata_map(pdev, port_info,
1678 piix_map_db_table[ent->driver_data]);
1680 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1683 host->private_data = hpriv;
1685 /* initialize controller */
1686 if (port_flags & ATA_FLAG_SATA) {
1687 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1688 rc = piix_init_sidpr(host);
1691 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1692 sht = &piix_sidpr_sht;
1695 /* apply IOCFG bit18 quirk */
1696 piix_iocfg_bit18_quirk(host);
1698 /* On ICH5, some BIOSen disable the interrupt using the
1699 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1700 * On ICH6, this bit has the same effect, but only when
1701 * MSI is disabled (and it is disabled, as we don't use
1702 * message-signalled interrupts currently).
1704 if (port_flags & PIIX_FLAG_CHECKINTR)
1707 if (piix_check_450nx_errata(pdev)) {
1708 /* This writes into the master table but it does not
1709 really matter for this errata as we will apply it to
1710 all the PIIX devices on the board */
1711 host->ports[0]->mwdma_mask = 0;
1712 host->ports[0]->udma_mask = 0;
1713 host->ports[1]->mwdma_mask = 0;
1714 host->ports[1]->udma_mask = 0;
1716 host->flags |= ATA_HOST_PARALLEL_SCAN;
1718 pci_set_master(pdev);
1719 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1722 static void piix_remove_one(struct pci_dev *pdev)
1724 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1725 struct piix_host_priv *hpriv = host->private_data;
1727 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1729 ata_pci_remove_one(pdev);
1732 static int __init piix_init(void)
1736 DPRINTK("pci_register_driver\n");
1737 rc = pci_register_driver(&piix_pci_driver);
1747 static void __exit piix_exit(void)
1749 pci_unregister_driver(&piix_pci_driver);
1752 module_init(piix_init);
1753 module_exit(piix_exit);