2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
60 /* board IDs by feature in alphabetical order */
66 /* board IDs for specific chipsets in alphabetical order */
72 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89 static int ahci_pci_device_resume(struct pci_dev *pdev);
92 static struct scsi_host_template ahci_sht = {
96 static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
101 static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
106 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
108 static const struct ata_port_info ahci_port_info[] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
117 [board_ahci_ign_iferr] =
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
125 [board_ahci_nosntf] =
127 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
133 [board_ahci_yes_fbs] =
135 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
144 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
146 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_pmp_retry_srst_ops,
186 [board_ahci_sb700] = /* for SB700 and SB800 */
188 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_pmp_retry_srst_ops,
194 [board_ahci_vt8251] =
196 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_vt8251_ops,
204 static const struct pci_device_id ahci_pci_tbl[] = {
206 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
207 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
208 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
209 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
210 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
211 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
212 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
216 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
244 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
253 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
379 /* ST Microelectronics */
380 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
383 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
384 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
385 { PCI_DEVICE(0x1b4b, 0x9123),
386 .class = PCI_CLASS_STORAGE_SATA_AHCI,
387 .class_mask = 0xffffff,
388 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
389 { PCI_DEVICE(0x1b4b, 0x9125),
390 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
391 { PCI_DEVICE(0x1b4b, 0x917a),
392 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
393 { PCI_DEVICE(0x1b4b, 0x9192),
394 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
395 { PCI_DEVICE(0x1b4b, 0x91a3),
396 .driver_data = board_ahci_yes_fbs },
399 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
402 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
403 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
404 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
405 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
407 /* Generic, PCI class code for AHCI */
408 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
409 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
411 { } /* terminate list */
415 static struct pci_driver ahci_pci_driver = {
417 .id_table = ahci_pci_tbl,
418 .probe = ahci_init_one,
419 .remove = ata_pci_remove_one,
421 .suspend = ahci_pci_device_suspend,
422 .resume = ahci_pci_device_resume,
426 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
427 static int marvell_enable;
429 static int marvell_enable = 1;
431 module_param(marvell_enable, int, 0644);
432 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
435 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
436 struct ahci_host_priv *hpriv)
438 unsigned int force_port_map = 0;
439 unsigned int mask_port_map = 0;
441 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
442 dev_info(&pdev->dev, "JMB361 has only one port\n");
447 * Temporary Marvell 6145 hack: PATA port presence
448 * is asserted through the standard AHCI port
449 * presence register, as bit 4 (counting from 0)
451 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
452 if (pdev->device == 0x6121)
457 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
460 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
464 static int ahci_pci_reset_controller(struct ata_host *host)
466 struct pci_dev *pdev = to_pci_dev(host->dev);
468 ahci_reset_controller(host);
470 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
471 struct ahci_host_priv *hpriv = host->private_data;
475 pci_read_config_word(pdev, 0x92, &tmp16);
476 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
477 tmp16 |= hpriv->port_map;
478 pci_write_config_word(pdev, 0x92, tmp16);
485 static void ahci_pci_init_controller(struct ata_host *host)
487 struct ahci_host_priv *hpriv = host->private_data;
488 struct pci_dev *pdev = to_pci_dev(host->dev);
489 void __iomem *port_mmio;
493 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
494 if (pdev->device == 0x6121)
498 port_mmio = __ahci_port_base(host, mv);
500 writel(0, port_mmio + PORT_IRQ_MASK);
503 tmp = readl(port_mmio + PORT_IRQ_STAT);
504 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
506 writel(tmp, port_mmio + PORT_IRQ_STAT);
509 ahci_init_controller(host);
512 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
513 unsigned long deadline)
515 struct ata_port *ap = link->ap;
521 ahci_stop_engine(ap);
523 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
524 deadline, &online, NULL);
526 ahci_start_engine(ap);
528 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
530 /* vt8251 doesn't clear BSY on signature FIS reception,
531 * request follow-up softreset.
533 return online ? -EAGAIN : rc;
536 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
537 unsigned long deadline)
539 struct ata_port *ap = link->ap;
540 struct ahci_port_priv *pp = ap->private_data;
541 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
542 struct ata_taskfile tf;
546 ahci_stop_engine(ap);
548 /* clear D2H reception area to properly wait for D2H FIS */
549 ata_tf_init(link->device, &tf);
551 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
553 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
554 deadline, &online, NULL);
556 ahci_start_engine(ap);
558 /* The pseudo configuration device on SIMG4726 attached to
559 * ASUS P5W-DH Deluxe doesn't send signature FIS after
560 * hardreset if no device is attached to the first downstream
561 * port && the pseudo device locks up on SRST w/ PMP==0. To
562 * work around this, wait for !BSY only briefly. If BSY isn't
563 * cleared, perform CLO and proceed to IDENTIFY (achieved by
564 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
566 * Wait for two seconds. Devices attached to downstream port
567 * which can't process the following IDENTIFY after this will
568 * have to be reset again. For most cases, this should
569 * suffice while making probing snappish enough.
572 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
575 ahci_kick_engine(ap);
581 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
583 struct ata_host *host = dev_get_drvdata(&pdev->dev);
584 struct ahci_host_priv *hpriv = host->private_data;
585 void __iomem *mmio = hpriv->mmio;
588 if (mesg.event & PM_EVENT_SUSPEND &&
589 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
591 "BIOS update required for suspend/resume\n");
595 if (mesg.event & PM_EVENT_SLEEP) {
596 /* AHCI spec rev1.1 section 8.3.3:
597 * Software must disable interrupts prior to requesting a
598 * transition of the HBA to D3 state.
600 ctl = readl(mmio + HOST_CTL);
602 writel(ctl, mmio + HOST_CTL);
603 readl(mmio + HOST_CTL); /* flush */
606 return ata_pci_device_suspend(pdev, mesg);
609 static int ahci_pci_device_resume(struct pci_dev *pdev)
611 struct ata_host *host = dev_get_drvdata(&pdev->dev);
614 rc = ata_pci_device_do_resume(pdev);
618 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
619 rc = ahci_pci_reset_controller(host);
623 ahci_pci_init_controller(host);
626 ata_host_resume(host);
632 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
637 * If the device fixup already set the dma_mask to some non-standard
638 * value, don't extend it here. This happens on STA2X11, for example.
640 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
644 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
645 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
647 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
650 "64-bit DMA enable failed\n");
655 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
657 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
660 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
663 "32-bit consistent DMA enable failed\n");
670 static void ahci_pci_print_info(struct ata_host *host)
672 struct pci_dev *pdev = to_pci_dev(host->dev);
676 pci_read_config_word(pdev, 0x0a, &cc);
677 if (cc == PCI_CLASS_STORAGE_IDE)
679 else if (cc == PCI_CLASS_STORAGE_SATA)
681 else if (cc == PCI_CLASS_STORAGE_RAID)
686 ahci_print_info(host, scc_s);
689 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
690 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
691 * support PMP and the 4726 either directly exports the device
692 * attached to the first downstream port or acts as a hardware storage
693 * controller and emulate a single ATA device (can be RAID 0/1 or some
694 * other configuration).
696 * When there's no device attached to the first downstream port of the
697 * 4726, "Config Disk" appears, which is a pseudo ATA device to
698 * configure the 4726. However, ATA emulation of the device is very
699 * lame. It doesn't send signature D2H Reg FIS after the initial
700 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
702 * The following function works around the problem by always using
703 * hardreset on the port and not depending on receiving signature FIS
704 * afterward. If signature FIS isn't received soon, ATA class is
705 * assumed without follow-up softreset.
707 static void ahci_p5wdh_workaround(struct ata_host *host)
709 static struct dmi_system_id sysids[] = {
711 .ident = "P5W DH Deluxe",
713 DMI_MATCH(DMI_SYS_VENDOR,
714 "ASUSTEK COMPUTER INC"),
715 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
720 struct pci_dev *pdev = to_pci_dev(host->dev);
722 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
723 dmi_check_system(sysids)) {
724 struct ata_port *ap = host->ports[1];
727 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
729 ap->ops = &ahci_p5wdh_ops;
730 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
734 /* only some SB600 ahci controllers can do 64bit DMA */
735 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
737 static const struct dmi_system_id sysids[] = {
739 * The oldest version known to be broken is 0901 and
740 * working is 1501 which was released on 2007-10-26.
741 * Enable 64bit DMA on 1501 and anything newer.
743 * Please read bko#9412 for more info.
746 .ident = "ASUS M2A-VM",
748 DMI_MATCH(DMI_BOARD_VENDOR,
749 "ASUSTeK Computer INC."),
750 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
752 .driver_data = "20071026", /* yyyymmdd */
755 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
758 * BIOS versions earlier than 1.5 had the Manufacturer DMI
759 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
760 * This spelling mistake was fixed in BIOS version 1.5, so
761 * 1.5 and later have the Manufacturer as
762 * "MICRO-STAR INTERNATIONAL CO.,LTD".
763 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
765 * BIOS versions earlier than 1.9 had a Board Product Name
766 * DMI field of "MS-7376". This was changed to be
767 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
768 * match on DMI_BOARD_NAME of "MS-7376".
771 .ident = "MSI K9A2 Platinum",
773 DMI_MATCH(DMI_BOARD_VENDOR,
775 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
779 * All BIOS versions for the Asus M3A support 64bit DMA.
780 * (all release versions from 0301 to 1206 were tested)
785 DMI_MATCH(DMI_BOARD_VENDOR,
786 "ASUSTeK Computer INC."),
787 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
792 const struct dmi_system_id *match;
793 int year, month, date;
796 match = dmi_first_match(sysids);
797 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
801 if (!match->driver_data)
804 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
805 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
807 if (strcmp(buf, match->driver_data) >= 0)
811 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
817 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
821 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
823 static const struct dmi_system_id broken_systems[] = {
825 .ident = "HP Compaq nx6310",
827 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
828 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
830 /* PCI slot number of the controller */
831 .driver_data = (void *)0x1FUL,
834 .ident = "HP Compaq 6720s",
836 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
837 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
839 /* PCI slot number of the controller */
840 .driver_data = (void *)0x1FUL,
843 { } /* terminate list */
845 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
848 unsigned long slot = (unsigned long)dmi->driver_data;
849 /* apply the quirk only to on-board controllers */
850 return slot == PCI_SLOT(pdev->devfn);
856 static bool ahci_broken_suspend(struct pci_dev *pdev)
858 static const struct dmi_system_id sysids[] = {
860 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
861 * to the harddisk doesn't become online after
862 * resuming from STR. Warn and fail suspend.
864 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
866 * Use dates instead of versions to match as HP is
867 * apparently recycling both product and version
870 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
875 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
876 DMI_MATCH(DMI_PRODUCT_NAME,
877 "HP Pavilion dv4 Notebook PC"),
879 .driver_data = "20090105", /* F.30 */
884 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
885 DMI_MATCH(DMI_PRODUCT_NAME,
886 "HP Pavilion dv5 Notebook PC"),
888 .driver_data = "20090506", /* F.16 */
893 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
894 DMI_MATCH(DMI_PRODUCT_NAME,
895 "HP Pavilion dv6 Notebook PC"),
897 .driver_data = "20090423", /* F.21 */
902 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
903 DMI_MATCH(DMI_PRODUCT_NAME,
904 "HP HDX18 Notebook PC"),
906 .driver_data = "20090430", /* F.23 */
909 * Acer eMachines G725 has the same problem. BIOS
910 * V1.03 is known to be broken. V3.04 is known to
911 * work. Between, there are V1.06, V2.06 and V3.03
912 * that we don't have much idea about. For now,
913 * blacklist anything older than V3.04.
915 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
920 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
921 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
923 .driver_data = "20091216", /* V3.04 */
925 { } /* terminate list */
927 const struct dmi_system_id *dmi = dmi_first_match(sysids);
928 int year, month, date;
931 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
934 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
935 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
937 return strcmp(buf, dmi->driver_data) < 0;
940 static bool ahci_broken_online(struct pci_dev *pdev)
942 #define ENCODE_BUSDEVFN(bus, slot, func) \
943 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
944 static const struct dmi_system_id sysids[] = {
946 * There are several gigabyte boards which use
947 * SIMG5723s configured as hardware RAID. Certain
948 * 5723 firmware revisions shipped there keep the link
949 * online but fail to answer properly to SRST or
950 * IDENTIFY when no device is attached downstream
951 * causing libata to retry quite a few times leading
952 * to excessive detection delay.
954 * As these firmwares respond to the second reset try
955 * with invalid device signature, considering unknown
956 * sig as offline works around the problem acceptably.
961 DMI_MATCH(DMI_BOARD_VENDOR,
962 "Gigabyte Technology Co., Ltd."),
963 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
965 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
970 DMI_MATCH(DMI_BOARD_VENDOR,
971 "Gigabyte Technology Co., Ltd."),
972 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
974 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
976 { } /* terminate list */
978 #undef ENCODE_BUSDEVFN
979 const struct dmi_system_id *dmi = dmi_first_match(sysids);
985 val = (unsigned long)dmi->driver_data;
987 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
990 #ifdef CONFIG_ATA_ACPI
991 static void ahci_gtf_filter_workaround(struct ata_host *host)
993 static const struct dmi_system_id sysids[] = {
995 * Aspire 3810T issues a bunch of SATA enable commands
996 * via _GTF including an invalid one and one which is
997 * rejected by the device. Among the successful ones
998 * is FPDMA non-zero offset enable which when enabled
999 * only on the drive side leads to NCQ command
1000 * failures. Filter it out.
1003 .ident = "Aspire 3810T",
1005 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1006 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1008 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1012 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1013 unsigned int filter;
1019 filter = (unsigned long)dmi->driver_data;
1020 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1021 filter, dmi->ident);
1023 for (i = 0; i < host->n_ports; i++) {
1024 struct ata_port *ap = host->ports[i];
1025 struct ata_link *link;
1026 struct ata_device *dev;
1028 ata_for_each_link(link, ap, EDGE)
1029 ata_for_each_dev(dev, link, ALL)
1030 dev->gtf_filter |= filter;
1034 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1038 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1040 unsigned int board_id = ent->driver_data;
1041 struct ata_port_info pi = ahci_port_info[board_id];
1042 const struct ata_port_info *ppi[] = { &pi, NULL };
1043 struct device *dev = &pdev->dev;
1044 struct ahci_host_priv *hpriv;
1045 struct ata_host *host;
1047 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1051 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1053 ata_print_version_once(&pdev->dev, DRV_VERSION);
1055 /* The AHCI driver can only drive the SATA ports, the PATA driver
1056 can drive them all so if both drivers are selected make sure
1057 AHCI stays out of the way */
1058 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1062 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1063 * ahci, use ata_generic instead.
1065 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1066 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1067 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1068 pdev->subsystem_device == 0xcb89)
1071 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1072 * At the moment, we can only use the AHCI mode. Let the users know
1073 * that for SAS drives they're out of luck.
1075 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1076 dev_info(&pdev->dev,
1077 "PDC42819 can only drive SATA devices with this driver\n");
1079 /* The Connext uses non-standard BAR */
1080 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1081 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1083 /* acquire resources */
1084 rc = pcim_enable_device(pdev);
1088 /* AHCI controllers often implement SFF compatible interface.
1089 * Grab all PCI BARs just in case.
1091 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1093 pcim_pin_device(pdev);
1097 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1098 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1101 /* ICH6s share the same PCI ID for both piix and ahci
1102 * modes. Enabling ahci mode while MAP indicates
1103 * combined mode is a bad idea. Yield to ata_piix.
1105 pci_read_config_byte(pdev, ICH_MAP, &map);
1107 dev_info(&pdev->dev,
1108 "controller is in combined mode, can't enable AHCI mode\n");
1113 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1116 hpriv->flags |= (unsigned long)pi.private_data;
1118 /* MCP65 revision A1 and A2 can't do MSI */
1119 if (board_id == board_ahci_mcp65 &&
1120 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1121 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1123 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1124 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1125 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1127 /* only some SB600s can do 64bit DMA */
1128 if (ahci_sb600_enable_64bit(pdev))
1129 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1131 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1134 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1136 /* save initial config */
1137 ahci_pci_save_initial_config(pdev, hpriv);
1140 if (hpriv->cap & HOST_CAP_NCQ) {
1141 pi.flags |= ATA_FLAG_NCQ;
1143 * Auto-activate optimization is supposed to be
1144 * supported on all AHCI controllers indicating NCQ
1145 * capability, but it seems to be broken on some
1146 * chipsets including NVIDIAs.
1148 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1149 pi.flags |= ATA_FLAG_FPDMA_AA;
1152 if (hpriv->cap & HOST_CAP_PMP)
1153 pi.flags |= ATA_FLAG_PMP;
1155 ahci_set_em_messages(hpriv, &pi);
1157 if (ahci_broken_system_poweroff(pdev)) {
1158 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1159 dev_info(&pdev->dev,
1160 "quirky BIOS, skipping spindown on poweroff\n");
1163 if (ahci_broken_suspend(pdev)) {
1164 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1165 dev_warn(&pdev->dev,
1166 "BIOS update required for suspend/resume\n");
1169 if (ahci_broken_online(pdev)) {
1170 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1171 dev_info(&pdev->dev,
1172 "online status unreliable, applying workaround\n");
1175 /* CAP.NP sometimes indicate the index of the last enabled
1176 * port, at other times, that of the last possible port, so
1177 * determining the maximum port number requires looking at
1178 * both CAP.NP and port_map.
1180 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1182 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1185 host->private_data = hpriv;
1187 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1188 host->flags |= ATA_HOST_PARALLEL_SCAN;
1190 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1192 if (pi.flags & ATA_FLAG_EM)
1193 ahci_reset_em(host);
1195 for (i = 0; i < host->n_ports; i++) {
1196 struct ata_port *ap = host->ports[i];
1198 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1199 ata_port_pbar_desc(ap, ahci_pci_bar,
1200 0x100 + ap->port_no * 0x80, "port");
1202 /* set enclosure management message type */
1203 if (ap->flags & ATA_FLAG_EM)
1204 ap->em_message_type = hpriv->em_msg_type;
1207 /* disabled/not-implemented port */
1208 if (!(hpriv->port_map & (1 << i)))
1209 ap->ops = &ata_dummy_port_ops;
1212 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1213 ahci_p5wdh_workaround(host);
1215 /* apply gtf filter quirk */
1216 ahci_gtf_filter_workaround(host);
1218 /* initialize adapter */
1219 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1223 rc = ahci_pci_reset_controller(host);
1227 ahci_pci_init_controller(host);
1228 ahci_pci_print_info(host);
1230 pci_set_master(pdev);
1231 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1235 static int __init ahci_init(void)
1237 return pci_register_driver(&ahci_pci_driver);
1240 static void __exit ahci_exit(void)
1242 pci_unregister_driver(&ahci_pci_driver);
1246 MODULE_AUTHOR("Jeff Garzik");
1247 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1248 MODULE_LICENSE("GPL");
1249 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1250 MODULE_VERSION(DRV_VERSION);
1252 module_init(ahci_init);
1253 module_exit(ahci_exit);