2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] =
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nosntf] =
128 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_yes_fbs] =
136 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
180 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
181 AHCI_HFLAG_32BIT_ONLY),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_pmp_retry_srst_ops,
187 [board_ahci_sb700] = /* for SB700 and SB800 */
189 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_vt8251] =
197 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_vt8251_ops,
205 static const struct pci_device_id ahci_pci_tbl[] = {
207 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
208 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
209 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
210 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
211 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
212 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
213 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
216 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
217 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
220 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
222 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
236 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
239 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
249 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
254 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
257 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
260 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
274 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
275 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
282 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
283 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
298 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
302 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
306 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
307 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
309 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
311 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
312 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
313 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
316 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
317 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
325 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
326 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
327 /* AMD is using RAID class only for ahci controllers */
328 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
329 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
332 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
333 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
336 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426 /* ST Microelectronics */
427 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
430 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
431 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
432 { PCI_DEVICE(0x1b4b, 0x9123),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
436 { PCI_DEVICE(0x1b4b, 0x9125),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
438 { PCI_DEVICE(0x1b4b, 0x917a),
439 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
440 { PCI_DEVICE(0x1b4b, 0x9192),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
442 { PCI_DEVICE(0x1b4b, 0x91a3),
443 .driver_data = board_ahci_yes_fbs },
446 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
449 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
450 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
451 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
452 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
455 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
457 /* Generic, PCI class code for AHCI */
458 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
459 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
461 { } /* terminate list */
465 static struct pci_driver ahci_pci_driver = {
467 .id_table = ahci_pci_tbl,
468 .probe = ahci_init_one,
469 .remove = ata_pci_remove_one,
471 .suspend = ahci_pci_device_suspend,
472 .resume = ahci_pci_device_resume,
476 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
477 static int marvell_enable;
479 static int marvell_enable = 1;
481 module_param(marvell_enable, int, 0644);
482 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
485 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
486 struct ahci_host_priv *hpriv)
488 unsigned int force_port_map = 0;
489 unsigned int mask_port_map = 0;
491 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
492 dev_info(&pdev->dev, "JMB361 has only one port\n");
497 * Temporary Marvell 6145 hack: PATA port presence
498 * is asserted through the standard AHCI port
499 * presence register, as bit 4 (counting from 0)
501 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
502 if (pdev->device == 0x6121)
507 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
510 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
514 static int ahci_pci_reset_controller(struct ata_host *host)
516 struct pci_dev *pdev = to_pci_dev(host->dev);
518 ahci_reset_controller(host);
520 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
521 struct ahci_host_priv *hpriv = host->private_data;
525 pci_read_config_word(pdev, 0x92, &tmp16);
526 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
527 tmp16 |= hpriv->port_map;
528 pci_write_config_word(pdev, 0x92, tmp16);
535 static void ahci_pci_init_controller(struct ata_host *host)
537 struct ahci_host_priv *hpriv = host->private_data;
538 struct pci_dev *pdev = to_pci_dev(host->dev);
539 void __iomem *port_mmio;
543 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
544 if (pdev->device == 0x6121)
548 port_mmio = __ahci_port_base(host, mv);
550 writel(0, port_mmio + PORT_IRQ_MASK);
553 tmp = readl(port_mmio + PORT_IRQ_STAT);
554 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
556 writel(tmp, port_mmio + PORT_IRQ_STAT);
559 ahci_init_controller(host);
562 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
563 unsigned long deadline)
565 struct ata_port *ap = link->ap;
571 ahci_stop_engine(ap);
573 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
574 deadline, &online, NULL);
576 ahci_start_engine(ap);
578 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
580 /* vt8251 doesn't clear BSY on signature FIS reception,
581 * request follow-up softreset.
583 return online ? -EAGAIN : rc;
586 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
587 unsigned long deadline)
589 struct ata_port *ap = link->ap;
590 struct ahci_port_priv *pp = ap->private_data;
591 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
592 struct ata_taskfile tf;
596 ahci_stop_engine(ap);
598 /* clear D2H reception area to properly wait for D2H FIS */
599 ata_tf_init(link->device, &tf);
601 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
603 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
604 deadline, &online, NULL);
606 ahci_start_engine(ap);
608 /* The pseudo configuration device on SIMG4726 attached to
609 * ASUS P5W-DH Deluxe doesn't send signature FIS after
610 * hardreset if no device is attached to the first downstream
611 * port && the pseudo device locks up on SRST w/ PMP==0. To
612 * work around this, wait for !BSY only briefly. If BSY isn't
613 * cleared, perform CLO and proceed to IDENTIFY (achieved by
614 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
616 * Wait for two seconds. Devices attached to downstream port
617 * which can't process the following IDENTIFY after this will
618 * have to be reset again. For most cases, this should
619 * suffice while making probing snappish enough.
622 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
625 ahci_kick_engine(ap);
631 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
633 struct ata_host *host = dev_get_drvdata(&pdev->dev);
634 struct ahci_host_priv *hpriv = host->private_data;
635 void __iomem *mmio = hpriv->mmio;
638 if (mesg.event & PM_EVENT_SUSPEND &&
639 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
641 "BIOS update required for suspend/resume\n");
645 if (mesg.event & PM_EVENT_SLEEP) {
646 /* AHCI spec rev1.1 section 8.3.3:
647 * Software must disable interrupts prior to requesting a
648 * transition of the HBA to D3 state.
650 ctl = readl(mmio + HOST_CTL);
652 writel(ctl, mmio + HOST_CTL);
653 readl(mmio + HOST_CTL); /* flush */
656 return ata_pci_device_suspend(pdev, mesg);
659 static int ahci_pci_device_resume(struct pci_dev *pdev)
661 struct ata_host *host = dev_get_drvdata(&pdev->dev);
664 rc = ata_pci_device_do_resume(pdev);
668 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
669 rc = ahci_pci_reset_controller(host);
673 ahci_pci_init_controller(host);
676 ata_host_resume(host);
682 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
687 * If the device fixup already set the dma_mask to some non-standard
688 * value, don't extend it here. This happens on STA2X11, for example.
690 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
694 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
695 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
697 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
700 "64-bit DMA enable failed\n");
705 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
707 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
710 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
713 "32-bit consistent DMA enable failed\n");
720 static void ahci_pci_print_info(struct ata_host *host)
722 struct pci_dev *pdev = to_pci_dev(host->dev);
726 pci_read_config_word(pdev, 0x0a, &cc);
727 if (cc == PCI_CLASS_STORAGE_IDE)
729 else if (cc == PCI_CLASS_STORAGE_SATA)
731 else if (cc == PCI_CLASS_STORAGE_RAID)
736 ahci_print_info(host, scc_s);
739 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
740 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
741 * support PMP and the 4726 either directly exports the device
742 * attached to the first downstream port or acts as a hardware storage
743 * controller and emulate a single ATA device (can be RAID 0/1 or some
744 * other configuration).
746 * When there's no device attached to the first downstream port of the
747 * 4726, "Config Disk" appears, which is a pseudo ATA device to
748 * configure the 4726. However, ATA emulation of the device is very
749 * lame. It doesn't send signature D2H Reg FIS after the initial
750 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
752 * The following function works around the problem by always using
753 * hardreset on the port and not depending on receiving signature FIS
754 * afterward. If signature FIS isn't received soon, ATA class is
755 * assumed without follow-up softreset.
757 static void ahci_p5wdh_workaround(struct ata_host *host)
759 static struct dmi_system_id sysids[] = {
761 .ident = "P5W DH Deluxe",
763 DMI_MATCH(DMI_SYS_VENDOR,
764 "ASUSTEK COMPUTER INC"),
765 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
770 struct pci_dev *pdev = to_pci_dev(host->dev);
772 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
773 dmi_check_system(sysids)) {
774 struct ata_port *ap = host->ports[1];
777 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
779 ap->ops = &ahci_p5wdh_ops;
780 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
784 /* only some SB600 ahci controllers can do 64bit DMA */
785 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
787 static const struct dmi_system_id sysids[] = {
789 * The oldest version known to be broken is 0901 and
790 * working is 1501 which was released on 2007-10-26.
791 * Enable 64bit DMA on 1501 and anything newer.
793 * Please read bko#9412 for more info.
796 .ident = "ASUS M2A-VM",
798 DMI_MATCH(DMI_BOARD_VENDOR,
799 "ASUSTeK Computer INC."),
800 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
802 .driver_data = "20071026", /* yyyymmdd */
805 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
808 * BIOS versions earlier than 1.5 had the Manufacturer DMI
809 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
810 * This spelling mistake was fixed in BIOS version 1.5, so
811 * 1.5 and later have the Manufacturer as
812 * "MICRO-STAR INTERNATIONAL CO.,LTD".
813 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
815 * BIOS versions earlier than 1.9 had a Board Product Name
816 * DMI field of "MS-7376". This was changed to be
817 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
818 * match on DMI_BOARD_NAME of "MS-7376".
821 .ident = "MSI K9A2 Platinum",
823 DMI_MATCH(DMI_BOARD_VENDOR,
825 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
829 * All BIOS versions for the Asus M3A support 64bit DMA.
830 * (all release versions from 0301 to 1206 were tested)
835 DMI_MATCH(DMI_BOARD_VENDOR,
836 "ASUSTeK Computer INC."),
837 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
842 const struct dmi_system_id *match;
843 int year, month, date;
846 match = dmi_first_match(sysids);
847 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
851 if (!match->driver_data)
854 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
855 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
857 if (strcmp(buf, match->driver_data) >= 0)
861 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
867 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
871 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
873 static const struct dmi_system_id broken_systems[] = {
875 .ident = "HP Compaq nx6310",
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
880 /* PCI slot number of the controller */
881 .driver_data = (void *)0x1FUL,
884 .ident = "HP Compaq 6720s",
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
889 /* PCI slot number of the controller */
890 .driver_data = (void *)0x1FUL,
893 { } /* terminate list */
895 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
898 unsigned long slot = (unsigned long)dmi->driver_data;
899 /* apply the quirk only to on-board controllers */
900 return slot == PCI_SLOT(pdev->devfn);
906 static bool ahci_broken_suspend(struct pci_dev *pdev)
908 static const struct dmi_system_id sysids[] = {
910 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
911 * to the harddisk doesn't become online after
912 * resuming from STR. Warn and fail suspend.
914 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
916 * Use dates instead of versions to match as HP is
917 * apparently recycling both product and version
920 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
925 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
926 DMI_MATCH(DMI_PRODUCT_NAME,
927 "HP Pavilion dv4 Notebook PC"),
929 .driver_data = "20090105", /* F.30 */
934 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
935 DMI_MATCH(DMI_PRODUCT_NAME,
936 "HP Pavilion dv5 Notebook PC"),
938 .driver_data = "20090506", /* F.16 */
943 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
944 DMI_MATCH(DMI_PRODUCT_NAME,
945 "HP Pavilion dv6 Notebook PC"),
947 .driver_data = "20090423", /* F.21 */
952 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
953 DMI_MATCH(DMI_PRODUCT_NAME,
954 "HP HDX18 Notebook PC"),
956 .driver_data = "20090430", /* F.23 */
959 * Acer eMachines G725 has the same problem. BIOS
960 * V1.03 is known to be broken. V3.04 is known to
961 * work. Between, there are V1.06, V2.06 and V3.03
962 * that we don't have much idea about. For now,
963 * blacklist anything older than V3.04.
965 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
970 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
971 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
973 .driver_data = "20091216", /* V3.04 */
975 { } /* terminate list */
977 const struct dmi_system_id *dmi = dmi_first_match(sysids);
978 int year, month, date;
981 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
984 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
985 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
987 return strcmp(buf, dmi->driver_data) < 0;
990 static bool ahci_broken_online(struct pci_dev *pdev)
992 #define ENCODE_BUSDEVFN(bus, slot, func) \
993 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
994 static const struct dmi_system_id sysids[] = {
996 * There are several gigabyte boards which use
997 * SIMG5723s configured as hardware RAID. Certain
998 * 5723 firmware revisions shipped there keep the link
999 * online but fail to answer properly to SRST or
1000 * IDENTIFY when no device is attached downstream
1001 * causing libata to retry quite a few times leading
1002 * to excessive detection delay.
1004 * As these firmwares respond to the second reset try
1005 * with invalid device signature, considering unknown
1006 * sig as offline works around the problem acceptably.
1009 .ident = "EP45-DQ6",
1011 DMI_MATCH(DMI_BOARD_VENDOR,
1012 "Gigabyte Technology Co., Ltd."),
1013 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1015 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1018 .ident = "EP45-DS5",
1020 DMI_MATCH(DMI_BOARD_VENDOR,
1021 "Gigabyte Technology Co., Ltd."),
1022 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1024 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1026 { } /* terminate list */
1028 #undef ENCODE_BUSDEVFN
1029 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1035 val = (unsigned long)dmi->driver_data;
1037 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1040 #ifdef CONFIG_ATA_ACPI
1041 static void ahci_gtf_filter_workaround(struct ata_host *host)
1043 static const struct dmi_system_id sysids[] = {
1045 * Aspire 3810T issues a bunch of SATA enable commands
1046 * via _GTF including an invalid one and one which is
1047 * rejected by the device. Among the successful ones
1048 * is FPDMA non-zero offset enable which when enabled
1049 * only on the drive side leads to NCQ command
1050 * failures. Filter it out.
1053 .ident = "Aspire 3810T",
1055 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1058 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1062 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1063 unsigned int filter;
1069 filter = (unsigned long)dmi->driver_data;
1070 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1071 filter, dmi->ident);
1073 for (i = 0; i < host->n_ports; i++) {
1074 struct ata_port *ap = host->ports[i];
1075 struct ata_link *link;
1076 struct ata_device *dev;
1078 ata_for_each_link(link, ap, EDGE)
1079 ata_for_each_dev(dev, link, ALL)
1080 dev->gtf_filter |= filter;
1084 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1088 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1090 unsigned int board_id = ent->driver_data;
1091 struct ata_port_info pi = ahci_port_info[board_id];
1092 const struct ata_port_info *ppi[] = { &pi, NULL };
1093 struct device *dev = &pdev->dev;
1094 struct ahci_host_priv *hpriv;
1095 struct ata_host *host;
1097 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1101 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1103 ata_print_version_once(&pdev->dev, DRV_VERSION);
1105 /* The AHCI driver can only drive the SATA ports, the PATA driver
1106 can drive them all so if both drivers are selected make sure
1107 AHCI stays out of the way */
1108 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1112 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1113 * ahci, use ata_generic instead.
1115 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1116 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1117 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1118 pdev->subsystem_device == 0xcb89)
1121 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1122 * At the moment, we can only use the AHCI mode. Let the users know
1123 * that for SAS drives they're out of luck.
1125 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1126 dev_info(&pdev->dev,
1127 "PDC42819 can only drive SATA devices with this driver\n");
1129 /* Both Connext and Enmotus devices use non-standard BARs */
1130 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1131 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1132 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1133 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1135 /* acquire resources */
1136 rc = pcim_enable_device(pdev);
1140 /* AHCI controllers often implement SFF compatible interface.
1141 * Grab all PCI BARs just in case.
1143 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1145 pcim_pin_device(pdev);
1149 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1150 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1153 /* ICH6s share the same PCI ID for both piix and ahci
1154 * modes. Enabling ahci mode while MAP indicates
1155 * combined mode is a bad idea. Yield to ata_piix.
1157 pci_read_config_byte(pdev, ICH_MAP, &map);
1159 dev_info(&pdev->dev,
1160 "controller is in combined mode, can't enable AHCI mode\n");
1165 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1168 hpriv->flags |= (unsigned long)pi.private_data;
1170 /* MCP65 revision A1 and A2 can't do MSI */
1171 if (board_id == board_ahci_mcp65 &&
1172 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1173 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1175 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1176 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1177 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1179 /* only some SB600s can do 64bit DMA */
1180 if (ahci_sb600_enable_64bit(pdev))
1181 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1183 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1186 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1188 /* save initial config */
1189 ahci_pci_save_initial_config(pdev, hpriv);
1192 if (hpriv->cap & HOST_CAP_NCQ) {
1193 pi.flags |= ATA_FLAG_NCQ;
1195 * Auto-activate optimization is supposed to be
1196 * supported on all AHCI controllers indicating NCQ
1197 * capability, but it seems to be broken on some
1198 * chipsets including NVIDIAs.
1200 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1201 pi.flags |= ATA_FLAG_FPDMA_AA;
1204 if (hpriv->cap & HOST_CAP_PMP)
1205 pi.flags |= ATA_FLAG_PMP;
1207 ahci_set_em_messages(hpriv, &pi);
1209 if (ahci_broken_system_poweroff(pdev)) {
1210 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1211 dev_info(&pdev->dev,
1212 "quirky BIOS, skipping spindown on poweroff\n");
1215 if (ahci_broken_suspend(pdev)) {
1216 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1217 dev_warn(&pdev->dev,
1218 "BIOS update required for suspend/resume\n");
1221 if (ahci_broken_online(pdev)) {
1222 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1223 dev_info(&pdev->dev,
1224 "online status unreliable, applying workaround\n");
1227 /* CAP.NP sometimes indicate the index of the last enabled
1228 * port, at other times, that of the last possible port, so
1229 * determining the maximum port number requires looking at
1230 * both CAP.NP and port_map.
1232 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1234 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1237 host->private_data = hpriv;
1239 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1240 host->flags |= ATA_HOST_PARALLEL_SCAN;
1242 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1244 if (pi.flags & ATA_FLAG_EM)
1245 ahci_reset_em(host);
1247 for (i = 0; i < host->n_ports; i++) {
1248 struct ata_port *ap = host->ports[i];
1250 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1251 ata_port_pbar_desc(ap, ahci_pci_bar,
1252 0x100 + ap->port_no * 0x80, "port");
1254 /* set enclosure management message type */
1255 if (ap->flags & ATA_FLAG_EM)
1256 ap->em_message_type = hpriv->em_msg_type;
1259 /* disabled/not-implemented port */
1260 if (!(hpriv->port_map & (1 << i)))
1261 ap->ops = &ata_dummy_port_ops;
1264 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1265 ahci_p5wdh_workaround(host);
1267 /* apply gtf filter quirk */
1268 ahci_gtf_filter_workaround(host);
1270 /* initialize adapter */
1271 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1275 rc = ahci_pci_reset_controller(host);
1279 ahci_pci_init_controller(host);
1280 ahci_pci_print_info(host);
1282 pci_set_master(pdev);
1283 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1287 static int __init ahci_init(void)
1289 return pci_register_driver(&ahci_pci_driver);
1292 static void __exit ahci_exit(void)
1294 pci_unregister_driver(&ahci_pci_driver);
1298 MODULE_AUTHOR("Jeff Garzik");
1299 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1300 MODULE_LICENSE("GPL");
1301 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1302 MODULE_VERSION(DRV_VERSION);
1304 module_init(ahci_init);
1305 module_exit(ahci_exit);