2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
76 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
86 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
95 static int ahci_pci_device_resume(struct pci_dev *pdev);
98 static struct scsi_host_template ahci_sht = {
102 static struct ata_port_operations ahci_vt8251_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_vt8251_hardreset,
107 static struct ata_port_operations ahci_p5wdh_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_p5wdh_hardreset,
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] =
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_nomsi] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_noncq] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_nosntf] =
152 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_yes_fbs] =
160 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_avn_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = /* for SB700 and SB800 */
219 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
225 [board_ahci_vt8251] =
227 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_vt8251_ops,
235 static const struct pci_device_id ahci_pci_tbl[] = {
237 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
238 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
239 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
240 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
241 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
242 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
243 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
245 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
247 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
249 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
251 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
252 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
265 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
266 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
268 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
298 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
299 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
302 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
303 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
304 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
306 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
307 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
309 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
310 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
314 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
316 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
321 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
322 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
323 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
324 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
331 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
332 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
333 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
340 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
341 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
346 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
350 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
354 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
356 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
358 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
363 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
364 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
368 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
369 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
370 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
371 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
372 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
373 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
374 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
375 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
378 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
381 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
390 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
391 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
393 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
394 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
399 /* JMicron 362B and 362C have an AHCI function with IDE class code */
400 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
401 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
404 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
405 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
410 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
413 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
414 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
415 /* AMD is using RAID class only for ahci controllers */
416 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
420 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
421 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
424 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
511 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
512 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
514 /* ST Microelectronics */
515 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
518 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
519 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
521 .class = PCI_CLASS_STORAGE_SATA_AHCI,
522 .class_mask = 0xffffff,
523 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
526 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
527 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
546 .driver_data = board_ahci_yes_fbs },
549 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
550 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
553 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
554 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
555 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
556 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
559 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
560 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
562 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
563 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
566 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
568 /* Generic, PCI class code for AHCI */
569 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
570 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
572 { } /* terminate list */
576 static struct pci_driver ahci_pci_driver = {
578 .id_table = ahci_pci_tbl,
579 .probe = ahci_init_one,
580 .remove = ata_pci_remove_one,
582 .suspend = ahci_pci_device_suspend,
583 .resume = ahci_pci_device_resume,
587 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
588 static int marvell_enable;
590 static int marvell_enable = 1;
592 module_param(marvell_enable, int, 0644);
593 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
596 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
597 struct ahci_host_priv *hpriv)
599 unsigned int force_port_map = 0;
600 unsigned int mask_port_map = 0;
602 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
603 dev_info(&pdev->dev, "JMB361 has only one port\n");
608 * Temporary Marvell 6145 hack: PATA port presence
609 * is asserted through the standard AHCI port
610 * presence register, as bit 4 (counting from 0)
612 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
613 if (pdev->device == 0x6121)
618 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
621 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
625 static int ahci_pci_reset_controller(struct ata_host *host)
627 struct pci_dev *pdev = to_pci_dev(host->dev);
629 ahci_reset_controller(host);
631 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
632 struct ahci_host_priv *hpriv = host->private_data;
636 pci_read_config_word(pdev, 0x92, &tmp16);
637 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
638 tmp16 |= hpriv->port_map;
639 pci_write_config_word(pdev, 0x92, tmp16);
646 static void ahci_pci_init_controller(struct ata_host *host)
648 struct ahci_host_priv *hpriv = host->private_data;
649 struct pci_dev *pdev = to_pci_dev(host->dev);
650 void __iomem *port_mmio;
654 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
655 if (pdev->device == 0x6121)
659 port_mmio = __ahci_port_base(host, mv);
661 writel(0, port_mmio + PORT_IRQ_MASK);
664 tmp = readl(port_mmio + PORT_IRQ_STAT);
665 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
667 writel(tmp, port_mmio + PORT_IRQ_STAT);
670 ahci_init_controller(host);
673 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
674 unsigned long deadline)
676 struct ata_port *ap = link->ap;
682 ahci_stop_engine(ap);
684 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
685 deadline, &online, NULL);
687 ahci_start_engine(ap);
689 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
691 /* vt8251 doesn't clear BSY on signature FIS reception,
692 * request follow-up softreset.
694 return online ? -EAGAIN : rc;
697 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
700 struct ata_port *ap = link->ap;
701 struct ahci_port_priv *pp = ap->private_data;
702 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
703 struct ata_taskfile tf;
707 ahci_stop_engine(ap);
709 /* clear D2H reception area to properly wait for D2H FIS */
710 ata_tf_init(link->device, &tf);
712 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
714 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
715 deadline, &online, NULL);
717 ahci_start_engine(ap);
719 /* The pseudo configuration device on SIMG4726 attached to
720 * ASUS P5W-DH Deluxe doesn't send signature FIS after
721 * hardreset if no device is attached to the first downstream
722 * port && the pseudo device locks up on SRST w/ PMP==0. To
723 * work around this, wait for !BSY only briefly. If BSY isn't
724 * cleared, perform CLO and proceed to IDENTIFY (achieved by
725 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
727 * Wait for two seconds. Devices attached to downstream port
728 * which can't process the following IDENTIFY after this will
729 * have to be reset again. For most cases, this should
730 * suffice while making probing snappish enough.
733 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
736 ahci_kick_engine(ap);
742 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
744 * It has been observed with some SSDs that the timing of events in the
745 * link synchronization phase can leave the port in a state that can not
746 * be recovered by a SATA-hard-reset alone. The failing signature is
747 * SStatus.DET stuck at 1 ("Device presence detected but Phy
748 * communication not established"). It was found that unloading and
749 * reloading the driver when this problem occurs allows the drive
750 * connection to be recovered (DET advanced to 0x3). The critical
751 * component of reloading the driver is that the port state machines are
752 * reset by bouncing "port enable" in the AHCI PCS configuration
753 * register. So, reproduce that effect by bouncing a port whenever we
754 * see DET==1 after a reset.
756 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
757 unsigned long deadline)
759 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
760 struct ata_port *ap = link->ap;
761 struct ahci_port_priv *pp = ap->private_data;
762 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
763 unsigned long tmo = deadline - jiffies;
764 struct ata_taskfile tf;
770 ahci_stop_engine(ap);
772 for (i = 0; i < 2; i++) {
775 int port = ap->port_no;
776 struct ata_host *host = ap->host;
777 struct pci_dev *pdev = to_pci_dev(host->dev);
779 /* clear D2H reception area to properly wait for D2H FIS */
780 ata_tf_init(link->device, &tf);
781 tf.command = ATA_BUSY;
782 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
784 rc = sata_link_hardreset(link, timing, deadline, &online,
787 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
788 (sstatus & 0xf) != 1)
791 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
794 pci_read_config_word(pdev, 0x92, &val);
796 pci_write_config_word(pdev, 0x92, val);
797 ata_msleep(ap, 1000);
799 pci_write_config_word(pdev, 0x92, val);
803 ahci_start_engine(ap);
806 *class = ahci_dev_classify(ap);
808 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
814 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
816 struct ata_host *host = dev_get_drvdata(&pdev->dev);
817 struct ahci_host_priv *hpriv = host->private_data;
818 void __iomem *mmio = hpriv->mmio;
821 if (mesg.event & PM_EVENT_SUSPEND &&
822 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
824 "BIOS update required for suspend/resume\n");
828 if (mesg.event & PM_EVENT_SLEEP) {
829 /* AHCI spec rev1.1 section 8.3.3:
830 * Software must disable interrupts prior to requesting a
831 * transition of the HBA to D3 state.
833 ctl = readl(mmio + HOST_CTL);
835 writel(ctl, mmio + HOST_CTL);
836 readl(mmio + HOST_CTL); /* flush */
839 return ata_pci_device_suspend(pdev, mesg);
842 static int ahci_pci_device_resume(struct pci_dev *pdev)
844 struct ata_host *host = dev_get_drvdata(&pdev->dev);
847 rc = ata_pci_device_do_resume(pdev);
851 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
852 rc = ahci_pci_reset_controller(host);
856 ahci_pci_init_controller(host);
859 ata_host_resume(host);
865 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
870 * If the device fixup already set the dma_mask to some non-standard
871 * value, don't extend it here. This happens on STA2X11, for example.
873 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
877 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
878 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
880 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
883 "64-bit DMA enable failed\n");
888 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
890 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
893 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
896 "32-bit consistent DMA enable failed\n");
903 static void ahci_pci_print_info(struct ata_host *host)
905 struct pci_dev *pdev = to_pci_dev(host->dev);
909 pci_read_config_word(pdev, 0x0a, &cc);
910 if (cc == PCI_CLASS_STORAGE_IDE)
912 else if (cc == PCI_CLASS_STORAGE_SATA)
914 else if (cc == PCI_CLASS_STORAGE_RAID)
919 ahci_print_info(host, scc_s);
922 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
923 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
924 * support PMP and the 4726 either directly exports the device
925 * attached to the first downstream port or acts as a hardware storage
926 * controller and emulate a single ATA device (can be RAID 0/1 or some
927 * other configuration).
929 * When there's no device attached to the first downstream port of the
930 * 4726, "Config Disk" appears, which is a pseudo ATA device to
931 * configure the 4726. However, ATA emulation of the device is very
932 * lame. It doesn't send signature D2H Reg FIS after the initial
933 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
935 * The following function works around the problem by always using
936 * hardreset on the port and not depending on receiving signature FIS
937 * afterward. If signature FIS isn't received soon, ATA class is
938 * assumed without follow-up softreset.
940 static void ahci_p5wdh_workaround(struct ata_host *host)
942 static struct dmi_system_id sysids[] = {
944 .ident = "P5W DH Deluxe",
946 DMI_MATCH(DMI_SYS_VENDOR,
947 "ASUSTEK COMPUTER INC"),
948 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
953 struct pci_dev *pdev = to_pci_dev(host->dev);
955 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
956 dmi_check_system(sysids)) {
957 struct ata_port *ap = host->ports[1];
960 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
962 ap->ops = &ahci_p5wdh_ops;
963 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
967 /* only some SB600 ahci controllers can do 64bit DMA */
968 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
970 static const struct dmi_system_id sysids[] = {
972 * The oldest version known to be broken is 0901 and
973 * working is 1501 which was released on 2007-10-26.
974 * Enable 64bit DMA on 1501 and anything newer.
976 * Please read bko#9412 for more info.
979 .ident = "ASUS M2A-VM",
981 DMI_MATCH(DMI_BOARD_VENDOR,
982 "ASUSTeK Computer INC."),
983 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
985 .driver_data = "20071026", /* yyyymmdd */
988 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
991 * BIOS versions earlier than 1.5 had the Manufacturer DMI
992 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
993 * This spelling mistake was fixed in BIOS version 1.5, so
994 * 1.5 and later have the Manufacturer as
995 * "MICRO-STAR INTERNATIONAL CO.,LTD".
996 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
998 * BIOS versions earlier than 1.9 had a Board Product Name
999 * DMI field of "MS-7376". This was changed to be
1000 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1001 * match on DMI_BOARD_NAME of "MS-7376".
1004 .ident = "MSI K9A2 Platinum",
1006 DMI_MATCH(DMI_BOARD_VENDOR,
1007 "MICRO-STAR INTER"),
1008 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1012 * All BIOS versions for the Asus M3A support 64bit DMA.
1013 * (all release versions from 0301 to 1206 were tested)
1016 .ident = "ASUS M3A",
1018 DMI_MATCH(DMI_BOARD_VENDOR,
1019 "ASUSTeK Computer INC."),
1020 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1025 const struct dmi_system_id *match;
1026 int year, month, date;
1029 match = dmi_first_match(sysids);
1030 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1034 if (!match->driver_data)
1037 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1038 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1040 if (strcmp(buf, match->driver_data) >= 0)
1043 dev_warn(&pdev->dev,
1044 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1050 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1054 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1056 static const struct dmi_system_id broken_systems[] = {
1058 .ident = "HP Compaq nx6310",
1060 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1061 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1063 /* PCI slot number of the controller */
1064 .driver_data = (void *)0x1FUL,
1067 .ident = "HP Compaq 6720s",
1069 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1072 /* PCI slot number of the controller */
1073 .driver_data = (void *)0x1FUL,
1076 { } /* terminate list */
1078 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1081 unsigned long slot = (unsigned long)dmi->driver_data;
1082 /* apply the quirk only to on-board controllers */
1083 return slot == PCI_SLOT(pdev->devfn);
1089 static bool ahci_broken_suspend(struct pci_dev *pdev)
1091 static const struct dmi_system_id sysids[] = {
1093 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1094 * to the harddisk doesn't become online after
1095 * resuming from STR. Warn and fail suspend.
1097 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1099 * Use dates instead of versions to match as HP is
1100 * apparently recycling both product and version
1103 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1108 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1109 DMI_MATCH(DMI_PRODUCT_NAME,
1110 "HP Pavilion dv4 Notebook PC"),
1112 .driver_data = "20090105", /* F.30 */
1117 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1118 DMI_MATCH(DMI_PRODUCT_NAME,
1119 "HP Pavilion dv5 Notebook PC"),
1121 .driver_data = "20090506", /* F.16 */
1126 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1127 DMI_MATCH(DMI_PRODUCT_NAME,
1128 "HP Pavilion dv6 Notebook PC"),
1130 .driver_data = "20090423", /* F.21 */
1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1136 DMI_MATCH(DMI_PRODUCT_NAME,
1137 "HP HDX18 Notebook PC"),
1139 .driver_data = "20090430", /* F.23 */
1142 * Acer eMachines G725 has the same problem. BIOS
1143 * V1.03 is known to be broken. V3.04 is known to
1144 * work. Between, there are V1.06, V2.06 and V3.03
1145 * that we don't have much idea about. For now,
1146 * blacklist anything older than V3.04.
1148 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1153 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1154 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1156 .driver_data = "20091216", /* V3.04 */
1158 { } /* terminate list */
1160 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1161 int year, month, date;
1164 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1167 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1168 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1170 return strcmp(buf, dmi->driver_data) < 0;
1173 static bool ahci_broken_online(struct pci_dev *pdev)
1175 #define ENCODE_BUSDEVFN(bus, slot, func) \
1176 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1177 static const struct dmi_system_id sysids[] = {
1179 * There are several gigabyte boards which use
1180 * SIMG5723s configured as hardware RAID. Certain
1181 * 5723 firmware revisions shipped there keep the link
1182 * online but fail to answer properly to SRST or
1183 * IDENTIFY when no device is attached downstream
1184 * causing libata to retry quite a few times leading
1185 * to excessive detection delay.
1187 * As these firmwares respond to the second reset try
1188 * with invalid device signature, considering unknown
1189 * sig as offline works around the problem acceptably.
1192 .ident = "EP45-DQ6",
1194 DMI_MATCH(DMI_BOARD_VENDOR,
1195 "Gigabyte Technology Co., Ltd."),
1196 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1198 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1201 .ident = "EP45-DS5",
1203 DMI_MATCH(DMI_BOARD_VENDOR,
1204 "Gigabyte Technology Co., Ltd."),
1205 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1207 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1209 { } /* terminate list */
1211 #undef ENCODE_BUSDEVFN
1212 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1218 val = (unsigned long)dmi->driver_data;
1220 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1223 #ifdef CONFIG_ATA_ACPI
1224 static void ahci_gtf_filter_workaround(struct ata_host *host)
1226 static const struct dmi_system_id sysids[] = {
1228 * Aspire 3810T issues a bunch of SATA enable commands
1229 * via _GTF including an invalid one and one which is
1230 * rejected by the device. Among the successful ones
1231 * is FPDMA non-zero offset enable which when enabled
1232 * only on the drive side leads to NCQ command
1233 * failures. Filter it out.
1236 .ident = "Aspire 3810T",
1238 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1239 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1241 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1245 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1246 unsigned int filter;
1252 filter = (unsigned long)dmi->driver_data;
1253 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1254 filter, dmi->ident);
1256 for (i = 0; i < host->n_ports; i++) {
1257 struct ata_port *ap = host->ports[i];
1258 struct ata_link *link;
1259 struct ata_device *dev;
1261 ata_for_each_link(link, ap, EDGE)
1262 ata_for_each_dev(dev, link, ALL)
1263 dev->gtf_filter |= filter;
1267 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1271 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1273 unsigned int board_id = ent->driver_data;
1274 struct ata_port_info pi = ahci_port_info[board_id];
1275 const struct ata_port_info *ppi[] = { &pi, NULL };
1276 struct device *dev = &pdev->dev;
1277 struct ahci_host_priv *hpriv;
1278 struct ata_host *host;
1280 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1284 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1286 ata_print_version_once(&pdev->dev, DRV_VERSION);
1288 /* The AHCI driver can only drive the SATA ports, the PATA driver
1289 can drive them all so if both drivers are selected make sure
1290 AHCI stays out of the way */
1291 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1295 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1296 * ahci, use ata_generic instead.
1298 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1299 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1300 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1301 pdev->subsystem_device == 0xcb89)
1304 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1305 * At the moment, we can only use the AHCI mode. Let the users know
1306 * that for SAS drives they're out of luck.
1308 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1309 dev_info(&pdev->dev,
1310 "PDC42819 can only drive SATA devices with this driver\n");
1312 /* Both Connext and Enmotus devices use non-standard BARs */
1313 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1314 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1315 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1316 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1318 /* acquire resources */
1319 rc = pcim_enable_device(pdev);
1323 /* AHCI controllers often implement SFF compatible interface.
1324 * Grab all PCI BARs just in case.
1326 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1328 pcim_pin_device(pdev);
1332 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1333 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1336 /* ICH6s share the same PCI ID for both piix and ahci
1337 * modes. Enabling ahci mode while MAP indicates
1338 * combined mode is a bad idea. Yield to ata_piix.
1340 pci_read_config_byte(pdev, ICH_MAP, &map);
1342 dev_info(&pdev->dev,
1343 "controller is in combined mode, can't enable AHCI mode\n");
1348 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1351 hpriv->flags |= (unsigned long)pi.private_data;
1353 /* MCP65 revision A1 and A2 can't do MSI */
1354 if (board_id == board_ahci_mcp65 &&
1355 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1356 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1358 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1359 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1360 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1362 /* only some SB600s can do 64bit DMA */
1363 if (ahci_sb600_enable_64bit(pdev))
1364 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1366 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1369 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1371 /* save initial config */
1372 ahci_pci_save_initial_config(pdev, hpriv);
1375 if (hpriv->cap & HOST_CAP_NCQ) {
1376 pi.flags |= ATA_FLAG_NCQ;
1378 * Auto-activate optimization is supposed to be
1379 * supported on all AHCI controllers indicating NCQ
1380 * capability, but it seems to be broken on some
1381 * chipsets including NVIDIAs.
1383 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1384 pi.flags |= ATA_FLAG_FPDMA_AA;
1387 if (hpriv->cap & HOST_CAP_PMP)
1388 pi.flags |= ATA_FLAG_PMP;
1390 ahci_set_em_messages(hpriv, &pi);
1392 if (ahci_broken_system_poweroff(pdev)) {
1393 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1394 dev_info(&pdev->dev,
1395 "quirky BIOS, skipping spindown on poweroff\n");
1398 if (ahci_broken_suspend(pdev)) {
1399 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1400 dev_warn(&pdev->dev,
1401 "BIOS update required for suspend/resume\n");
1404 if (ahci_broken_online(pdev)) {
1405 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1406 dev_info(&pdev->dev,
1407 "online status unreliable, applying workaround\n");
1410 /* CAP.NP sometimes indicate the index of the last enabled
1411 * port, at other times, that of the last possible port, so
1412 * determining the maximum port number requires looking at
1413 * both CAP.NP and port_map.
1415 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1417 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1420 host->private_data = hpriv;
1422 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1423 host->flags |= ATA_HOST_PARALLEL_SCAN;
1425 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1427 if (pi.flags & ATA_FLAG_EM)
1428 ahci_reset_em(host);
1430 for (i = 0; i < host->n_ports; i++) {
1431 struct ata_port *ap = host->ports[i];
1433 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1434 ata_port_pbar_desc(ap, ahci_pci_bar,
1435 0x100 + ap->port_no * 0x80, "port");
1437 /* set enclosure management message type */
1438 if (ap->flags & ATA_FLAG_EM)
1439 ap->em_message_type = hpriv->em_msg_type;
1442 /* disabled/not-implemented port */
1443 if (!(hpriv->port_map & (1 << i)))
1444 ap->ops = &ata_dummy_port_ops;
1447 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1448 ahci_p5wdh_workaround(host);
1450 /* apply gtf filter quirk */
1451 ahci_gtf_filter_workaround(host);
1453 /* initialize adapter */
1454 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1458 rc = ahci_pci_reset_controller(host);
1462 ahci_pci_init_controller(host);
1463 ahci_pci_print_info(host);
1465 pci_set_master(pdev);
1466 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1470 static int __init ahci_init(void)
1472 return pci_register_driver(&ahci_pci_driver);
1475 static void __exit ahci_exit(void)
1477 pci_unregister_driver(&ahci_pci_driver);
1481 MODULE_AUTHOR("Jeff Garzik");
1482 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1483 MODULE_LICENSE("GPL");
1484 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1485 MODULE_VERSION(DRV_VERSION);
1487 module_init(ahci_init);
1488 module_exit(ahci_exit);