2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] =
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nosntf] =
128 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_yes_fbs] =
136 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
180 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
181 AHCI_HFLAG_32BIT_ONLY),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_pmp_retry_srst_ops,
187 [board_ahci_sb700] = /* for SB700 and SB800 */
189 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_vt8251] =
197 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_vt8251_ops,
205 static const struct pci_device_id ahci_pci_tbl[] = {
207 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
208 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
209 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
210 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
211 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
212 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
213 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
216 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
217 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
220 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
222 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
236 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
239 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
249 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
254 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
257 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
260 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
274 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
275 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
282 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
283 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
298 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
302 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
306 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
307 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
308 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
311 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
312 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
316 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
317 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
321 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
322 /* AMD is using RAID class only for ahci controllers */
323 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
324 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
327 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
328 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
331 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
418 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
419 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
421 /* ST Microelectronics */
422 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
425 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
426 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
427 { PCI_DEVICE(0x1b4b, 0x9123),
428 .class = PCI_CLASS_STORAGE_SATA_AHCI,
429 .class_mask = 0xffffff,
430 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
431 { PCI_DEVICE(0x1b4b, 0x9125),
432 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
433 { PCI_DEVICE(0x1b4b, 0x917a),
434 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
435 { PCI_DEVICE(0x1b4b, 0x9192),
436 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
437 { PCI_DEVICE(0x1b4b, 0x91a3),
438 .driver_data = board_ahci_yes_fbs },
441 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
444 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
445 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
446 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
447 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
450 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
452 /* Generic, PCI class code for AHCI */
453 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
454 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
456 { } /* terminate list */
460 static struct pci_driver ahci_pci_driver = {
462 .id_table = ahci_pci_tbl,
463 .probe = ahci_init_one,
464 .remove = ata_pci_remove_one,
466 .suspend = ahci_pci_device_suspend,
467 .resume = ahci_pci_device_resume,
471 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
472 static int marvell_enable;
474 static int marvell_enable = 1;
476 module_param(marvell_enable, int, 0644);
477 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
480 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
481 struct ahci_host_priv *hpriv)
483 unsigned int force_port_map = 0;
484 unsigned int mask_port_map = 0;
486 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
487 dev_info(&pdev->dev, "JMB361 has only one port\n");
492 * Temporary Marvell 6145 hack: PATA port presence
493 * is asserted through the standard AHCI port
494 * presence register, as bit 4 (counting from 0)
496 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
497 if (pdev->device == 0x6121)
502 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
505 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
509 static int ahci_pci_reset_controller(struct ata_host *host)
511 struct pci_dev *pdev = to_pci_dev(host->dev);
513 ahci_reset_controller(host);
515 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
516 struct ahci_host_priv *hpriv = host->private_data;
520 pci_read_config_word(pdev, 0x92, &tmp16);
521 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
522 tmp16 |= hpriv->port_map;
523 pci_write_config_word(pdev, 0x92, tmp16);
530 static void ahci_pci_init_controller(struct ata_host *host)
532 struct ahci_host_priv *hpriv = host->private_data;
533 struct pci_dev *pdev = to_pci_dev(host->dev);
534 void __iomem *port_mmio;
538 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
539 if (pdev->device == 0x6121)
543 port_mmio = __ahci_port_base(host, mv);
545 writel(0, port_mmio + PORT_IRQ_MASK);
548 tmp = readl(port_mmio + PORT_IRQ_STAT);
549 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
551 writel(tmp, port_mmio + PORT_IRQ_STAT);
554 ahci_init_controller(host);
557 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
558 unsigned long deadline)
560 struct ata_port *ap = link->ap;
566 ahci_stop_engine(ap);
568 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
569 deadline, &online, NULL);
571 ahci_start_engine(ap);
573 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
575 /* vt8251 doesn't clear BSY on signature FIS reception,
576 * request follow-up softreset.
578 return online ? -EAGAIN : rc;
581 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
582 unsigned long deadline)
584 struct ata_port *ap = link->ap;
585 struct ahci_port_priv *pp = ap->private_data;
586 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
587 struct ata_taskfile tf;
591 ahci_stop_engine(ap);
593 /* clear D2H reception area to properly wait for D2H FIS */
594 ata_tf_init(link->device, &tf);
596 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
598 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
599 deadline, &online, NULL);
601 ahci_start_engine(ap);
603 /* The pseudo configuration device on SIMG4726 attached to
604 * ASUS P5W-DH Deluxe doesn't send signature FIS after
605 * hardreset if no device is attached to the first downstream
606 * port && the pseudo device locks up on SRST w/ PMP==0. To
607 * work around this, wait for !BSY only briefly. If BSY isn't
608 * cleared, perform CLO and proceed to IDENTIFY (achieved by
609 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
611 * Wait for two seconds. Devices attached to downstream port
612 * which can't process the following IDENTIFY after this will
613 * have to be reset again. For most cases, this should
614 * suffice while making probing snappish enough.
617 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
620 ahci_kick_engine(ap);
626 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
628 struct ata_host *host = dev_get_drvdata(&pdev->dev);
629 struct ahci_host_priv *hpriv = host->private_data;
630 void __iomem *mmio = hpriv->mmio;
633 if (mesg.event & PM_EVENT_SUSPEND &&
634 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
636 "BIOS update required for suspend/resume\n");
640 if (mesg.event & PM_EVENT_SLEEP) {
641 /* AHCI spec rev1.1 section 8.3.3:
642 * Software must disable interrupts prior to requesting a
643 * transition of the HBA to D3 state.
645 ctl = readl(mmio + HOST_CTL);
647 writel(ctl, mmio + HOST_CTL);
648 readl(mmio + HOST_CTL); /* flush */
651 return ata_pci_device_suspend(pdev, mesg);
654 static int ahci_pci_device_resume(struct pci_dev *pdev)
656 struct ata_host *host = dev_get_drvdata(&pdev->dev);
659 rc = ata_pci_device_do_resume(pdev);
663 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
664 rc = ahci_pci_reset_controller(host);
668 ahci_pci_init_controller(host);
671 ata_host_resume(host);
677 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
682 * If the device fixup already set the dma_mask to some non-standard
683 * value, don't extend it here. This happens on STA2X11, for example.
685 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
689 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
690 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
692 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
695 "64-bit DMA enable failed\n");
700 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
702 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
705 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
708 "32-bit consistent DMA enable failed\n");
715 static void ahci_pci_print_info(struct ata_host *host)
717 struct pci_dev *pdev = to_pci_dev(host->dev);
721 pci_read_config_word(pdev, 0x0a, &cc);
722 if (cc == PCI_CLASS_STORAGE_IDE)
724 else if (cc == PCI_CLASS_STORAGE_SATA)
726 else if (cc == PCI_CLASS_STORAGE_RAID)
731 ahci_print_info(host, scc_s);
734 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
735 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
736 * support PMP and the 4726 either directly exports the device
737 * attached to the first downstream port or acts as a hardware storage
738 * controller and emulate a single ATA device (can be RAID 0/1 or some
739 * other configuration).
741 * When there's no device attached to the first downstream port of the
742 * 4726, "Config Disk" appears, which is a pseudo ATA device to
743 * configure the 4726. However, ATA emulation of the device is very
744 * lame. It doesn't send signature D2H Reg FIS after the initial
745 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
747 * The following function works around the problem by always using
748 * hardreset on the port and not depending on receiving signature FIS
749 * afterward. If signature FIS isn't received soon, ATA class is
750 * assumed without follow-up softreset.
752 static void ahci_p5wdh_workaround(struct ata_host *host)
754 static struct dmi_system_id sysids[] = {
756 .ident = "P5W DH Deluxe",
758 DMI_MATCH(DMI_SYS_VENDOR,
759 "ASUSTEK COMPUTER INC"),
760 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
765 struct pci_dev *pdev = to_pci_dev(host->dev);
767 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
768 dmi_check_system(sysids)) {
769 struct ata_port *ap = host->ports[1];
772 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
774 ap->ops = &ahci_p5wdh_ops;
775 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
779 /* only some SB600 ahci controllers can do 64bit DMA */
780 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
782 static const struct dmi_system_id sysids[] = {
784 * The oldest version known to be broken is 0901 and
785 * working is 1501 which was released on 2007-10-26.
786 * Enable 64bit DMA on 1501 and anything newer.
788 * Please read bko#9412 for more info.
791 .ident = "ASUS M2A-VM",
793 DMI_MATCH(DMI_BOARD_VENDOR,
794 "ASUSTeK Computer INC."),
795 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
797 .driver_data = "20071026", /* yyyymmdd */
800 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
803 * BIOS versions earlier than 1.5 had the Manufacturer DMI
804 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
805 * This spelling mistake was fixed in BIOS version 1.5, so
806 * 1.5 and later have the Manufacturer as
807 * "MICRO-STAR INTERNATIONAL CO.,LTD".
808 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
810 * BIOS versions earlier than 1.9 had a Board Product Name
811 * DMI field of "MS-7376". This was changed to be
812 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
813 * match on DMI_BOARD_NAME of "MS-7376".
816 .ident = "MSI K9A2 Platinum",
818 DMI_MATCH(DMI_BOARD_VENDOR,
820 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
824 * All BIOS versions for the Asus M3A support 64bit DMA.
825 * (all release versions from 0301 to 1206 were tested)
830 DMI_MATCH(DMI_BOARD_VENDOR,
831 "ASUSTeK Computer INC."),
832 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
837 const struct dmi_system_id *match;
838 int year, month, date;
841 match = dmi_first_match(sysids);
842 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
846 if (!match->driver_data)
849 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
850 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
852 if (strcmp(buf, match->driver_data) >= 0)
856 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
862 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
866 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
868 static const struct dmi_system_id broken_systems[] = {
870 .ident = "HP Compaq nx6310",
872 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
873 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
875 /* PCI slot number of the controller */
876 .driver_data = (void *)0x1FUL,
879 .ident = "HP Compaq 6720s",
881 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
882 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
884 /* PCI slot number of the controller */
885 .driver_data = (void *)0x1FUL,
888 { } /* terminate list */
890 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
893 unsigned long slot = (unsigned long)dmi->driver_data;
894 /* apply the quirk only to on-board controllers */
895 return slot == PCI_SLOT(pdev->devfn);
901 static bool ahci_broken_suspend(struct pci_dev *pdev)
903 static const struct dmi_system_id sysids[] = {
905 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
906 * to the harddisk doesn't become online after
907 * resuming from STR. Warn and fail suspend.
909 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
911 * Use dates instead of versions to match as HP is
912 * apparently recycling both product and version
915 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
920 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
921 DMI_MATCH(DMI_PRODUCT_NAME,
922 "HP Pavilion dv4 Notebook PC"),
924 .driver_data = "20090105", /* F.30 */
929 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
930 DMI_MATCH(DMI_PRODUCT_NAME,
931 "HP Pavilion dv5 Notebook PC"),
933 .driver_data = "20090506", /* F.16 */
938 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
939 DMI_MATCH(DMI_PRODUCT_NAME,
940 "HP Pavilion dv6 Notebook PC"),
942 .driver_data = "20090423", /* F.21 */
947 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
948 DMI_MATCH(DMI_PRODUCT_NAME,
949 "HP HDX18 Notebook PC"),
951 .driver_data = "20090430", /* F.23 */
954 * Acer eMachines G725 has the same problem. BIOS
955 * V1.03 is known to be broken. V3.04 is known to
956 * work. Between, there are V1.06, V2.06 and V3.03
957 * that we don't have much idea about. For now,
958 * blacklist anything older than V3.04.
960 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
965 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
968 .driver_data = "20091216", /* V3.04 */
970 { } /* terminate list */
972 const struct dmi_system_id *dmi = dmi_first_match(sysids);
973 int year, month, date;
976 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
979 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
980 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
982 return strcmp(buf, dmi->driver_data) < 0;
985 static bool ahci_broken_online(struct pci_dev *pdev)
987 #define ENCODE_BUSDEVFN(bus, slot, func) \
988 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
989 static const struct dmi_system_id sysids[] = {
991 * There are several gigabyte boards which use
992 * SIMG5723s configured as hardware RAID. Certain
993 * 5723 firmware revisions shipped there keep the link
994 * online but fail to answer properly to SRST or
995 * IDENTIFY when no device is attached downstream
996 * causing libata to retry quite a few times leading
997 * to excessive detection delay.
999 * As these firmwares respond to the second reset try
1000 * with invalid device signature, considering unknown
1001 * sig as offline works around the problem acceptably.
1004 .ident = "EP45-DQ6",
1006 DMI_MATCH(DMI_BOARD_VENDOR,
1007 "Gigabyte Technology Co., Ltd."),
1008 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1010 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1013 .ident = "EP45-DS5",
1015 DMI_MATCH(DMI_BOARD_VENDOR,
1016 "Gigabyte Technology Co., Ltd."),
1017 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1019 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1021 { } /* terminate list */
1023 #undef ENCODE_BUSDEVFN
1024 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1030 val = (unsigned long)dmi->driver_data;
1032 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1035 #ifdef CONFIG_ATA_ACPI
1036 static void ahci_gtf_filter_workaround(struct ata_host *host)
1038 static const struct dmi_system_id sysids[] = {
1040 * Aspire 3810T issues a bunch of SATA enable commands
1041 * via _GTF including an invalid one and one which is
1042 * rejected by the device. Among the successful ones
1043 * is FPDMA non-zero offset enable which when enabled
1044 * only on the drive side leads to NCQ command
1045 * failures. Filter it out.
1048 .ident = "Aspire 3810T",
1050 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1051 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1053 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1057 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1058 unsigned int filter;
1064 filter = (unsigned long)dmi->driver_data;
1065 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1066 filter, dmi->ident);
1068 for (i = 0; i < host->n_ports; i++) {
1069 struct ata_port *ap = host->ports[i];
1070 struct ata_link *link;
1071 struct ata_device *dev;
1073 ata_for_each_link(link, ap, EDGE)
1074 ata_for_each_dev(dev, link, ALL)
1075 dev->gtf_filter |= filter;
1079 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1083 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1085 unsigned int board_id = ent->driver_data;
1086 struct ata_port_info pi = ahci_port_info[board_id];
1087 const struct ata_port_info *ppi[] = { &pi, NULL };
1088 struct device *dev = &pdev->dev;
1089 struct ahci_host_priv *hpriv;
1090 struct ata_host *host;
1092 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1096 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1098 ata_print_version_once(&pdev->dev, DRV_VERSION);
1100 /* The AHCI driver can only drive the SATA ports, the PATA driver
1101 can drive them all so if both drivers are selected make sure
1102 AHCI stays out of the way */
1103 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1107 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1108 * ahci, use ata_generic instead.
1110 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1111 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1112 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1113 pdev->subsystem_device == 0xcb89)
1116 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1117 * At the moment, we can only use the AHCI mode. Let the users know
1118 * that for SAS drives they're out of luck.
1120 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1121 dev_info(&pdev->dev,
1122 "PDC42819 can only drive SATA devices with this driver\n");
1124 /* Both Connext and Enmotus devices use non-standard BARs */
1125 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1126 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1127 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1128 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1130 /* acquire resources */
1131 rc = pcim_enable_device(pdev);
1135 /* AHCI controllers often implement SFF compatible interface.
1136 * Grab all PCI BARs just in case.
1138 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1140 pcim_pin_device(pdev);
1144 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1145 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1148 /* ICH6s share the same PCI ID for both piix and ahci
1149 * modes. Enabling ahci mode while MAP indicates
1150 * combined mode is a bad idea. Yield to ata_piix.
1152 pci_read_config_byte(pdev, ICH_MAP, &map);
1154 dev_info(&pdev->dev,
1155 "controller is in combined mode, can't enable AHCI mode\n");
1160 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1163 hpriv->flags |= (unsigned long)pi.private_data;
1165 /* MCP65 revision A1 and A2 can't do MSI */
1166 if (board_id == board_ahci_mcp65 &&
1167 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1168 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1170 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1171 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1172 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1174 /* only some SB600s can do 64bit DMA */
1175 if (ahci_sb600_enable_64bit(pdev))
1176 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1178 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1181 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1183 /* save initial config */
1184 ahci_pci_save_initial_config(pdev, hpriv);
1187 if (hpriv->cap & HOST_CAP_NCQ) {
1188 pi.flags |= ATA_FLAG_NCQ;
1190 * Auto-activate optimization is supposed to be
1191 * supported on all AHCI controllers indicating NCQ
1192 * capability, but it seems to be broken on some
1193 * chipsets including NVIDIAs.
1195 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1196 pi.flags |= ATA_FLAG_FPDMA_AA;
1199 if (hpriv->cap & HOST_CAP_PMP)
1200 pi.flags |= ATA_FLAG_PMP;
1202 ahci_set_em_messages(hpriv, &pi);
1204 if (ahci_broken_system_poweroff(pdev)) {
1205 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1206 dev_info(&pdev->dev,
1207 "quirky BIOS, skipping spindown on poweroff\n");
1210 if (ahci_broken_suspend(pdev)) {
1211 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1212 dev_warn(&pdev->dev,
1213 "BIOS update required for suspend/resume\n");
1216 if (ahci_broken_online(pdev)) {
1217 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1218 dev_info(&pdev->dev,
1219 "online status unreliable, applying workaround\n");
1222 /* CAP.NP sometimes indicate the index of the last enabled
1223 * port, at other times, that of the last possible port, so
1224 * determining the maximum port number requires looking at
1225 * both CAP.NP and port_map.
1227 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1229 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1232 host->private_data = hpriv;
1234 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1235 host->flags |= ATA_HOST_PARALLEL_SCAN;
1237 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1239 if (pi.flags & ATA_FLAG_EM)
1240 ahci_reset_em(host);
1242 for (i = 0; i < host->n_ports; i++) {
1243 struct ata_port *ap = host->ports[i];
1245 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1246 ata_port_pbar_desc(ap, ahci_pci_bar,
1247 0x100 + ap->port_no * 0x80, "port");
1249 /* set enclosure management message type */
1250 if (ap->flags & ATA_FLAG_EM)
1251 ap->em_message_type = hpriv->em_msg_type;
1254 /* disabled/not-implemented port */
1255 if (!(hpriv->port_map & (1 << i)))
1256 ap->ops = &ata_dummy_port_ops;
1259 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1260 ahci_p5wdh_workaround(host);
1262 /* apply gtf filter quirk */
1263 ahci_gtf_filter_workaround(host);
1265 /* initialize adapter */
1266 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1270 rc = ahci_pci_reset_controller(host);
1274 ahci_pci_init_controller(host);
1275 ahci_pci_print_info(host);
1277 pci_set_master(pdev);
1278 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1282 static int __init ahci_init(void)
1284 return pci_register_driver(&ahci_pci_driver);
1287 static void __exit ahci_exit(void)
1289 pci_unregister_driver(&ahci_pci_driver);
1293 MODULE_AUTHOR("Jeff Garzik");
1294 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1295 MODULE_LICENSE("GPL");
1296 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1297 MODULE_VERSION(DRV_VERSION);
1299 module_init(ahci_init);
1300 module_exit(ahci_exit);