2 * core routines for the asynchronous memory transfer/transform api
4 * Copyright © 2006, Intel Corporation.
6 * Dan Williams <dan.j.williams@intel.com>
8 * with architecture considerations by:
9 * Neil Brown <neilb@suse.de>
10 * Jeff Garzik <jeff@garzik.org>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc.,
23 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 #include <linux/rculist.h>
27 #include <linux/kernel.h>
28 #include <linux/async_tx.h>
30 #ifdef CONFIG_DMA_ENGINE
31 static int __init async_tx_init(void)
33 async_dmaengine_get();
35 printk(KERN_INFO "async_tx: api initialized (async)\n");
40 static void __exit async_tx_exit(void)
42 async_dmaengine_put();
45 module_init(async_tx_init);
46 module_exit(async_tx_exit);
49 * __async_tx_find_channel - find a channel to carry out the operation or let
50 * the transaction execute synchronously
51 * @submit: transaction dependency and submission modifiers
52 * @tx_type: transaction type
55 __async_tx_find_channel(struct async_submit_ctl *submit,
56 enum dma_transaction_type tx_type)
58 struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
60 /* see if we can keep the chain on one channel */
62 dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
63 return depend_tx->chan;
64 return async_dma_find_channel(tx_type);
66 EXPORT_SYMBOL_GPL(__async_tx_find_channel);
71 * async_tx_channel_switch - queue an interrupt descriptor with a dependency
73 * @depend_tx: the operation that must finish before the new operation runs
74 * @tx: the new operation
77 async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
78 struct dma_async_tx_descriptor *tx)
80 struct dma_chan *chan;
81 struct dma_device *device;
82 struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
84 /* first check to see if we can still append to depend_tx */
85 spin_lock_bh(&depend_tx->lock);
86 if (depend_tx->parent && depend_tx->chan == tx->chan) {
87 tx->parent = depend_tx;
91 spin_unlock_bh(&depend_tx->lock);
96 chan = depend_tx->chan;
97 device = chan->device;
99 /* see if we can schedule an interrupt
100 * otherwise poll for completion
102 if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
103 intr_tx = device->device_prep_dma_interrupt(chan, 0);
108 intr_tx->callback = NULL;
109 intr_tx->callback_param = NULL;
110 tx->parent = intr_tx;
111 /* safe to set ->next outside the lock since we know we are
116 /* check if we need to append */
117 spin_lock_bh(&depend_tx->lock);
118 if (depend_tx->parent) {
119 intr_tx->parent = depend_tx;
120 depend_tx->next = intr_tx;
121 async_tx_ack(intr_tx);
124 spin_unlock_bh(&depend_tx->lock);
127 intr_tx->parent = NULL;
128 intr_tx->tx_submit(intr_tx);
129 async_tx_ack(intr_tx);
132 if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
133 panic("%s: DMA_ERROR waiting for depend_tx\n",
141 * submit_disposition - flags for routing an incoming operation
142 * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
143 * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
144 * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
146 * while holding depend_tx->lock we must avoid submitting new operations
147 * to prevent a circular locking dependency with drivers that already
148 * hold a channel lock when calling async_tx_run_dependencies.
150 enum submit_disposition {
152 ASYNC_TX_CHANNEL_SWITCH,
153 ASYNC_TX_DIRECT_SUBMIT,
157 async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
158 struct async_submit_ctl *submit)
160 struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
162 tx->callback = submit->cb_fn;
163 tx->callback_param = submit->cb_param;
166 enum submit_disposition s;
168 /* sanity check the dependency chain:
169 * 1/ if ack is already set then we cannot be sure
170 * we are referring to the correct operation
171 * 2/ dependencies are 1:1 i.e. two transactions can
172 * not depend on the same parent
174 BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
177 /* the lock prevents async_tx_run_dependencies from missing
178 * the setting of ->next when ->parent != NULL
180 spin_lock_bh(&depend_tx->lock);
181 if (depend_tx->parent) {
182 /* we have a parent so we can not submit directly
183 * if we are staying on the same channel: append
184 * else: channel switch
186 if (depend_tx->chan == chan) {
187 tx->parent = depend_tx;
188 depend_tx->next = tx;
189 s = ASYNC_TX_SUBMITTED;
191 s = ASYNC_TX_CHANNEL_SWITCH;
193 /* we do not have a parent so we may be able to submit
194 * directly if we are staying on the same channel
196 if (depend_tx->chan == chan)
197 s = ASYNC_TX_DIRECT_SUBMIT;
199 s = ASYNC_TX_CHANNEL_SWITCH;
201 spin_unlock_bh(&depend_tx->lock);
204 case ASYNC_TX_SUBMITTED:
206 case ASYNC_TX_CHANNEL_SWITCH:
207 async_tx_channel_switch(depend_tx, tx);
209 case ASYNC_TX_DIRECT_SUBMIT:
219 if (submit->flags & ASYNC_TX_ACK)
223 async_tx_ack(depend_tx);
225 EXPORT_SYMBOL_GPL(async_tx_submit);
228 * async_trigger_callback - schedules the callback function to be run
229 * @submit: submission and completion parameters
231 * honored flags: ASYNC_TX_ACK
233 * The callback is run after any dependent operations have completed.
235 struct dma_async_tx_descriptor *
236 async_trigger_callback(struct async_submit_ctl *submit)
238 struct dma_chan *chan;
239 struct dma_device *device;
240 struct dma_async_tx_descriptor *tx;
241 struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
244 chan = depend_tx->chan;
245 device = chan->device;
247 /* see if we can schedule an interrupt
248 * otherwise poll for completion
250 if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
253 tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
258 pr_debug("%s: (async)\n", __func__);
260 async_tx_submit(chan, tx, submit);
262 pr_debug("%s: (sync)\n", __func__);
264 /* wait for any prerequisite operations */
265 async_tx_quiesce(&submit->depend_tx);
267 async_tx_sync_epilog(submit);
272 EXPORT_SYMBOL_GPL(async_trigger_callback);
275 * async_tx_quiesce - ensure tx is complete and freeable upon return
276 * @tx - transaction to quiesce
278 void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
281 /* if ack is already set then we cannot be sure
282 * we are referring to the correct operation
284 BUG_ON(async_tx_test_ack(*tx));
285 if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
286 panic("DMA_ERROR waiting for transaction\n");
291 EXPORT_SYMBOL_GPL(async_tx_quiesce);
293 MODULE_AUTHOR("Intel Corporation");
294 MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
295 MODULE_LICENSE("GPL");