3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
34 #ifdef CFG_DISCOVER_PHY
36 static void mii_discover_phy(void);
39 /* Ethernet Transmit and Receive Buffers */
40 #define DBUF_LENGTH 1520
46 #define PKT_MAXBUF_SIZE 1518
47 #define PKT_MINBUF_SIZE 64
48 #define PKT_MAXBLR_SIZE 1520
51 static char txbuf[DBUF_LENGTH];
53 static uint rxIdx; /* index of the current RX buffer */
54 static uint txIdx; /* index of the current TX buffer */
57 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
58 * immr->udata_bd address on Dual-Port RAM
59 * Provide for Double Buffering
62 typedef volatile struct CommonBufferDescriptor {
63 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
64 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
67 static RTXBD *rtx = NULL;
69 static int fec_send(struct eth_device* dev, volatile void *packet, int length);
70 static int fec_recv(struct eth_device* dev);
71 static int fec_init(struct eth_device* dev, bd_t * bd);
72 static void fec_halt(struct eth_device* dev);
74 int fec_initialize(bd_t *bis)
76 struct eth_device* dev;
78 dev = (struct eth_device*) malloc(sizeof *dev);
80 sprintf(dev->name, "FEC ETHERNET");
93 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
96 volatile immap_t *immr = (immap_t *) CFG_IMMR;
97 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
103 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
108 printf("TX not ready\n");
111 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
112 rtx->txbd[txIdx].cbd_datlen = length;
113 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
116 /* Activate transmit Buffer Descriptor polling */
117 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
120 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
121 #if defined(CONFIG_ICU862)
129 printf("TX timeout\n");
132 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
133 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
134 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
136 /* return only status bits */;
137 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
139 txIdx = (txIdx + 1) % TX_BUF_CNT;
144 static int fec_recv(struct eth_device* dev)
147 volatile immap_t *immr = (immap_t *) CFG_IMMR;
148 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
151 /* section 16.9.23.2 */
152 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
154 break; /* nothing received - leave for() loop */
157 length = rtx->rxbd[rxIdx].cbd_datlen;
159 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
161 printf("%s[%d] err: %x\n",
162 __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
165 /* Pass the packet up to the protocol layers. */
166 NetReceive(NetRxPackets[rxIdx], length - 4);
169 /* Give the buffer back to the FEC. */
170 rtx->rxbd[rxIdx].cbd_datlen = 0;
172 /* wrap around buffer index when necessary */
173 if ((rxIdx + 1) >= PKTBUFSRX) {
174 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
177 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
183 /* Try to fill Buffer Descriptors */
184 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
190 /**************************************************************
192 * FEC Ethernet Initialization Routine
194 *************************************************************/
196 #define FEC_ECNTRL_PINMUX 0x00000004
197 #define FEC_ECNTRL_ETHER_EN 0x00000002
198 #define FEC_ECNTRL_RESET 0x00000001
200 #define FEC_RCNTRL_BC_REJ 0x00000010
201 #define FEC_RCNTRL_PROM 0x00000008
202 #define FEC_RCNTRL_MII_MODE 0x00000004
203 #define FEC_RCNTRL_DRT 0x00000002
204 #define FEC_RCNTRL_LOOP 0x00000001
206 #define FEC_TCNTRL_FDEN 0x00000004
207 #define FEC_TCNTRL_HBC 0x00000002
208 #define FEC_TCNTRL_GTS 0x00000001
210 #define FEC_RESET_DELAY 50
212 static int fec_init(struct eth_device* dev, bd_t * bd)
216 volatile immap_t *immr = (immap_t *) CFG_IMMR;
217 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
219 #if defined(CONFIG_FADS) && defined(CONFIG_MPC860T)
220 /* configure FADS for fast (FEC) ethernet, half-duplex */
221 /* The LXT970 needs about 50ms to recover from reset, so
222 * wait for it by discovering the PHY before leaving eth_init().
225 volatile uint *bcsr4 = (volatile uint *) BCSR4;
226 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
227 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
229 /* reset the LXT970 PHY */
230 *bcsr4 &= ~BCSR4_FETHRST;
232 *bcsr4 |= BCSR4_FETHRST;
237 * A delay is required between a reset of the FEC block and
238 * initialization of other FEC registers because the reset takes
239 * some time to complete. If you don't delay, subsequent writes
240 * to FEC registers might get killed by the reset routine which is
243 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
245 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
249 if (i == FEC_RESET_DELAY) {
250 printf ("FEC_RESET_DELAY timeout\n");
254 /* We use strictly polling mode only
258 /* Clear any pending interrupt
260 fecp->fec_ievent = 0xffc0;
262 /* No need to set the IVEC register */
264 /* Set station address
266 #define ea eth_get_dev()->enetaddr
267 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
268 (ea[2] << 8) | (ea[3] ) ;
269 fecp->fec_addr_high = (ea[4] << 8) | (ea[5] ) ;
272 /* Clear multicast address hash table
274 fecp->fec_hash_table_high = 0;
275 fecp->fec_hash_table_low = 0;
277 /* Set maximum receive buffer size.
279 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
281 /* Set maximum frame length
283 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
286 * Setup Buffers and Buffer Desriptors
292 #ifdef CFG_ALLOC_DPRAM
293 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align(sizeof(RTXBD),8));
295 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
299 * Setup Receiver Buffer Descriptors (13.14.24.18)
303 for (i = 0; i < PKTBUFSRX; i++) {
304 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
305 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
306 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
308 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
311 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
315 for (i = 0; i < TX_BUF_CNT; i++) {
316 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
317 rtx->txbd[i].cbd_datlen = 0; /* Reset */
318 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
320 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
322 /* Set receive and transmit descriptor base
324 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
325 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
329 #if 0 /* Full duplex mode */
330 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
331 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
332 #else /* Half duplex mode */
333 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
334 fecp->fec_x_cntrl = 0;
337 /* Enable big endian and don't care about SDMA FC.
339 fecp->fec_fun_code = 0x78000000;
341 /* Set MII speed to 2.5 MHz or slightly below.
342 * According to the MPC860T (Rev. D) Fast ethernet controller user
344 * the MII management interface clock must be less than or equal
346 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
347 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
349 fecp->fec_mii_speed = ((bd->bi_busfreq + 4999999) / 5000000) << 1;
351 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
352 /* Configure all of port D for MII.
354 immr->im_ioport.iop_pdpar = 0x1fff;
356 /* Bits moved from Rev. D onward */
357 if ((get_immr (0) & 0xffff) < 0x0501) {
358 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
360 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
363 /* Configure port A for MII.
366 #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
368 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
369 * of CPU, so for this board we need to configure Utopia and
370 * enable PD8 to MII-MDC function */
371 immr->im_ioport.iop_pdpar |= 0x4080;
374 /* Has Utopia been configured? */
375 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
377 * YES - Use MUXED mode for UTOPIA bus.
378 * This frees Port A for use by MII (see 862UM table 41-6).
380 immr->im_ioport.utmode &= ~0x80;
383 * NO - set SPLIT mode for UTOPIA bus.
385 * This doesn't really effect UTOPIA (which isn't
386 * enabled anyway) but just tells the 862
387 * to use port A for MII (see 862UM table 41-6).
389 immr->im_ioport.utmode |= 0x80;
391 #endif /* !defined(CONFIG_ICU862) */
396 /* Now enable the transmit and receive processing
398 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
400 #ifdef CFG_DISCOVER_PHY
401 /* wait for the PHY to wake up after reset
406 /* And last, try to fill Rx Buffer Descriptors */
407 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
414 static void fec_halt(struct eth_device* dev)
417 volatile immap_t *immr = (immap_t *)CFG_IMMR;
418 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
425 volatile immap_t *immr = (immap_t *)CFG_IMMR;
426 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
430 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
432 static int phyaddr = -1; /* didn't find a PHY yet */
435 /* Make MII read/write commands for the FEC.
438 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
441 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
442 (REG & 0x1f) << 18) | \
445 /* Interrupt events/masks.
447 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
448 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
449 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
450 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
451 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
452 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
453 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
454 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
455 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
456 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
458 /* PHY identification
460 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
461 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
462 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
463 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
464 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
465 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
466 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
469 /* send command to phy using mii, wait for result */
471 mii_send(uint mii_cmd)
476 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
478 ep->fec_mii_data = mii_cmd; /* command to phy */
480 /* wait for mii complete */
481 while (!(ep->fec_ievent & FEC_ENET_MII))
482 ; /* spin until done */
483 mii_reply = ep->fec_mii_data; /* result from phy */
484 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
486 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
487 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
489 return (mii_reply & 0xffff); /* data read from phy */
491 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
493 #if defined(CFG_DISCOVER_PHY)
495 mii_discover_phy(void)
497 #define MAX_PHY_PASSES 11
501 phyaddr = -1; /* didn't find a PHY yet */
502 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
504 /* PHY may need more time to recover from reset.
505 * The LXT970 needs 50ms typical, no maximum is
506 * specified, so wait 10ms before try again.
507 * With 11 passes this gives it 100ms to wake up.
509 udelay(10000); /* wait 10ms */
511 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
512 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
514 printf("PHY type 0x%x pass %d type ", phytype, pass);
516 if (phytype != 0xffff) {
519 phytype |= mii_send(mk_mii_read(phyno,
523 printf("PHY @ 0x%x pass %d type ",phyno,pass);
524 switch (phytype & 0xfffffff0) {
537 case PHY_ID_AMD79C784:
538 printf("AMD79C784\n");
540 case PHY_ID_LSI80225B:
541 printf("LSI L80225/B\n");
544 printf("0x%08x\n", phytype);
552 printf("No PHY device found.\n");
555 #endif /* CFG_DISCOVER_PHY */
557 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
559 static int mii_init_done = 0;
561 /****************************************************************************
562 * mii_init -- Initialize the MII for MII command without ethernet
563 * This function is a subset of eth_init
564 ****************************************************************************
568 DECLARE_GLOBAL_DATA_PTR;
571 volatile immap_t *immr = (immap_t *) CFG_IMMR;
572 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
575 if (mii_init_done != 0) {
580 * A delay is required between a reset of the FEC block and
581 * initialization of other FEC registers because the reset takes
582 * some time to complete. If you don't delay, subsequent writes
583 * to FEC registers might get killed by the reset routine which is
587 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
589 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
593 if (i == FEC_RESET_DELAY) {
594 printf ("FEC_RESET_DELAY timeout\n");
598 /* We use strictly polling mode only
602 /* Clear any pending interrupt
604 fecp->fec_ievent = 0xffc0;
606 /* Set MII speed to 2.5 MHz or slightly below.
607 * According to the MPC860T (Rev. D) Fast ethernet controller user
609 * the MII management interface clock must be less than or equal
611 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
612 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
614 fecp->fec_mii_speed = ((bd->bi_busfreq + 4999999) / 5000000) << 1;
616 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
617 /* Configure all of port D for MII.
619 immr->im_ioport.iop_pdpar = 0x1fff;
621 /* Bits moved from Rev. D onward */
622 if ((get_immr (0) & 0xffff) < 0x0501) {
623 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
625 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
628 /* Configure port A for MII.
631 #if defined(CONFIG_ICU862)
633 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
634 * of CPU, so for this board we need to configure Utopia and
635 * enable PD8 to MII-MDC function */
636 immr->im_ioport.iop_pdpar |= 0x4080;
639 /* Has Utopia been configured? */
640 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
642 * YES - Use MUXED mode for UTOPIA bus.
643 * This frees Port A for use by MII (see 862UM table 41-6).
645 immr->im_ioport.utmode &= ~0x80;
648 * NO - set SPLIT mode for UTOPIA bus.
650 * This doesn't really effect UTOPIA (which isn't
651 * enabled anyway) but just tells the 862
652 * to use port A for MII (see 862UM table 41-6).
654 immr->im_ioport.utmode |= 0x80;
656 #endif /* !defined(CONFIG_ICU862) */
657 /* Now enable the transmit and receive processing
659 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
663 /*****************************************************************************
664 * Read and write a MII PHY register, routines used by MII Utilities
666 * FIXME: These routines are expected to return 0 on success, but mii_send
667 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
668 * no PHY connected...
669 * For now always return 0.
670 * FIXME: These routines only work after calling eth_init() at least once!
671 * Otherwise they hang in mii_send() !!! Sorry!
672 *****************************************************************************/
674 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
676 short rdreg; /* register working value */
679 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
681 rdreg = mii_send(mk_mii_read(addr, reg));
686 printf ("0x%04x\n", *value);
692 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
694 short rdreg; /* register working value */
697 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
700 rdreg = mii_send(mk_mii_write(addr, reg, value));
703 printf ("0x%04x\n", value);
708 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
710 #endif /* CFG_CMD_NET, FEC_ENET */