3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
28 /* ----- Ethernet Buffer definitions ----- */
31 unsigned long addr, size;
34 #define RBF_ADDR 0xfffffffc
35 #define RBF_OWNER (1<<0)
36 #define RBF_WRAP (1<<1)
37 #define RBF_BROADCAST (1<<31)
38 #define RBF_MULTICAST (1<<30)
39 #define RBF_UNICAST (1<<29)
40 #define RBF_EXTERNAL (1<<28)
41 #define RBF_UNKOWN (1<<27)
42 #define RBF_SIZE 0x07ff
43 #define RBF_LOCAL4 (1<<26)
44 #define RBF_LOCAL3 (1<<25)
45 #define RBF_LOCAL2 (1<<24)
46 #define RBF_LOCAL1 (1<<23)
48 #define RBF_FRAMEMAX 64
49 #define RBF_FRAMELEN 0x600
51 #ifdef CONFIG_DRIVER_ETHER
53 #if defined(CONFIG_CMD_NET)
55 /* alignment as per Errata #11 (64 bytes) is insufficient! */
56 rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
59 unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4)));
61 /* structure to interface the PHY */
66 /*********** EMAC Phy layer Management functions *************************/
69 * at91rm9200_EmacEnableMDIO
71 * Enables the MDIO bit in MAC control register
73 * p_mac - pointer to struct AT91S_EMAC
77 void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
79 /* Mac CTRL reg set for MDIO enable */
80 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
85 * at91rm9200_EmacDisableMDIO
87 * Disables the MDIO bit in MAC control register
89 * p_mac - pointer to struct AT91S_EMAC
93 void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
95 /* Mac CTRL reg set for MDIO disable */
96 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
102 * at91rm9200_EmacReadPhy
104 * Reads data from the PHY register
106 * dev - pointer to struct net_device
107 * RegisterAddress - unsigned char
108 * pInput - pointer to value read from register
110 * TRUE - if data read successfully
112 UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
113 unsigned char RegisterAddress,
114 unsigned short *pInput)
116 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
118 (RegisterAddress << 18) |
119 (AT91C_EMAC_CODE_802_3);
123 *pInput = (unsigned short) p_mac->EMAC_MAN;
131 * at91rm9200_EmacWritePhy
133 * Writes data to the PHY register
135 * dev - pointer to struct net_device
136 * RegisterAddress - unsigned char
137 * pOutput - pointer to value to be written in the register
139 * TRUE - if data read successfully
141 UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
142 unsigned char RegisterAddress,
143 unsigned short *pOutput)
145 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
146 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
147 (RegisterAddress << 18) | *pOutput;
154 int eth_init (bd_t * bd)
160 p_mac = AT91C_BASE_EMAC;
162 /* PIO Disable Register */
163 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
164 AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
165 AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
166 AT91C_PA7_ETXCK_EREFCK;
168 #ifdef CONFIG_AT91C_USE_RMII
169 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
170 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
172 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
173 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
174 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
176 /* Select B Register */
177 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
178 AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
179 AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
182 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
184 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
186 /* Init Ehternet buffers */
187 for (i = 0; i < RBF_FRAMEMAX; i++) {
188 rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
191 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
194 eth_getenv_enetaddr("ethaddr", enetaddr);
195 p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
196 | (enetaddr[1] << 8) | (enetaddr[0]);
197 p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
199 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
200 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
202 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
205 #ifdef CONFIG_AT91C_USE_RMII
206 p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
209 #if (AT91C_MASTER_CLOCK > 40000000)
210 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
211 p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
214 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
216 at91rm9200_GetPhyInterface (& PhyOps);
218 if (!PhyOps.IsPhyConnected (p_mac))
219 printf ("PHY not connected!!\n\r");
221 /* MII management start from here */
222 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
223 if (!(ret = PhyOps.Init (p_mac))) {
224 printf ("MAC: error during MII initialization\n");
228 printf ("No link\n\r");
235 int eth_send (volatile void *packet, int length)
237 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
238 p_mac->EMAC_TAR = (long) packet;
239 p_mac->EMAC_TCR = length;
240 while (p_mac->EMAC_TCR & 0x7ff);
241 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
249 if (!(rbfp->addr & RBF_OWNER))
252 size = rbfp->size & RBF_SIZE;
253 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
255 rbfp->addr &= ~RBF_OWNER;
256 if (rbfp->addr & RBF_WRAP)
261 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
270 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
271 int at91rm9200_miiphy_read(char *devname, unsigned char addr,
272 unsigned char reg, unsigned short * value)
274 at91rm9200_EmacEnableMDIO (p_mac);
275 at91rm9200_EmacReadPhy (p_mac, reg, value);
276 at91rm9200_EmacDisableMDIO (p_mac);
280 int at91rm9200_miiphy_write(char *devname, unsigned char addr,
281 unsigned char reg, unsigned short value)
283 at91rm9200_EmacEnableMDIO (p_mac);
284 at91rm9200_EmacWritePhy (p_mac, reg, &value);
285 at91rm9200_EmacDisableMDIO (p_mac);
291 int at91rm9200_miiphy_initialize(bd_t *bis)
293 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
294 miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
301 #endif /* CONFIG_DRIVER_ETHER */