board/ti/ks2_evm/board_k2hk.c

   1 /*
   2  * K2HK EVM : Board initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 unsigned int external_clk[ext_clk_count] = {
  16         [sys_clk]       =       122880000,
  17         [alt_core_clk]  =       125000000,
  18         [pa_clk]        =       122880000,
  19         [tetris_clk]    =       125000000,
  20         [ddr3a_clk]     =       100000000,
  21         [ddr3b_clk]     =       100000000,
  22 };
  23
  24 unsigned int get_external_clk(u32 clk)
  25 {
  26         unsigned int clk_freq;
  27
  28         switch (clk) {
  29         case sys_clk:
  30                 clk_freq = 122880000;
  31                 break;
  32         case alt_core_clk:
  33                 clk_freq = 125000000;
  34                 break;
  35         case pa_clk:
  36                 clk_freq = 122880000;
  37                 break;
  38         case tetris_clk:
  39                 clk_freq = 125000000;
  40                 break;
  41         case ddr3a_clk:
  42                 clk_freq = 100000000;
  43                 break;
  44         case ddr3b_clk:
  45                 clk_freq = 100000000;
  46                 break;
  47         default:
  48                 clk_freq = 0;
  49                 break;
  50         }
  51
  52         return clk_freq;
  53 }
  54
  55 static struct pll_init_data core_pll_config[NUM_SPDS] = {
  56         [SPD800]        = CORE_PLL_799,
  57         [SPD1000]       = CORE_PLL_999,
  58         [SPD1200]       = CORE_PLL_1200,
  59 };
  60
  61 s16 divn_val[16] = {
  62         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  63 };
  64
  65 static struct pll_init_data tetris_pll_config[] = {
  66         [SPD800]        = TETRIS_PLL_800,
  67         [SPD1000]       = TETRIS_PLL_1000,
  68         [SPD1200]       = TETRIS_PLL_1200,
  69         [SPD1350]       = TETRIS_PLL_1350,
  70         [SPD1400]       = TETRIS_PLL_1400,
  71 };
  72
  73 static struct pll_init_data pa_pll_config =
  74         PASS_PLL_983;
  75
  76 struct pll_init_data *get_pll_init_data(int pll)
  77 {
  78         int speed;
  79         struct pll_init_data *data;
  80
  81         switch (pll) {
  82         case MAIN_PLL:
  83                 speed = get_max_dev_speed(speeds);
  84                 data = &core_pll_config[speed];
  85                 break;
  86         case TETRIS_PLL:
  87                 speed = get_max_arm_speed(speeds);
  88                 data = &tetris_pll_config[speed];
  89                 break;
  90         case PASS_PLL:
  91                 data = &pa_pll_config;
  92                 break;
  93         default:
  94                 data = NULL;
  95         }
  96
  97         return data;
  98 }
  99
 100 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 101 struct eth_priv_t eth_priv_cfg[] = {
 102         {
 103                 .int_name       = "K2HK_EMAC",
 104                 .rx_flow        = 22,
 105                 .phy_addr       = 0,
 106                 .slave_port     = 1,
 107                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 108                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 109         },
 110         {
 111                 .int_name       = "K2HK_EMAC1",
 112                 .rx_flow        = 23,
 113                 .phy_addr       = 1,
 114                 .slave_port     = 2,
 115                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 116                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 117         },
 118         {
 119                 .int_name       = "K2HK_EMAC2",
 120                 .rx_flow        = 24,
 121                 .phy_addr       = 2,
 122                 .slave_port     = 3,
 123                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 124                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 125         },
 126         {
 127                 .int_name       = "K2HK_EMAC3",
 128                 .rx_flow        = 25,
 129                 .phy_addr       = 3,
 130                 .slave_port     = 4,
 131                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 132                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 133         },
 134 };
 135
 136 int get_num_eth_ports(void)
 137 {
 138         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_BOARD_EARLY_INIT_F
 143 int board_early_init_f(void)
 144 {
 145         init_plls();
 146
 147         return 0;
 148 }
 149 #endif
 150
 151 #if defined(CONFIG_MULTI_DTB_FIT)
 152 int board_fit_config_name_match(const char *name)
 153 {
 154         if (!strcmp(name, "keystone-k2hk-evm"))
 155                 return 0;
 156
 157         return -1;
 158 }
 159 #endif
 160
 161 #ifdef CONFIG_SPL_BUILD
 162 void spl_init_keystone_plls(void)
 163 {
 164         init_plls();
 165 }
 166 #endif