1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
12 #include <asm/arcregs.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define ARC_PERIPHERAL_BASE 0xF0000000
18 #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
19 #define CGU_ARC_FMEAS_ARC_START BIT(31)
20 #define CGU_ARC_FMEAS_ARC_DONE BIT(30)
21 #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
22 #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
23 #define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
25 #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
27 int mach_cpu_init(void)
32 /* Start frequency measurement */
33 writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
37 data = readl(CGU_ARC_FMEAS_ARC);
38 } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
40 /* Amount of reference 100 MHz clocks */
41 rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
42 CGU_ARC_FMEAS_ARC_CNT_MASK);
44 /* Amount of CPU clocks */
45 fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
46 CGU_ARC_FMEAS_ARC_CNT_MASK);
48 gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
53 int board_early_init_r(void)
55 #define EMSDP_PSRAM_BASE 0xf2001000
56 #define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
57 #define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
58 #define CRE_ENABLE BIT(31)
59 #define CRE_DRIVE_CMD BIT(6)
61 #define PSRAM_RCR_DPD BIT(1)
62 #define PSRAM_RCR_PAGE_MODE BIT(7)
65 * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
68 #define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
70 // Switch PSRAM controller to command mode
71 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
72 // Program Refresh Configuration Register (RCR) for BANK0
73 writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
74 // Switch PSRAM controller back to memory mode
75 writel(0, PSRAM_FLASH_CONFIG_REG_0);
78 // Switch PSRAM controller to command mode
79 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
80 // Program Refresh Configuration Register (RCR) for BANK1
81 writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
82 // Switch PSRAM controller back to memory mode
83 writel(0, PSRAM_FLASH_CONFIG_REG_1);
85 printf("PSRAM initialized.\n");
90 #define CREG_BASE 0xF0001000
91 #define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
92 #define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
93 #define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
95 /* Bits in CREG_BOOT register */
96 #define CREG_BOOT_WP_BIT BIT(8)
98 void reset_cpu(ulong addr)
100 writel(1, CREG_IP_SW_RESET);
102 ; /* loop forever till reset */
105 static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
107 u32 creg_boot = readl(CREG_BOOT);
109 if (!strcmp(argv[1], "unlock"))
110 creg_boot &= ~CREG_BOOT_WP_BIT;
111 else if (!strcmp(argv[1], "lock"))
112 creg_boot |= CREG_BOOT_WP_BIT;
114 return CMD_RET_USAGE;
116 writel(creg_boot, CREG_BOOT);
118 return CMD_RET_SUCCESS;
121 cmd_tbl_t cmd_emsdp[] = {
122 U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
125 static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
129 c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
131 /* Strip off leading 'emsdp' command */
135 if (c == NULL || argc > c->maxargs)
136 return CMD_RET_USAGE;
138 return c->cmd(cmdtp, flag, argc, argv);
142 emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
143 "Synopsys EMSDP specific commands",
144 "rom unlock - Unlock non-volatile memory for writing\n"
145 "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
150 int version = readl(CREG_IP_VERSION);
152 printf("Board: ARC EM Software Development Platform v%d.%d\n",
153 (version >> 16) & 0xff, version & 0xff);