board/sks-kinkel/sksimx6/sksimx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <net.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/video.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc_imx.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <spl.h>
  23 #include <netdev.h>
  24 #include <miiphy.h>
  25 #include <micrel.h>
  26
  27 #include <common.h>
  28 #include <malloc.h>
  29 #include <fuse.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  38         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  39         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  43         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  44
  45 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  46                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 static iomux_v3_cfg_t const uart1_pads[] = {
  49         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  50         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  51 };
  52
  53 static iomux_v3_cfg_t const gpios_pads[] = {
  54         IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  55 };
  56
  57 static iomux_v3_cfg_t const usdhc2_pads[] = {
  58         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  65 };
  66
  67 static iomux_v3_cfg_t const enet_pads[] = {
  68         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
  81                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  83                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  85                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87 };
  88
  89 iomux_v3_cfg_t const enet_pads1[] = {
  90         /* pin 35 - 1 (PHY_AD2) on reset */
  91         IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         /* pin 32 - 1 - (MODE0) all */
  93         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         /* pin 31 - 1 - (MODE1) all */
  95         IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         /* pin 28 - 1 - (MODE2) all */
  97         IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98         /* pin 27 - 1 - (MODE3) all */
  99         IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 100         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 101         IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 102         /* pin 42 PHY nRST */
 103         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 104 };
 105
 106 static int mx6_rgmii_rework(struct phy_device *phydev)
 107 {
 108
 109         /* min rx data delay */
 110         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
 111                                    0x0);
 112         /* min tx data delay */
 113         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
 114                                    0x0);
 115         /* max rx/tx clock delay, min rx/tx control */
 116         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
 117                                    0xf0f0);
 118
 119         return 0;
 120 }
 121
 122 int board_phy_config(struct phy_device *phydev)
 123 {
 124         mx6_rgmii_rework(phydev);
 125
 126         if (phydev->drv->config)
 127                 return phydev->drv->config(phydev);
 128
 129         return 0;
 130 }
 131
 132 #define ENET_NRST IMX_GPIO_NR(1, 25)
 133
 134 void setup_iomux_enet(void)
 135 {
 136         SETUP_IOMUX_PADS(enet_pads);
 137
 138 }
 139
 140 int board_eth_init(bd_t *bis)
 141 {
 142         uint32_t base = IMX_FEC_BASE;
 143         struct mii_dev *bus = NULL;
 144         struct phy_device *phydev = NULL;
 145         int ret;
 146
 147         setup_iomux_enet();
 148
 149         bus = fec_get_miibus(base, -1);
 150         if (!bus)
 151                 return -EINVAL;
 152         /* scan phy */
 153         phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
 154                                         PHY_INTERFACE_MODE_RGMII);
 155
 156         if (!phydev) {
 157                 ret = -EINVAL;
 158                 goto free_bus;
 159         }
 160         ret  = fec_probe(bis, -1, base, bus, phydev);
 161         if (ret)
 162                 goto free_phydev;
 163
 164         return 0;
 165
 166 free_phydev:
 167         free(phydev);
 168 free_bus:
 169         free(bus);
 170         return ret;
 171 }
 172
 173 int board_early_init_f(void)
 174 {
 175         SETUP_IOMUX_PADS(uart1_pads);
 176
 177         return 0;
 178 }
 179
 180 int board_init(void)
 181 {
 182         /* Address of boot parameters */
 183         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 184
 185         /* Take in reset the ATMega processor */
 186         SETUP_IOMUX_PADS(gpios_pads);
 187         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 188
 189         return 0;
 190 }
 191
 192 int dram_init(void)
 193 {
 194         gd->ram_size = imx_ddr_size();
 195
 196         return 0;
 197 }
 198
 199 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 200         {USDHC2_BASE_ADDR, 0},
 201 };
 202
 203 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 0)
 204 int board_mmc_getcd(struct mmc *mmc)
 205 {
 206         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 207         int ret = 0;
 208
 209         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 210                 ret = 1;
 211
 212         return ret;
 213 }
 214
 215 int board_mmc_init(bd_t *bis)
 216 {
 217         int ret;
 218
 219         SETUP_IOMUX_PADS(usdhc2_pads);
 220         gpio_direction_input(USDHC2_CD_GPIO);
 221         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 222         usdhc_cfg[0].max_bus_width = 4;
 223
 224         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 225         if (ret) {
 226                 printf("Warning: failed to initialize mmc dev \n");
 227                 return ret;
 228         }
 229
 230         return 0;
 231 }
 232
 233 #if defined(CONFIG_SPL_BUILD)
 234 #include <asm/arch/mx6-ddr.h>
 235
 236 /*
 237  * Driving strength:
 238  *   0x30 == 40 Ohm
 239  *   0x28 == 48 Ohm
 240  */
 241 #define IMX6SDL_DRIVE_STRENGTH  0x230
 242
 243
 244 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 245 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 246         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 247         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 248         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 249         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 250         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 251         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 252         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 253         .dram_sdba2 = 0x00000000,
 254         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 255         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 256         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 257         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 258         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 259         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 260         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 261         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 262         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 263         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 264         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 265         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 266         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 267         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 268         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 269         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 270         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 271         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 272 };
 273
 274 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 275 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 276         .grp_ddr_type = 0x000c0000,
 277         .grp_ddrmode_ctl = 0x00020000,
 278         .grp_ddrpke = 0x00000000,
 279         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 280         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 281         .grp_ddrmode = 0x00020000,
 282         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 283         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 284         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 285         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 286         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 287         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 288         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 289         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 290 };
 291
 292 /* MT41K128M16JT-125 */
 293 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 294         /* quad = 1066, duallite = 800 */
 295         .mem_speed = 1066,
 296         .density = 2,
 297         .width = 16,
 298         .banks = 8,
 299         .rowaddr = 14,
 300         .coladdr = 10,
 301         .pagesz = 2,
 302         .trcd = 1375,
 303         .trcmin = 4875,
 304         .trasmin = 3500,
 305         .SRT = 0,
 306 };
 307
 308 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 309         .p0_mpwldectrl0 = 0x0043004E,
 310         .p0_mpwldectrl1 = 0x003D003F,
 311         .p1_mpwldectrl0 = 0x00230021,
 312         .p1_mpwldectrl1 = 0x0028003E,
 313         .p0_mpdgctrl0 = 0x42580250,
 314         .p0_mpdgctrl1 = 0x0238023C,
 315         .p1_mpdgctrl0 = 0x422C0238,
 316         .p1_mpdgctrl1 = 0x02180228,
 317         .p0_mprddlctl = 0x44464A46,
 318         .p1_mprddlctl = 0x44464A42,
 319         .p0_mpwrdlctl = 0x36343236,
 320         .p1_mpwrdlctl = 0x36343230,
 321 };
 322
 323 /* DDR 64bit 1GB */
 324 static struct mx6_ddr_sysinfo mem_qdl = {
 325         .dsize = 2,
 326         .cs1_mirror = 0,
 327         /* config for full 4GB range so that get_mem_size() works */
 328         .cs_density = 32,
 329         .ncs = 1,
 330         .bi_on = 1,
 331         .rtt_nom = 1,
 332         .rtt_wr = 1,
 333         .ralat = 5,
 334         .walat = 0,
 335         .mif3_mode = 3,
 336         .rst_to_cke = 0x23,
 337         .sde_to_rst = 0x10,
 338         .refsel = 1,    /* Refresh cycles at 32KHz */
 339         .refr = 7,      /* 8 refresh commands per refresh cycle */
 340 };
 341
 342 static void ccgr_init(void)
 343 {
 344         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 345
 346         /* set the default clock gate to save power */
 347         writel(0x00C03F3F, &ccm->CCGR0);
 348         writel(0x0030FC03, &ccm->CCGR1);
 349         writel(0x0FFFC000, &ccm->CCGR2);
 350         writel(0x3FF00000, &ccm->CCGR3);
 351         writel(0x00FFF300, &ccm->CCGR4);
 352         writel(0xFFFFFFFF, &ccm->CCGR5);
 353         writel(0x000003FF, &ccm->CCGR6);
 354 }
 355
 356 static void spl_dram_init(void)
 357 {
 358         if (is_cpu_type(MXC_CPU_MX6DL)) {
 359                 mt41k128m16jt_125.mem_speed = 800;
 360                 mem_qdl.rtt_nom = 1;
 361                 mem_qdl.rtt_wr = 1;
 362
 363                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 364                 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
 365         } else {
 366                 printf("Wrong CPU for this board\n");
 367                 return;
 368         }
 369
 370         udelay(100);
 371
 372 #ifdef CONFIG_MX6_DDRCAL
 373
 374         /* Perform DDR DRAM calibration */
 375         mmdc_do_write_level_calibration(&mem_qdl);
 376         mmdc_do_dqs_calibration(&mem_qdl);
 377 #endif
 378 }
 379
 380 static void check_bootcfg(void)
 381 {
 382         u32 val5, val6;
 383
 384         fuse_sense(0, 5, &val5);
 385         fuse_sense(0, 6, &val6);
 386         /* Check if boot from MMC */
 387         if (val6 & 0x10) {
 388                 puts("BT_FUSE_SEL already fused, will do nothing\n");
 389                 return;
 390         }
 391         fuse_prog(0, 5, 0x00000840);
 392         /* BT_FUSE_SEL */
 393         fuse_prog(0, 6, 0x00000010);
 394
 395         do_reset(NULL, 0, 0, NULL);
 396 }
 397
 398 void board_init_f(ulong dummy)
 399 {
 400         ccgr_init();
 401
 402         /* setup AIPS and disable watchdog */
 403         arch_cpu_init();
 404
 405         gpr_init();
 406
 407         /* iomux */
 408         board_early_init_f();
 409
 410         /* setup GP timer */
 411         timer_init();
 412
 413         /* UART clocks enabled and gd valid - init serial console */
 414         preloader_console_init();
 415
 416         /* DDR initialization */
 417         spl_dram_init();
 418
 419         /* Set fuses for new boards and reboot if not set */
 420         check_bootcfg();
 421
 422         /* Clear the BSS. */
 423         memset(__bss_start, 0, __bss_end - __bss_start);
 424
 425         /* load/boot image from boot device */
 426         board_init_r(NULL, 0);
 427 }
 428 #endif