board/silica/pengwyn/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <net.h>
  11 #include <serial.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/ddr_defs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <i2c.h>
  18 #include <phy.h>
  19 #include <cpsw.h>
  20 #include "board.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  25
  26 #if defined(CONFIG_SPL_BUILD)
  27
  28 /* DDR3 RAM timings */
  29 static const struct ddr_data ddr3_data = {
  30         .datardsratio0 = MT41K128MJT187E_RD_DQS,
  31         .datawdsratio0 = MT41K128MJT187E_WR_DQS,
  32         .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
  33         .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
  34 };
  35
  36 static const struct cmd_control ddr3_cmd_ctrl_data = {
  37         .cmd0csratio = MT41K128MJT187E_RATIO,
  38         .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  39         .cmd1csratio = MT41K128MJT187E_RATIO,
  40         .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  41         .cmd2csratio = MT41K128MJT187E_RATIO,
  42         .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  43 };
  44
  45 static struct emif_regs ddr3_emif_reg_data = {
  46         .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
  47         .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
  48         .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
  49         .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
  50         .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
  51         .zq_config = MT41K128MJT187E_ZQ_CFG,
  52         .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
  53                                 PHY_EN_DYN_PWRDN,
  54 };
  55
  56 const struct ctrl_ioregs ddr3_ioregs = {
  57         .cm0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  58         .cm1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  59         .cm2ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  60         .dt0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  61         .dt1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  62 };
  63
  64 #ifdef CONFIG_SPL_OS_BOOT
  65 int spl_start_uboot(void)
  66 {
  67         /* break into full u-boot on 'c' */
  68         return serial_tstc() && serial_getc() == 'c';
  69 }
  70 #endif
  71
  72 #define OSC     (V_OSCK/1000000)
  73 const struct dpll_params dpll_ddr_266 = {
  74                 266, OSC-1, 1, -1, -1, -1, -1};
  75 const struct dpll_params dpll_ddr_303 = {
  76                 303, OSC-1, 1, -1, -1, -1, -1};
  77 const struct dpll_params dpll_ddr_400 = {
  78                 400, OSC-1, 1, -1, -1, -1, -1};
  79
  80 void am33xx_spl_board_init(void)
  81 {
  82         /*
  83          * The pengwyn board uses the TPS650250 PMIC  without I2C
  84          * interface and will output the following fixed voltages:
  85          * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
  86          * VLDO1=1V8 (IO) VLDO2=1V8(IO)
  87          * Vcore=1V1 is fixed, generated by TPS62231
  88          */
  89
  90         /* Get the frequency */
  91         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  92
  93         /* Set CORE Frequencies to OPP100 */
  94         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  95
  96         /* 720MHz cpu, this might change on newer board revisions */
  97         dpll_mpu_opp100.m = MPUPLL_M_720;
  98         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  99 }
 100
 101 const struct dpll_params *get_dpll_ddr_params(void)
 102 {
 103         /* future configs can return other clock settings */
 104         return &dpll_ddr_303;
 105 }
 106
 107 void set_uart_mux_conf(void)
 108 {
 109         enable_uart0_pin_mux();
 110 }
 111
 112 void set_mux_conf_regs(void)
 113 {
 114         enable_board_pin_mux();
 115 }
 116
 117 void sdram_init(void)
 118 {
 119         config_ddr(303, &ddr3_ioregs, &ddr3_data,
 120                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 121 }
 122 #endif /* if CONFIG_SPL_BUILD */
 123
 124 /*
 125  * Basic board specific setup.  Pinmux has been handled already.
 126  */
 127 int board_init(void)
 128 {
 129         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 130         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 131         gpmc_init();
 132         return 0;
 133 }
 134
 135 #ifdef CONFIG_DRIVER_TI_CPSW
 136 static void cpsw_control(int enabled)
 137 {
 138         /* VTP can be added here */
 139         return;
 140 }
 141
 142 static struct cpsw_slave_data cpsw_slaves[] = {
 143         {
 144                 .slave_reg_ofs  = 0x208,
 145                 .sliver_reg_ofs = 0xd80,
 146                 .phy_addr       = 1,
 147                 .phy_if         = PHY_INTERFACE_MODE_MII,
 148         },
 149 };
 150
 151 static struct cpsw_platform_data cpsw_data = {
 152         .mdio_base              = CPSW_MDIO_BASE,
 153         .cpsw_base              = CPSW_BASE,
 154         .mdio_div               = 0xff,
 155         .channels               = 8,
 156         .cpdma_reg_ofs          = 0x800,
 157         .slaves                 = 1,
 158         .slave_data             = cpsw_slaves,
 159         .ale_reg_ofs            = 0xd00,
 160         .ale_entries            = 1024,
 161         .host_port_reg_ofs      = 0x108,
 162         .hw_stats_reg_ofs       = 0x900,
 163         .bd_ram_ofs             = 0x2000,
 164         .mac_control            = (1 << 5),
 165         .control                = cpsw_control,
 166         .host_port_num          = 0,
 167         .version                = CPSW_CTRL_VERSION_2,
 168 };
 169
 170 int board_eth_init(bd_t *bis)
 171 {
 172         int rv, n = 0;
 173         uint8_t mac_addr[6];
 174         uint32_t mac_hi, mac_lo;
 175
 176         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 177                 printf("<ethaddr> not set. Reading from E-fuse\n");
 178                 /* try reading mac address from efuse */
 179                 mac_lo = readl(&cdev->macid0l);
 180                 mac_hi = readl(&cdev->macid0h);
 181                 mac_addr[0] = mac_hi & 0xFF;
 182                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 183                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 184                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 185                 mac_addr[4] = mac_lo & 0xFF;
 186                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 187
 188                 if (is_valid_ethaddr(mac_addr))
 189                         eth_env_set_enetaddr("ethaddr", mac_addr);
 190                 else
 191                         return n;
 192         }
 193
 194         writel(MII_MODE_ENABLE, &cdev->miisel);
 195
 196         rv = cpsw_register(&cpsw_data);
 197         if (rv < 0)
 198                 printf("Error %d registering CPSW switch\n", rv);
 199         else
 200                 n += rv;
 201         return n;
 202 }
 203 #endif /* if CONFIG_DRIVER_TI_CPSW */