2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/mipi_dsim.h>
18 #include <asm/arch/watchdog.h>
19 #include <asm/arch/power.h>
20 #include <power/pmic.h>
21 #include <usb/dwc2_udc.h>
22 #include <power/max8997_pmic.h>
23 #include <power/max8997_muic.h>
24 #include <power/battery.h>
25 #include <power/max17042_fg.h>
26 #include <power/pmic.h>
29 #include <usb_mass_storage.h>
33 unsigned int board_rev;
35 #ifdef CONFIG_REVISION_TAG
36 u32 get_board_rev(void)
42 static void check_hw_revision(void);
43 struct dwc2_plat_otg_data s5pc210_otg_data;
48 printf("HW Revision:\t0x%x\n", board_rev);
53 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
54 static void trats_low_power_mode(void)
56 struct exynos4_clock *clk =
57 (struct exynos4_clock *)samsung_get_base_clock();
58 struct exynos4_power *pwr =
59 (struct exynos4_power *)samsung_get_base_power();
61 /* Power down CORE1 */
62 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
63 writel(0x0, &pwr->arm_core1_configuration);
65 /* Change the APLL frequency */
66 /* ENABLE (1 enable) | LOCKED (1 locked) */
68 /* FSEL | MDIV | PDIV | SDIV */
69 /* [27] | [25:16] | [13:8] | [2:0] */
70 writel(0xa0c80604, &clk->apll_con0);
72 /* Change CPU0 clock divider */
73 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
74 /* [30:28] | [26:24] | [22:20] | [18:16] */
75 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
76 /* [14:12] | [10:8] | [6:4] | [2:0] */
77 writel(0x00000100, &clk->div_cpu0);
79 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
80 while (readl(&clk->div_stat_cpu0) & 0x1111111)
83 /* Change clock divider ratio for DMC */
84 /* DMCP_RATIO | DMCD_RATIO */
85 /* [22:20] | [18:16] */
86 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
87 /* [14:12] | [10:8] | [6:4] | [2:0] */
88 writel(0x13113117, &clk->div_dmc0);
90 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
91 while (readl(&clk->div_stat_dmc0) & 0x11111111)
94 /* Turn off unnecessary power domains */
95 writel(0x0, &pwr->xxti_configuration); /* XXTI */
96 writel(0x0, &pwr->cam_configuration); /* CAM */
97 writel(0x0, &pwr->tv_configuration); /* TV */
98 writel(0x0, &pwr->mfc_configuration); /* MFC */
99 writel(0x0, &pwr->g3d_configuration); /* G3D */
100 writel(0x0, &pwr->gps_configuration); /* GPS */
101 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
103 /* Turn off unnecessary clocks */
104 writel(0x0, &clk->gate_ip_cam); /* CAM */
105 writel(0x0, &clk->gate_ip_tv); /* TV */
106 writel(0x0, &clk->gate_ip_mfc); /* MFC */
107 writel(0x0, &clk->gate_ip_g3d); /* G3D */
108 writel(0x0, &clk->gate_ip_image); /* IMAGE */
109 writel(0x0, &clk->gate_ip_gps); /* GPS */
113 int exynos_power_init(void)
115 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
117 struct power_battery *pb;
118 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
121 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
122 * to logical I2C adapter 0
124 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
125 * to logical I2C adapter 1
127 ret = power_fg_init(I2C_9);
128 ret |= power_muic_init(I2C_5);
129 ret |= power_bat_init(0);
133 p_fg = pmic_get("MAX17042_FG");
135 puts("MAX17042_FG: Not found\n");
139 p_chrg = pmic_get("MAX8997_PMIC");
141 puts("MAX8997_PMIC: Not found\n");
145 p_muic = pmic_get("MAX8997_MUIC");
147 puts("MAX8997_MUIC: Not found\n");
151 p_bat = pmic_get("BAT_TRATS");
153 puts("BAT_TRATS: Not found\n");
157 p_fg->parent = p_bat;
158 p_chrg->parent = p_bat;
159 p_muic->parent = p_bat;
161 p_bat->low_power_mode = trats_low_power_mode;
162 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
165 chrg = p_muic->chrg->chrg_type(p_muic);
166 debug("CHARGER TYPE: %d\n", chrg);
168 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
169 puts("No battery detected\n");
173 p_fg->fg->fg_battery_check(p_fg, p_bat);
175 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
176 puts("CHARGE Battery !\n");
182 static unsigned int get_hw_revision(void)
188 /* hw_rev[3:0] == GPE1[3:0] */
189 for (i = 0; i < 4; i++) {
190 int pin = i + EXYNOS4_GPIO_E10;
192 sprintf(str, "hw_rev%d", i);
193 gpio_request(pin, str);
194 gpio_cfg_pin(pin, S5P_GPIO_INPUT);
195 gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
200 for (i = 0; i < 4; i++)
201 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
203 debug("hwrev 0x%x\n", hwrev);
208 static void check_hw_revision(void)
212 hwrev = get_hw_revision();
218 #ifdef CONFIG_USB_GADGET
219 static int s5pc210_phy_control(int on)
224 ret = pmic_get("max8997-pmic", &dev);
229 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
231 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
233 puts("MAX8997 setting error!\n");
236 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
238 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
240 puts("MAX8997 setting error!\n");
243 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
245 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
247 puts("MAX8997 setting error!\n");
251 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
253 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
255 puts("MAX8997 setting error!\n");
258 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
260 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
262 puts("MAX8997 setting error!\n");
265 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
267 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
269 puts("MAX8997 setting error!\n");
278 struct dwc2_plat_otg_data s5pc210_otg_data = {
279 .phy_control = s5pc210_phy_control,
280 .regs_phy = EXYNOS4_USBPHY_BASE,
281 .regs_otg = EXYNOS4_USBOTG_BASE,
282 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
283 .usb_flags = PHY0_SLEEP,
286 int board_usb_init(int index, enum usb_init_type init)
288 debug("USB_udc_probe\n");
289 return dwc2_udc_probe(&s5pc210_otg_data);
292 int g_dnl_board_usb_cable_connected(void)
294 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
295 struct pmic *muic = pmic_get("MAX8997_MUIC");
299 return !!muic->chrg->chrg_type(muic);
307 static void pmic_reset(void)
309 gpio_direction_output(EXYNOS4_GPIO_X07, 1);
310 gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
313 static void board_clock_init(void)
315 struct exynos4_clock *clk =
316 (struct exynos4_clock *)samsung_get_base_clock();
318 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
319 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
320 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
321 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
323 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
324 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
325 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
326 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
327 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
328 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
329 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
330 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
331 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
332 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
333 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
334 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
336 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
337 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
338 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
339 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
340 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
341 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
342 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
343 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
344 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
345 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
346 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
347 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
349 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
350 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
351 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
352 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
353 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
354 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
355 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
356 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
357 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
358 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
359 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
360 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
363 static void board_power_init(void)
365 struct exynos4_power *pwr =
366 (struct exynos4_power *)samsung_get_base_power();
369 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
372 writel(0, (unsigned int)&pwr->cam_configuration);
373 writel(0, (unsigned int)&pwr->tv_configuration);
374 writel(0, (unsigned int)&pwr->mfc_configuration);
375 writel(0, (unsigned int)&pwr->g3d_configuration);
376 writel(0, (unsigned int)&pwr->lcd1_configuration);
377 writel(0, (unsigned int)&pwr->gps_configuration);
378 writel(0, (unsigned int)&pwr->gps_alive_configuration);
380 /* It is necessary to power down core 1 */
381 /* to successfully boot CPU1 in kernel */
382 writel(0, (unsigned int)&pwr->arm_core1_configuration);
385 static void exynos_uart_init(void)
387 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
388 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
389 gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
390 gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
393 int exynos_early_init_f(void)
404 void exynos_reset_lcd(void)
406 gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
407 gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
409 gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
411 gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
416 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
418 struct pmic *p = pmic_get("MAX8997_PMIC");
425 /* LDO15 voltage: 2.2v */
426 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
427 /* LDO13 voltage: 3.0v */
428 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
431 puts("MAX8997 LDO setting error!\n");
440 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
442 struct pmic *p = pmic_get("MAX8997_PMIC");
449 /* LDO3 voltage: 1.1v */
450 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
451 /* LDO4 voltage: 1.8v */
452 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
455 puts("MAX8997 LDO setting error!\n");
463 void exynos_lcd_misc_init(vidinfo_t *vid)
466 get_tizen_logo_info(vid);
468 #ifdef CONFIG_S6E8AX0
470 env_set("lcdinfo", "lcd=s6e8ax0");