2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/bitops.h>
31 #include <asm/processor.h>
32 #include <asm/mpc512x.h>
33 #include <fdt_support.h>
35 #ifdef CONFIG_MISC_INIT_R
39 #include <jffs2/load_kernel.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 extern flash_info_t flash_info[];
45 ulong flash_get_size (phys_addr_t base, int banknum);
48 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
49 CLOCK_SCCR1_LPC_EN | \
50 CLOCK_SCCR1_NFC_EN | \
51 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
52 CLOCK_SCCR1_PSCFIFO_EN | \
53 CLOCK_SCCR1_DDR_EN | \
54 CLOCK_SCCR1_FEC_EN | \
57 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
58 CLOCK_SCCR2_SPDIF_EN | \
59 CLOCK_SCCR2_DIU_EN | \
62 int board_early_init_f(void)
64 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
67 * Initialize Local Window for FLASH-Bank1 access (CS1)
69 out_be32(&im->sysconf.lpcs1aw,
70 CSAW_START(CONFIG_SYS_FLASH1_BASE) |
71 CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
73 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
76 * Local Window for MRAM access (CS2)
78 out_be32(&im->sysconf.lpcs2aw,
79 CSAW_START(CONFIG_SYS_MRAM_BASE) |
80 CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
82 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
84 sync_law(&im->sysconf.lpcs2aw);
87 * Configure Flash Speed
89 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
90 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
95 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
96 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
97 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
98 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
104 sdram_conf_t mddrc_config[] = {
106 (512 << 20), /* 512 MB RAM configuration */
108 CONFIG_SYS_MDDRC_SYS_CFG,
109 CONFIG_SYS_MDDRC_TIME_CFG0,
110 CONFIG_SYS_MDDRC_TIME_CFG1,
111 CONFIG_SYS_MDDRC_TIME_CFG2
115 (128 << 20), /* 128 MB RAM configuration */
117 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
118 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
119 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
120 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
125 phys_size_t initdram (int board_type)
129 u32 pdm360ng_init_seq[] = {
130 CONFIG_SYS_DDRCMD_NOP,
131 CONFIG_SYS_DDRCMD_NOP,
132 CONFIG_SYS_DDRCMD_NOP,
133 CONFIG_SYS_DDRCMD_NOP,
134 CONFIG_SYS_DDRCMD_NOP,
135 CONFIG_SYS_DDRCMD_NOP,
136 CONFIG_SYS_DDRCMD_NOP,
137 CONFIG_SYS_DDRCMD_NOP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_PCHG_ALL,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_RFSH,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_RFSH,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_MICRON_INIT_DEV_OP,
147 CONFIG_SYS_DDRCMD_NOP,
148 CONFIG_SYS_DDRCMD_EM2,
149 CONFIG_SYS_DDRCMD_NOP,
150 CONFIG_SYS_DDRCMD_PCHG_ALL,
151 CONFIG_SYS_DDRCMD_EM2,
152 CONFIG_SYS_DDRCMD_EM3,
153 CONFIG_SYS_DDRCMD_EN_DLL,
154 CONFIG_SYS_DDRCMD_RES_DLL,
155 CONFIG_SYS_DDRCMD_PCHG_ALL,
156 CONFIG_SYS_DDRCMD_RFSH,
157 CONFIG_SYS_DDRCMD_RFSH,
158 CONFIG_SYS_MICRON_INIT_DEV_OP,
159 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
160 CONFIG_SYS_DDRCMD_OCD_EXIT,
161 CONFIG_SYS_DDRCMD_PCHG_ALL,
162 CONFIG_SYS_DDRCMD_NOP
165 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
166 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
167 ARRAY_SIZE(pdm360ng_init_seq));
168 if (msize == mddrc_config[i].size)
175 #if defined(CONFIG_SERIAL_MULTI)
176 static int set_lcd_brightness(char *);
179 int misc_init_r(void)
181 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
184 * Re-configure flash setup using auto-detected info
186 if (flash_info[1].size > 0) {
187 out_be32(&im->sysconf.lpcs1aw,
188 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
189 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
190 flash_info[1].size));
191 sync_law(&im->sysconf.lpcs1aw);
193 * Re-check to get correct base address
195 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
198 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
199 sync_law(&im->sysconf.lpcs1aw);
202 out_be32(&im->sysconf.lpcs0aw,
203 CSAW_START(gd->bd->bi_flashstart) |
204 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
205 sync_law(&im->sysconf.lpcs0aw);
208 * Re-check to get correct base address
210 flash_get_size (gd->bd->bi_flashstart, 0);
213 * Re-do flash protection upon new addresses
215 flash_protect (FLAG_PROTECT_CLEAR,
216 gd->bd->bi_flashstart, 0xffffffff,
219 /* Monitor protection ON by default */
220 flash_protect (FLAG_PROTECT_SET,
221 CONFIG_SYS_MONITOR_BASE,
222 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
225 /* Environment protection ON by default */
226 flash_protect (FLAG_PROTECT_SET,
228 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
231 #ifdef CONFIG_ENV_ADDR_REDUND
232 /* Redundant environment protection ON by default */
233 flash_protect (FLAG_PROTECT_SET,
234 CONFIG_ENV_ADDR_REDUND,
235 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
239 #ifdef CONFIG_FSL_DIU_FB
240 #if defined(CONFIG_SERIAL_MULTI)
241 set_lcd_brightness(0);
243 /* Switch LCD-Backlight and LVDS-Interface on */
244 setbits_be32(&im->gpio.gpdir, 0x01040000);
245 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
248 #if defined(CONFIG_HARD_I2C)
249 if (!getenv("ethaddr")) {
251 uchar ifm_oui[3] = { 0, 2, 1, };
254 /* I2C-0 for on-board eeprom */
255 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
257 /* Read ethaddr from EEPROM */
258 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
259 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
261 printf("Error: Unable to read MAC from I2C"
262 " EEPROM at address %02X:%02X\n",
263 CONFIG_SYS_I2C_EEPROM_ADDR,
264 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
269 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
270 printf("Illegal MAC address in EEPROM: %pM\n", buf);
274 eth_setenv_enetaddr("ethaddr", buf);
276 #endif /* defined(CONFIG_HARD_I2C) */
281 static iopin_t ioregs_init[] = {
284 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
285 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
286 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
290 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
291 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
292 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
296 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
297 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
298 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
302 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
303 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
304 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
306 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
307 /* DIU_LD22-DIU_LD23 */
309 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
310 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
311 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
313 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
314 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
316 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
317 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
318 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
320 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
321 /* VIU_DATA0-VIU_DATA2 */
323 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
324 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
325 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
327 /* FUNC2=FEC_TXD_0 */
329 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
330 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
331 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
333 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
334 /* VIU_DATA3, VIU_DATA4 */
336 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
337 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
338 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
340 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
341 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
342 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
344 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
345 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
346 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
348 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
349 /* DIU_LD00-DIU_LD21 */
351 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
352 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
353 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
355 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
356 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
358 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
359 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
360 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
364 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
365 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
366 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
368 /* Sets lowest slew on 2 CAN_TX Pins*/
370 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
371 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
372 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
374 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
375 /* CAN4_TX, CAN4_RX */
377 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
378 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
379 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
381 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
384 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
385 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
386 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
388 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
389 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
391 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
392 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
393 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
395 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
396 /* FEC_RXD_3, FEC_RXD_2 */
398 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
399 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
400 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
404 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
405 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
406 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
408 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
409 /* GPIO2, GPIO20, GPIO21 */
411 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
412 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
413 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
415 /* FUNC2=VIU_PIX_CLK */
417 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
418 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
419 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
421 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
424 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
425 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
426 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
430 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
431 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
432 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
434 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
435 /* VIU_DATA5-VIU_DATA9 */
437 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
438 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
439 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
441 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
442 /* LPC_TSIZ1-LPC_TSIZ2 */
444 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
445 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
446 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
450 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
451 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
452 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
456 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
457 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
458 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
460 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
461 /* GPIO18-GPIO19, GPT7/GPIO7 */
463 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
464 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
465 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
467 /* FUNC3=GPIO0/GPT0 */
469 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
470 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
471 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
473 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
474 /* GPIO11, GPIO2, GPIO12, GPIO13 */
476 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
477 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
478 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
482 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
483 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
484 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
488 int checkboard (void)
490 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
492 puts("Board: PDM360NG\n");
494 /* initialize function mux & slew rate IO inter alia on IO Pins */
496 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
498 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
499 setbits_be32(&im->io_ctrl.io_control_gp,
500 (1 << 0) | /* GP_MUX7->GPIO7 */
501 (1 << 5)); /* GP_MUX2->GPIO2 */
503 /* configure GPIO24 (VIU_CE), output/high */
504 setbits_be32(&im->gpio.gpdir, 0x80);
505 setbits_be32(&im->gpio.gpdat, 0x80);
510 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
511 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
512 struct node_info nodes[] = {
513 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
514 { "cfi-flash", MTD_DEV_TYPE_NOR, },
518 void ft_board_setup(void *blob, bd_t *bd)
523 ft_cpu_setup(blob, bd);
524 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
525 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
526 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
529 /* Fixup NOR FLASH mapping */
530 val[i++] = 0; /* chip select number */
531 val[i++] = 0; /* always 0 */
532 val[i++] = gd->bd->bi_flashstart;
533 val[i++] = gd->bd->bi_flashsize;
535 /* Fixup MRAM mapping */
536 val[i++] = 2; /* chip select number */
537 val[i++] = 0; /* always 0 */
538 val[i++] = CONFIG_SYS_MRAM_BASE;
539 val[i++] = CONFIG_SYS_MRAM_SIZE;
541 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
542 val, i * sizeof(u32), 1);
544 printf("Unable to update localbus ranges, err=%s\n",
547 /* Fixup reg property in NOR Flash node */
549 val[i++] = 0; /* always 0 */
550 val[i++] = 0; /* start at offset 0 */
551 val[i++] = flash_info[0].size; /* size of Bank 0 */
553 /* Second Bank available? */
554 if (flash_info[1].size > 0) {
555 val[i++] = 0; /* always 0 */
556 val[i++] = flash_info[0].size; /* offset of Bank 1 */
557 val[i++] = flash_info[1].size; /* size of Bank 1 */
560 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
561 val, i * sizeof(u32), 1);
563 printf("Unable to update flash reg property, err=%s\n",
566 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
568 #if defined(CONFIG_SERIAL_MULTI)
570 * If argument is NULL, set the LCD brightness to the
571 * value from "brightness" environment variable. Set
572 * the LCD brightness to the value specified by the
573 * argument otherwise. Default brightness is zero.
575 #define MAX_BRIGHTNESS 99
576 static int set_lcd_brightness(char *brightness)
578 struct stdio_dev *cop_port;
586 val = simple_strtol(brightness, NULL, 10);
588 env = getenv("brightness");
590 val = simple_strtol(env, NULL, 10);
596 if (val > MAX_BRIGHTNESS)
597 val = MAX_BRIGHTNESS;
599 sprintf(cmd_buf, "$SB;%04d;", val);
601 len = strlen(cmd_buf);
602 for (i = 1; i <= len; i++)
605 cs = (~cs + 1) & 0xff;
606 sprintf(cmd_buf + len, "%02X\n", cs);
608 /* IO Coprocessor communication */
609 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
611 printf("Error: Can't open IO Coprocessor port.\n");
615 debug("%s: cmd: %s", __func__, cmd_buf);
616 write_port(cop_port, cmd_buf);
618 * Wait for transmission and maybe response data
619 * before closing the port.
621 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
622 memset(cmd_buf, 0, sizeof(cmd_buf));
623 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
625 printf("Error: %s\n", cmd_buf);
632 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
633 int argc, char * const argv[])
636 return cmd_usage(cmdtp);
638 return set_lcd_brightness(argv[1]);
641 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
642 "set LCD brightness",
643 "<brightness> - set LCD backlight level to <brightness>.\n"
645 #endif /* CONFIG_SERIAL_MULTI */