2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/bitops.h>
31 #include <asm/processor.h>
32 #include <asm/mpc512x.h>
33 #include <fdt_support.h>
35 #ifdef CONFIG_MISC_INIT_R
39 #include <jffs2/load_kernel.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 extern flash_info_t flash_info[];
45 ulong flash_get_size (phys_addr_t base, int banknum);
48 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
49 CLOCK_SCCR1_LPC_EN | \
50 CLOCK_SCCR1_NFC_EN | \
51 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
52 CLOCK_SCCR1_PSCFIFO_EN | \
53 CLOCK_SCCR1_DDR_EN | \
54 CLOCK_SCCR1_FEC_EN | \
57 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
58 CLOCK_SCCR2_SPDIF_EN | \
59 CLOCK_SCCR2_DIU_EN | \
62 int board_early_init_f(void)
64 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
69 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
70 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
71 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
72 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
78 sdram_conf_t mddrc_config[] = {
80 (512 << 20), /* 512 MB RAM configuration */
82 CONFIG_SYS_MDDRC_SYS_CFG,
83 CONFIG_SYS_MDDRC_TIME_CFG0,
84 CONFIG_SYS_MDDRC_TIME_CFG1,
85 CONFIG_SYS_MDDRC_TIME_CFG2
89 (128 << 20), /* 128 MB RAM configuration */
91 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
92 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
93 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
94 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
99 phys_size_t initdram (int board_type)
103 u32 pdm360ng_init_seq[] = {
104 CONFIG_SYS_DDRCMD_NOP,
105 CONFIG_SYS_DDRCMD_NOP,
106 CONFIG_SYS_DDRCMD_NOP,
107 CONFIG_SYS_DDRCMD_NOP,
108 CONFIG_SYS_DDRCMD_NOP,
109 CONFIG_SYS_DDRCMD_NOP,
110 CONFIG_SYS_DDRCMD_NOP,
111 CONFIG_SYS_DDRCMD_NOP,
112 CONFIG_SYS_DDRCMD_NOP,
113 CONFIG_SYS_DDRCMD_NOP,
114 CONFIG_SYS_DDRCMD_PCHG_ALL,
115 CONFIG_SYS_DDRCMD_NOP,
116 CONFIG_SYS_DDRCMD_RFSH,
117 CONFIG_SYS_DDRCMD_NOP,
118 CONFIG_SYS_DDRCMD_RFSH,
119 CONFIG_SYS_DDRCMD_NOP,
120 CONFIG_SYS_MICRON_INIT_DEV_OP,
121 CONFIG_SYS_DDRCMD_NOP,
122 CONFIG_SYS_DDRCMD_EM2,
123 CONFIG_SYS_DDRCMD_NOP,
124 CONFIG_SYS_DDRCMD_PCHG_ALL,
125 CONFIG_SYS_DDRCMD_EM2,
126 CONFIG_SYS_DDRCMD_EM3,
127 CONFIG_SYS_DDRCMD_EN_DLL,
128 CONFIG_SYS_DDRCMD_RES_DLL,
129 CONFIG_SYS_DDRCMD_PCHG_ALL,
130 CONFIG_SYS_DDRCMD_RFSH,
131 CONFIG_SYS_DDRCMD_RFSH,
132 CONFIG_SYS_MICRON_INIT_DEV_OP,
133 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
134 CONFIG_SYS_DDRCMD_OCD_EXIT,
135 CONFIG_SYS_DDRCMD_PCHG_ALL,
136 CONFIG_SYS_DDRCMD_NOP
139 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
140 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
141 ARRAY_SIZE(pdm360ng_init_seq));
142 if (msize == mddrc_config[i].size)
149 static int set_lcd_brightness(char *);
151 int misc_init_r(void)
153 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
156 * Re-configure flash setup using auto-detected info
158 if (flash_info[1].size > 0) {
159 out_be32(&im->sysconf.lpcs1aw,
160 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
161 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
162 flash_info[1].size));
163 sync_law(&im->sysconf.lpcs1aw);
165 * Re-check to get correct base address
167 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
170 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
171 sync_law(&im->sysconf.lpcs1aw);
174 out_be32(&im->sysconf.lpcs0aw,
175 CSAW_START(gd->bd->bi_flashstart) |
176 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
177 sync_law(&im->sysconf.lpcs0aw);
180 * Re-check to get correct base address
182 flash_get_size (gd->bd->bi_flashstart, 0);
185 * Re-do flash protection upon new addresses
187 flash_protect (FLAG_PROTECT_CLEAR,
188 gd->bd->bi_flashstart, 0xffffffff,
191 /* Monitor protection ON by default */
192 flash_protect (FLAG_PROTECT_SET,
193 CONFIG_SYS_MONITOR_BASE,
194 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
197 /* Environment protection ON by default */
198 flash_protect (FLAG_PROTECT_SET,
200 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
203 #ifdef CONFIG_ENV_ADDR_REDUND
204 /* Redundant environment protection ON by default */
205 flash_protect (FLAG_PROTECT_SET,
206 CONFIG_ENV_ADDR_REDUND,
207 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
211 #ifdef CONFIG_FSL_DIU_FB
212 set_lcd_brightness(0);
213 /* Switch LCD-Backlight and LVDS-Interface on */
214 setbits_be32(&im->gpio.gpdir, 0x01040000);
215 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
218 #if defined(CONFIG_HARD_I2C)
219 if (!getenv("ethaddr")) {
221 uchar ifm_oui[3] = { 0, 2, 1, };
224 /* I2C-0 for on-board eeprom */
225 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
227 /* Read ethaddr from EEPROM */
228 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
229 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
231 printf("Error: Unable to read MAC from I2C"
232 " EEPROM at address %02X:%02X\n",
233 CONFIG_SYS_I2C_EEPROM_ADDR,
234 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
239 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
240 printf("Illegal MAC address in EEPROM: %pM\n", buf);
244 eth_setenv_enetaddr("ethaddr", buf);
246 #endif /* defined(CONFIG_HARD_I2C) */
251 static iopin_t ioregs_init[] = {
254 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
255 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
256 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
260 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
261 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
262 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
266 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
267 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
268 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
272 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
273 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
274 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
276 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
277 /* DIU_LD22-DIU_LD23 */
279 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
280 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
281 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
283 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
284 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
286 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
287 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
288 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
290 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
291 /* VIU_DATA0-VIU_DATA2 */
293 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
294 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
295 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
297 /* FUNC2=FEC_TXD_0 */
299 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
300 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
301 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
303 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
304 /* VIU_DATA3, VIU_DATA4 */
306 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
307 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
308 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
310 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
311 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
312 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
314 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
315 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
316 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
318 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
319 /* DIU_LD00-DIU_LD21 */
321 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
322 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
323 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
325 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
326 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
328 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
329 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
330 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
334 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
335 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
336 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
338 /* Sets lowest slew on 2 CAN_TX Pins*/
340 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
341 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
342 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
344 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
345 /* CAN4_TX, CAN4_RX */
347 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
348 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
349 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
351 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
354 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
355 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
356 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
358 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
359 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
361 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
362 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
363 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
365 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
366 /* FEC_RXD_3, FEC_RXD_2 */
368 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
369 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
370 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
374 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
375 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
376 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
378 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
379 /* GPIO2, GPIO20, GPIO21 */
381 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
382 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
383 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
385 /* FUNC2=VIU_PIX_CLK */
387 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
388 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
389 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
391 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
394 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
395 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
396 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
400 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
401 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
402 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
404 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
405 /* VIU_DATA5-VIU_DATA9 */
407 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
408 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
409 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
411 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
412 /* LPC_TSIZ1-LPC_TSIZ2 */
414 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
415 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
416 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
420 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
421 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
422 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
426 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
427 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
428 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
430 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
431 /* GPIO18-GPIO19, GPT7/GPIO7 */
433 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
434 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
435 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
437 /* FUNC3=GPIO0/GPT0 */
439 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
440 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
441 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
443 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
444 /* GPIO11, GPIO2, GPIO12, GPIO13 */
446 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
447 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
448 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
452 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
453 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
454 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
458 int checkboard (void)
460 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
462 puts("Board: PDM360NG\n");
464 /* initialize function mux & slew rate IO inter alia on IO Pins */
466 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
468 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
469 setbits_be32(&im->io_ctrl.io_control_gp,
470 (1 << 0) | /* GP_MUX7->GPIO7 */
471 (1 << 5)); /* GP_MUX2->GPIO2 */
473 /* configure GPIO24 (VIU_CE), output/high */
474 setbits_be32(&im->gpio.gpdir, 0x80);
475 setbits_be32(&im->gpio.gpdat, 0x80);
480 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
481 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
482 struct node_info nodes[] = {
483 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
484 { "cfi-flash", MTD_DEV_TYPE_NOR, },
488 #if defined(CONFIG_VIDEO)
490 * EDID block has been generated using Phoenix EDID Designer 1.3.
491 * This tool creates a text file containing:
494 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
495 * ------------------------------------------------
496 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
497 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
498 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
499 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
500 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
501 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
502 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
503 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
505 * Then this data has been manually converted to the char
508 static unsigned char edid_buf[128] = {
509 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
510 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
511 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
512 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
513 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
514 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
515 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
516 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
517 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
518 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
519 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
520 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
521 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
522 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
523 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
524 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
528 void ft_board_setup(void *blob, bd_t *bd)
533 ft_cpu_setup(blob, bd);
534 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
535 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
536 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
538 #if defined(CONFIG_VIDEO)
539 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
542 /* Fixup NOR FLASH mapping */
543 val[i++] = 0; /* chip select number */
544 val[i++] = 0; /* always 0 */
545 val[i++] = gd->bd->bi_flashstart;
546 val[i++] = gd->bd->bi_flashsize;
548 /* Fixup MRAM mapping */
549 val[i++] = 2; /* chip select number */
550 val[i++] = 0; /* always 0 */
551 val[i++] = CONFIG_SYS_MRAM_BASE;
552 val[i++] = CONFIG_SYS_MRAM_SIZE;
554 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
555 val, i * sizeof(u32), 1);
557 printf("Unable to update localbus ranges, err=%s\n",
560 /* Fixup reg property in NOR Flash node */
562 val[i++] = 0; /* always 0 */
563 val[i++] = 0; /* start at offset 0 */
564 val[i++] = flash_info[0].size; /* size of Bank 0 */
566 /* Second Bank available? */
567 if (flash_info[1].size > 0) {
568 val[i++] = 0; /* always 0 */
569 val[i++] = flash_info[0].size; /* offset of Bank 1 */
570 val[i++] = flash_info[1].size; /* size of Bank 1 */
573 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
574 val, i * sizeof(u32), 1);
576 printf("Unable to update flash reg property, err=%s\n",
579 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
582 * If argument is NULL, set the LCD brightness to the
583 * value from "brightness" environment variable. Set
584 * the LCD brightness to the value specified by the
585 * argument otherwise. Default brightness is zero.
587 #define MAX_BRIGHTNESS 99
588 static int set_lcd_brightness(char *brightness)
590 struct stdio_dev *cop_port;
598 val = simple_strtol(brightness, NULL, 10);
600 env = getenv("brightness");
602 val = simple_strtol(env, NULL, 10);
608 if (val > MAX_BRIGHTNESS)
609 val = MAX_BRIGHTNESS;
611 sprintf(cmd_buf, "$SB;%04d;", val);
613 len = strlen(cmd_buf);
614 for (i = 1; i <= len; i++)
617 cs = (~cs + 1) & 0xff;
618 sprintf(cmd_buf + len, "%02X\n", cs);
620 /* IO Coprocessor communication */
621 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
623 printf("Error: Can't open IO Coprocessor port.\n");
627 debug("%s: cmd: %s", __func__, cmd_buf);
628 write_port(cop_port, cmd_buf);
630 * Wait for transmission and maybe response data
631 * before closing the port.
633 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
634 memset(cmd_buf, 0, sizeof(cmd_buf));
635 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
637 printf("Error: %s\n", cmd_buf);
644 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
645 int argc, char * const argv[])
648 return cmd_usage(cmdtp);
650 return set_lcd_brightness(argv[1]);
653 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
654 "set LCD brightness",
655 "<brightness> - set LCD backlight level to <brightness>.\n"