2 * Maintainer : Steve Sakoman <steve@sakoman.com>
4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Mohammed Khasim <khasim@ti.com>
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
10 * (C) Copyright 2004-2008
11 * Texas Instruments, <www.ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mux.h>
36 #include <asm/arch/mem.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/gpio.h>
39 #include <asm/mach-types.h>
42 #if defined(CONFIG_CMD_NET)
43 static void setup_net_chip(void);
46 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */
47 static const u32 gpmc_lan_config[] = {
48 NET_LAN9221_GPMC_CONFIG1,
49 NET_LAN9221_GPMC_CONFIG2,
50 NET_LAN9221_GPMC_CONFIG3,
51 NET_LAN9221_GPMC_CONFIG4,
52 NET_LAN9221_GPMC_CONFIG5,
53 NET_LAN9221_GPMC_CONFIG6,
54 /*CONFIG7- computed as params */
59 * Description: Early hardware init.
63 DECLARE_GLOBAL_DATA_PTR;
65 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
66 /* board id for Linux */
67 gd->bd->bi_arch_number = MACH_TYPE_OVERO;
69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
75 * Routine: get_board_revision
76 * Description: Returns the board revision
78 int get_board_revision(void)
82 if (!omap_request_gpio(112) &&
83 !omap_request_gpio(113) &&
84 !omap_request_gpio(115)) {
86 omap_set_gpio_direction(112, 1);
87 omap_set_gpio_direction(113, 1);
88 omap_set_gpio_direction(115, 1);
90 revision = omap_get_gpio_datain(115) << 2 |
91 omap_get_gpio_datain(113) << 1 |
92 omap_get_gpio_datain(112);
98 printf("Error: unable to acquire board revision GPIOs\n");
106 * Routine: misc_init_r
107 * Description: Configure board specific parts
109 int misc_init_r(void)
111 twl4030_power_init();
112 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
114 #if defined(CONFIG_CMD_NET)
118 printf("Board revision: %d\n", get_board_revision());
125 * Routine: set_muxconf_regs
126 * Description: Setting up the configuration Mux registers specific to the
127 * hardware. Many pins need to be moved from protect to primary
130 void set_muxconf_regs(void)
135 #if defined(CONFIG_CMD_NET)
137 * Routine: setup_net_chip
138 * Description: Setting up the configuration GPMC registers specific to the
141 static void setup_net_chip(void)
143 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
146 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
149 /* second lan chip */
150 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
153 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
154 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
155 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
156 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
157 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
158 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
159 &ctrl_base->gpmc_nadv_ale);
161 /* Make GPIO 64 as output pin and send a magic pulse through it */
162 if (!omap_request_gpio(64)) {
163 omap_set_gpio_direction(64, 0);
164 omap_set_gpio_dataout(64, 1);
166 omap_set_gpio_dataout(64, 0);
168 omap_set_gpio_dataout(64, 1);
173 int board_eth_init(bd_t *bis)
176 #ifdef CONFIG_SMC911X
177 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);