3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
29 #include <asm/iopin_8260.h>
32 /*-----------------------------------------------------------------------
33 * Board Special Commands: FPGA load/store, EEPROM erase
36 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
38 #define LOAD_SUCCESS 0
39 #define LOAD_FAIL_NOCONF 1
40 #define LOAD_FAIL_NOINIT 2
41 #define LOAD_FAIL_NODONE 3
43 #define STORE_SUCCESS 0
46 * Programming the Hymod FPGAs
48 * The 8260 io port config table is set up so that the INIT pin is
49 * held Low (Open Drain output 0) - this will delay the automatic
50 * Power-On config until INIT is released (by making it an input).
52 * If the FPGA has been programmed before, then the assertion of PROGRAM
53 * will initiate configuration (i.e. it begins clearing the RAM).
55 * When the FPGA is ready to receive configuration data (either after
56 * releasing INIT after Power-On, or after asserting PROGRAM), it will
59 * Notes from Paul Dunn:
61 * 1. program pin should be forced low for >= 300ns
62 * (about 20 bus clock cycles minimum).
64 * 2. then wait for init to go high, which signals
65 * that the FPGA has cleared its internal memory
66 * and is ready to load
68 * 3. perform load writes of entire config file
70 * 4. wait for done to go high, which should be
71 * within a few bus clock cycles. If done has not
72 * gone high after reasonable period, then load
73 * has not worked (wait several ms?)
77 fpga_load (int mezz, uchar *addr, ulong size)
79 DECLARE_GLOBAL_DATA_PTR;
81 hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
84 volatile uchar *fpgabase;
86 uchar *eaddr = addr + size;
90 fp = &cp->mezz.xlx[0];
92 fp = &cp->main.xlx[0];
94 if (!fp->mmap.prog.exists)
95 return (LOAD_FAIL_NOCONF);
97 fpgabase = (uchar *)fp->mmap.prog.base;
100 /* set enable HIGH if required */
101 if (fpgaio->enable_pin.flag)
102 iopin_set_high (&fpgaio->enable_pin);
104 /* ensure INIT is released (set it to be an input) */
105 iopin_set_in (&fpgaio->init_pin);
107 /* toggle PROG Low then High (will already be Low after Power-On) */
108 iopin_set_low (&fpgaio->prog_pin);
109 udelay (1); /* minimum 300ns - 1usec should do it */
110 iopin_set_high (&fpgaio->prog_pin);
112 /* wait for INIT High */
114 while (!iopin_is_high (&fpgaio->init_pin))
115 if (++cnt == 10000000) {
116 result = LOAD_FAIL_NOINIT;
120 /* write configuration data */
124 /* wait for DONE High */
126 while (!iopin_is_high (&fpgaio->done_pin))
127 if (++cnt == 100000000) {
128 result = LOAD_FAIL_NODONE;
133 result = LOAD_SUCCESS;
137 if (fpgaio->enable_pin.flag)
138 iopin_set_low (&fpgaio->enable_pin);
143 /* ------------------------------------------------------------------------- */
145 do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
147 uchar *addr, *save_addr;
149 int mezz, arg, result;
158 if (strcmp (argv[1], "info") == 0) {
159 printf ("\nHymod FPGA Info...\n");
160 printf ("\t\t\t\tAddress\t\tSize\n");
161 printf ("\tMain Configuration:\t0x%08x\t%d\n",
162 FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
163 printf ("\tMain Register:\t\t0x%08x\t%d\n",
164 FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
165 printf ("\tMain Port:\t\t0x%08x\t%d\n",
166 FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
167 printf ("\tMezz Configuration:\t0x%08x\t%d\n",
168 FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
174 if (strcmp (argv[1], "store") == 0) {
175 addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
179 /* fpga readback unimplemented */
180 while (more readback data)
182 result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
184 result = STORE_SUCCESS;
187 if (result == STORE_SUCCESS) {
188 printf ("SUCCEEDED (%d bytes)\n",
192 printf ("FAILED (%d bytes)\n",
199 if (strcmp (argv[1], "tftp") == 0) {
200 copy_filename (BootFile, argv[2], sizeof (BootFile));
201 load_addr = simple_strtoul (argv[3], NULL, 16);
202 NetBootFileXferSize = 0;
204 if (NetLoop (TFTP) <= 0) {
205 printf ("tftp transfer failed - aborting "
210 if (NetBootFileXferSize == 0) {
211 printf ("can't determine file size - "
212 "aborting fpga load\n");
216 printf ("File transfer succeeded - "
217 "beginning fpga load...");
219 result = fpga_load (0, (uchar *) load_addr,
220 NetBootFileXferSize);
222 if (result == LOAD_SUCCESS) {
223 printf ("SUCCEEDED\n");
225 } else if (result == LOAD_FAIL_NOCONF)
226 printf ("FAILED (no CONF)\n");
227 else if (result == LOAD_FAIL_NOINIT)
228 printf ("FAILED (no INIT)\n");
230 printf ("FAILED (no DONE)\n");
234 /* fall through ... */
237 if (strcmp (argv[1], "load") == 0) {
239 if (strcmp (argv[2], "main") == 0)
241 else if (strcmp (argv[2], "mezz") == 0)
244 printf ("FPGA type must be either "
245 "`main' or `mezz'\n");
254 addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
255 size = (ulong) simple_strtoul (argv[arg], NULL, 16);
257 result = fpga_load (mezz, addr, size);
259 if (result == LOAD_SUCCESS) {
260 printf ("SUCCEEDED\n");
262 } else if (result == LOAD_FAIL_NOCONF)
263 printf ("FAILED (no CONF)\n");
264 else if (result == LOAD_FAIL_NOINIT)
265 printf ("FAILED (no INIT)\n");
267 printf ("FAILED (no DONE)\n");
276 printf ("Usage:\n%s\n", cmdtp->usage);
280 /* ------------------------------------------------------------------------- */
282 do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
284 uchar data[HYMOD_EEPROM_SIZE];
285 uint addr = CFG_I2C_EEPROM_ADDR;
290 addr |= HYMOD_EEOFF_MAIN;
294 if (strcmp (argv[1], "main") == 0) {
295 addr |= HYMOD_EEOFF_MAIN;
298 if (strcmp (argv[1], "mezz") == 0) {
299 addr |= HYMOD_EEOFF_MEZZ;
302 /* fall through ... */
305 printf ("Usage:\n%s\n", cmdtp->usage);
309 memset (data, 0, HYMOD_EEPROM_SIZE);
311 eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
316 /* ------------------------------------------------------------------------- */
319 static uchar test_bitfile[] = {
325 do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
330 #ifdef CONFIG_ETHER_LOOPBACK_TEST
331 extern void eth_loopback_test (void);
332 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
334 printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
337 /* Load FPGA with test program */
339 printf ("Loading test FPGA program ...");
341 rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
346 printf (" SUCCEEDED\n");
349 case LOAD_FAIL_NOCONF:
350 printf (" FAILED (no configuration space defined)\n");
353 case LOAD_FAIL_NOINIT:
354 printf (" FAILED (timeout - no INIT signal seen)\n");
357 case LOAD_FAIL_NODONE:
358 printf (" FAILED (timeout - no DONE signal seen)\n");
362 printf (" FAILED (unknown return code from fpga_load\n");
366 /* run Local Bus <=> Xilinx tests */
368 /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
373 #ifdef CONFIG_ETHER_LOOPBACK_TEST
374 /* run Ethernet test */
375 eth_loopback_test ();
376 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
381 #endif /* CFG_CMD_BSP */
383 /* ------------------------------------------------------------------------- */