board/gateworks/gw_ventana/gw_ventana_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Gateworks Corporation
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <hang.h>
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <env.h>
  20 #include <i2c.h>
  21 #include <spl.h>
  22
  23 #include "gsc.h"
  24 #include "common.h"
  25
  26 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  27 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  28 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  29
  30 /* configure MX6Q/DUAL mmdc DDR io registers */
  31 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  32         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  33         .dram_sdclk_0 = 0x00020030,
  34         .dram_sdclk_1 = 0x00020030,
  35         .dram_cas = 0x00020030,
  36         .dram_ras = 0x00020030,
  37         .dram_reset = 0x00020030,
  38         /* SDCKE[0:1]: 100k pull-up */
  39         .dram_sdcke0 = 0x00003000,
  40         .dram_sdcke1 = 0x00003000,
  41         /* SDBA2: pull-up disabled */
  42         .dram_sdba2 = 0x00000000,
  43         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  44         .dram_sdodt0 = 0x00003030,
  45         .dram_sdodt1 = 0x00003030,
  46         /* SDQS[0:7]: Differential input, 40 ohm */
  47         .dram_sdqs0 = 0x00000030,
  48         .dram_sdqs1 = 0x00000030,
  49         .dram_sdqs2 = 0x00000030,
  50         .dram_sdqs3 = 0x00000030,
  51         .dram_sdqs4 = 0x00000030,
  52         .dram_sdqs5 = 0x00000030,
  53         .dram_sdqs6 = 0x00000030,
  54         .dram_sdqs7 = 0x00000030,
  55
  56         /* DQM[0:7]: Differential input, 40 ohm */
  57         .dram_dqm0 = 0x00020030,
  58         .dram_dqm1 = 0x00020030,
  59         .dram_dqm2 = 0x00020030,
  60         .dram_dqm3 = 0x00020030,
  61         .dram_dqm4 = 0x00020030,
  62         .dram_dqm5 = 0x00020030,
  63         .dram_dqm6 = 0x00020030,
  64         .dram_dqm7 = 0x00020030,
  65 };
  66
  67 /* configure MX6Q/DUAL mmdc GRP io registers */
  68 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  69         /* DDR3 */
  70         .grp_ddr_type = 0x000c0000,
  71         .grp_ddrmode_ctl = 0x00020000,
  72         /* disable DDR pullups */
  73         .grp_ddrpke = 0x00000000,
  74         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  75         .grp_addds = 0x00000030,
  76         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  77         .grp_ctlds = 0x00000030,
  78         /* DATA[00:63]: Differential input, 40 ohm */
  79         .grp_ddrmode = 0x00020000,
  80         .grp_b0ds = 0x00000030,
  81         .grp_b1ds = 0x00000030,
  82         .grp_b2ds = 0x00000030,
  83         .grp_b3ds = 0x00000030,
  84         .grp_b4ds = 0x00000030,
  85         .grp_b5ds = 0x00000030,
  86         .grp_b6ds = 0x00000030,
  87         .grp_b7ds = 0x00000030,
  88 };
  89
  90 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  91 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  92         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  93         .dram_sdclk_0 = 0x00020030,
  94         .dram_sdclk_1 = 0x00020030,
  95         .dram_cas = 0x00020030,
  96         .dram_ras = 0x00020030,
  97         .dram_reset = 0x00020030,
  98         /* SDCKE[0:1]: 100k pull-up */
  99         .dram_sdcke0 = 0x00003000,
 100         .dram_sdcke1 = 0x00003000,
 101         /* SDBA2: pull-up disabled */
 102         .dram_sdba2 = 0x00000000,
 103         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 104         .dram_sdodt0 = 0x00003030,
 105         .dram_sdodt1 = 0x00003030,
 106         /* SDQS[0:7]: Differential input, 40 ohm */
 107         .dram_sdqs0 = 0x00000030,
 108         .dram_sdqs1 = 0x00000030,
 109         .dram_sdqs2 = 0x00000030,
 110         .dram_sdqs3 = 0x00000030,
 111         .dram_sdqs4 = 0x00000030,
 112         .dram_sdqs5 = 0x00000030,
 113         .dram_sdqs6 = 0x00000030,
 114         .dram_sdqs7 = 0x00000030,
 115
 116         /* DQM[0:7]: Differential input, 40 ohm */
 117         .dram_dqm0 = 0x00020030,
 118         .dram_dqm1 = 0x00020030,
 119         .dram_dqm2 = 0x00020030,
 120         .dram_dqm3 = 0x00020030,
 121         .dram_dqm4 = 0x00020030,
 122         .dram_dqm5 = 0x00020030,
 123         .dram_dqm6 = 0x00020030,
 124         .dram_dqm7 = 0x00020030,
 125 };
 126
 127 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 128 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 129         /* DDR3 */
 130         .grp_ddr_type = 0x000c0000,
 131         /* SDQS[0:7]: Differential input, 40 ohm */
 132         .grp_ddrmode_ctl = 0x00020000,
 133         /* disable DDR pullups */
 134         .grp_ddrpke = 0x00000000,
 135         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 136         .grp_addds = 0x00000030,
 137         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 138         .grp_ctlds = 0x00000030,
 139         /* DATA[00:63]: Differential input, 40 ohm */
 140         .grp_ddrmode = 0x00020000,
 141         .grp_b0ds = 0x00000030,
 142         .grp_b1ds = 0x00000030,
 143         .grp_b2ds = 0x00000030,
 144         .grp_b3ds = 0x00000030,
 145         .grp_b4ds = 0x00000030,
 146         .grp_b5ds = 0x00000030,
 147         .grp_b6ds = 0x00000030,
 148         .grp_b7ds = 0x00000030,
 149 };
 150
 151 /* MT41K64M16JT-125 (1Gb density) */
 152 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
 153         .mem_speed = 1600,
 154         .density = 1,
 155         .width = 16,
 156         .banks = 8,
 157         .rowaddr = 13,
 158         .coladdr = 10,
 159         .pagesz = 2,
 160         .trcd = 1375,
 161         .trcmin = 4875,
 162         .trasmin = 3500,
 163 };
 164
 165 /* MT41K128M16JT-125 (2Gb density) */
 166 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 167         .mem_speed = 1600,
 168         .density = 2,
 169         .width = 16,
 170         .banks = 8,
 171         .rowaddr = 14,
 172         .coladdr = 10,
 173         .pagesz = 2,
 174         .trcd = 1375,
 175         .trcmin = 4875,
 176         .trasmin = 3500,
 177 };
 178
 179 /* MT41K256M16HA-125 (4Gb density) */
 180 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 181         .mem_speed = 1600,
 182         .density = 4,
 183         .width = 16,
 184         .banks = 8,
 185         .rowaddr = 15,
 186         .coladdr = 10,
 187         .pagesz = 2,
 188         .trcd = 1375,
 189         .trcmin = 4875,
 190         .trasmin = 3500,
 191 };
 192
 193 /* MT41K512M16HA-125 (8Gb density) */
 194 static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
 195         .mem_speed = 1600,
 196         .density = 8,
 197         .width = 16,
 198         .banks = 8,
 199         .rowaddr = 16,
 200         .coladdr = 10,
 201         .pagesz = 2,
 202         .trcd = 1375,
 203         .trcmin = 4875,
 204         .trasmin = 3500,
 205 };
 206
 207 /*
 208  * calibration - these are the various CPU/DDR3 combinations we support
 209  */
 210 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
 211         /* write leveling calibration determine */
 212         .p0_mpwldectrl0 = 0x004C004E,
 213         .p0_mpwldectrl1 = 0x00440044,
 214         /* Read DQS Gating calibration */
 215         .p0_mpdgctrl0 = 0x42440247,
 216         .p0_mpdgctrl1 = 0x02310232,
 217         /* Read Calibration: DQS delay relative to DQ read access */
 218         .p0_mprddlctl = 0x45424746,
 219         /* Write Calibration: DQ/DM delay relative to DQS write access */
 220         .p0_mpwrdlctl = 0x33382C31,
 221 };
 222
 223 /* TODO: update with calibrated values */
 224 static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
 225         /* write leveling calibration determine */
 226         .p0_mpwldectrl0 = 0x00190017,
 227         .p0_mpwldectrl1 = 0x00140026,
 228         .p1_mpwldectrl0 = 0x0021001C,
 229         .p1_mpwldectrl1 = 0x0011001D,
 230         /* Read DQS Gating calibration */
 231         .p0_mpdgctrl0 = 0x43380347,
 232         .p0_mpdgctrl1 = 0x433C034D,
 233         .p1_mpdgctrl0 = 0x032C0324,
 234         .p1_mpdgctrl1 = 0x03310232,
 235         /* Read Calibration: DQS delay relative to DQ read access */
 236         .p0_mprddlctl = 0x3C313539,
 237         .p1_mprddlctl = 0x37343141,
 238         /* Write Calibration: DQ/DM delay relative to DQS write access */
 239         .p0_mpwrdlctl = 0x36393C39,
 240         .p1_mpwrdlctl = 0x42344438,
 241 };
 242
 243 /* TODO: update with calibrated values */
 244 static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
 245         /* write leveling calibration determine */
 246         .p0_mpwldectrl0 = 0x003C003C,
 247         .p0_mpwldectrl1 = 0x001F002A,
 248         .p1_mpwldectrl0 = 0x00330038,
 249         .p1_mpwldectrl1 = 0x0022003F,
 250         /* Read DQS Gating calibration */
 251         .p0_mpdgctrl0 = 0x42410244,
 252         .p0_mpdgctrl1 = 0x4234023A,
 253         .p1_mpdgctrl0 = 0x022D022D,
 254         .p1_mpdgctrl1 = 0x021C0228,
 255         /* Read Calibration: DQS delay relative to DQ read access */
 256         .p0_mprddlctl = 0x484A4C4B,
 257         .p1_mprddlctl = 0x4B4D4E4B,
 258         /* Write Calibration: DQ/DM delay relative to DQS write access */
 259         .p0_mpwrdlctl = 0x33342B32,
 260         .p1_mpwrdlctl = 0x3933332B,
 261 };
 262
 263 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 264         /* write leveling calibration determine */
 265         .p0_mpwldectrl0 = 0x001B0016,
 266         .p0_mpwldectrl1 = 0x000C000E,
 267         /* Read DQS Gating calibration */
 268         .p0_mpdgctrl0 = 0x4324033A,
 269         .p0_mpdgctrl1 = 0x00000000,
 270         /* Read Calibration: DQS delay relative to DQ read access */
 271         .p0_mprddlctl = 0x40403438,
 272         /* Write Calibration: DQ/DM delay relative to DQS write access */
 273         .p0_mpwrdlctl = 0x40403D36,
 274 };
 275
 276 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 277         /* write leveling calibration determine */
 278         .p0_mpwldectrl0 = 0x00420043,
 279         .p0_mpwldectrl1 = 0x0016001A,
 280         /* Read DQS Gating calibration */
 281         .p0_mpdgctrl0 = 0x4238023B,
 282         .p0_mpdgctrl1 = 0x00000000,
 283         /* Read Calibration: DQS delay relative to DQ read access */
 284         .p0_mprddlctl = 0x40404849,
 285         /* Write Calibration: DQ/DM delay relative to DQS write access */
 286         .p0_mpwrdlctl = 0x40402E2F,
 287 };
 288
 289 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 290         /* write leveling calibration determine */
 291         .p0_mpwldectrl0 = 0x00190017,
 292         .p0_mpwldectrl1 = 0x00140026,
 293         /* Read DQS Gating calibration */
 294         .p0_mpdgctrl0 = 0x43380347,
 295         .p0_mpdgctrl1 = 0x433C034D,
 296         /* Read Calibration: DQS delay relative to DQ read access */
 297         .p0_mprddlctl = 0x3C313539,
 298         /* Write Calibration: DQ/DM delay relative to DQS write access */
 299         .p0_mpwrdlctl = 0x36393C39,
 300 };
 301
 302 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 303         /* write leveling calibration determine */
 304         .p0_mpwldectrl0 = 0x003C003C,
 305         .p0_mpwldectrl1 = 0x001F002A,
 306         /* Read DQS Gating calibration */
 307         .p0_mpdgctrl0 = 0x42410244,
 308         .p0_mpdgctrl1 = 0x4234023A,
 309         /* Read Calibration: DQS delay relative to DQ read access */
 310         .p0_mprddlctl = 0x484A4C4B,
 311         /* Write Calibration: DQ/DM delay relative to DQS write access */
 312         .p0_mpwrdlctl = 0x33342B32,
 313 };
 314
 315 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
 316         /* write leveling calibration determine */
 317         .p0_mpwldectrl0 = 0x00190017,
 318         .p0_mpwldectrl1 = 0x00140026,
 319         .p1_mpwldectrl0 = 0x0021001C,
 320         .p1_mpwldectrl1 = 0x0011001D,
 321         /* Read DQS Gating calibration */
 322         .p0_mpdgctrl0 = 0x43380347,
 323         .p0_mpdgctrl1 = 0x433C034D,
 324         .p1_mpdgctrl0 = 0x032C0324,
 325         .p1_mpdgctrl1 = 0x03310232,
 326         /* Read Calibration: DQS delay relative to DQ read access */
 327         .p0_mprddlctl = 0x3C313539,
 328         .p1_mprddlctl = 0x37343141,
 329         /* Write Calibration: DQ/DM delay relative to DQS write access */
 330         .p0_mpwrdlctl = 0x36393C39,
 331         .p1_mpwrdlctl = 0x42344438,
 332 };
 333
 334 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
 335         /* write leveling calibration determine */
 336         .p0_mpwldectrl0 = 0x003C003C,
 337         .p0_mpwldectrl1 = 0x001F002A,
 338         .p1_mpwldectrl0 = 0x00330038,
 339         .p1_mpwldectrl1 = 0x0022003F,
 340         /* Read DQS Gating calibration */
 341         .p0_mpdgctrl0 = 0x42410244,
 342         .p0_mpdgctrl1 = 0x4234023A,
 343         .p1_mpdgctrl0 = 0x022D022D,
 344         .p1_mpdgctrl1 = 0x021C0228,
 345         /* Read Calibration: DQS delay relative to DQ read access */
 346         .p0_mprddlctl = 0x484A4C4B,
 347         .p1_mprddlctl = 0x4B4D4E4B,
 348         /* Write Calibration: DQ/DM delay relative to DQS write access */
 349         .p0_mpwrdlctl = 0x33342B32,
 350         .p1_mpwrdlctl = 0x3933332B,
 351 };
 352
 353 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 354         /* write leveling calibration determine */
 355         .p0_mpwldectrl0 = 0x001E001A,
 356         .p0_mpwldectrl1 = 0x0026001F,
 357         /* Read DQS Gating calibration */
 358         .p0_mpdgctrl0 = 0x43370349,
 359         .p0_mpdgctrl1 = 0x032D0327,
 360         /* Read Calibration: DQS delay relative to DQ read access */
 361         .p0_mprddlctl = 0x3D303639,
 362         /* Write Calibration: DQ/DM delay relative to DQS write access */
 363         .p0_mpwrdlctl = 0x32363934,
 364 };
 365
 366 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 367         /* write leveling calibration determine */
 368         .p0_mpwldectrl0 = 0X00480047,
 369         .p0_mpwldectrl1 = 0X003D003F,
 370         /* Read DQS Gating calibration */
 371         .p0_mpdgctrl0 = 0X423E0241,
 372         .p0_mpdgctrl1 = 0X022B022C,
 373         /* Read Calibration: DQS delay relative to DQ read access */
 374         .p0_mprddlctl = 0X49454A4A,
 375         /* Write Calibration: DQ/DM delay relative to DQS write access */
 376         .p0_mpwrdlctl = 0X2E372C32,
 377 };
 378
 379 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 380         /* write leveling calibration determine */
 381         .p0_mpwldectrl0 = 0X00220021,
 382         .p0_mpwldectrl1 = 0X00200030,
 383         .p1_mpwldectrl0 = 0X002D0027,
 384         .p1_mpwldectrl1 = 0X00150026,
 385         /* Read DQS Gating calibration */
 386         .p0_mpdgctrl0 = 0x43330342,
 387         .p0_mpdgctrl1 = 0x0339034A,
 388         .p1_mpdgctrl0 = 0x032F0325,
 389         .p1_mpdgctrl1 = 0x032F022E,
 390         /* Read Calibration: DQS delay relative to DQ read access */
 391         .p0_mprddlctl = 0X3A2E3437,
 392         .p1_mprddlctl = 0X35312F3F,
 393         /* Write Calibration: DQ/DM delay relative to DQS write access */
 394         .p0_mpwrdlctl = 0X33363B37,
 395         .p1_mpwrdlctl = 0X40304239,
 396 };
 397
 398 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
 399         /* write leveling calibration determine */
 400         .p0_mpwldectrl0 = 0x0048004A,
 401         .p0_mpwldectrl1 = 0x003F004A,
 402         .p1_mpwldectrl0 = 0x001E0028,
 403         .p1_mpwldectrl1 = 0x002C0043,
 404         /* Read DQS Gating calibration */
 405         .p0_mpdgctrl0 = 0x02250219,
 406         .p0_mpdgctrl1 = 0x01790202,
 407         .p1_mpdgctrl0 = 0x02080208,
 408         .p1_mpdgctrl1 = 0x016C0175,
 409         /* Read Calibration: DQS delay relative to DQ read access */
 410         .p0_mprddlctl = 0x4A4C4D4C,
 411         .p1_mprddlctl = 0x494C4A48,
 412         /* Write Calibration: DQ/DM delay relative to DQS write access */
 413         .p0_mpwrdlctl = 0x403F3437,
 414         .p1_mpwrdlctl = 0x383A3930,
 415 };
 416
 417 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
 418         /* write leveling calibration determine */
 419         .p0_mpwldectrl0 = 0x001F003F,
 420         .p0_mpwldectrl1 = 0x001F001F,
 421         .p1_mpwldectrl0 = 0x001F004E,
 422         .p1_mpwldectrl1 = 0x0059001F,
 423         /* Read DQS Gating calibration */
 424         .p0_mpdgctrl0   = 0x42220225,
 425         .p0_mpdgctrl1   = 0x0213021F,
 426         .p1_mpdgctrl0   = 0x022C0242,
 427         .p1_mpdgctrl1   = 0x022C0244,
 428         /* Read Calibration: DQS delay relative to DQ read access */
 429         .p0_mprddlctl   = 0x474A4C4A,
 430         .p1_mprddlctl   = 0x48494C45,
 431         /* Write Calibration: DQ/DM delay relative to DQS write access */
 432         .p0_mpwrdlctl   = 0x3F3F3F36,
 433         .p1_mpwrdlctl   = 0x3F36363F,
 434 };
 435
 436 static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
 437         /* write leveling calibration determine */
 438         .p0_mpwldectrl0 = 0x001F003F,
 439         .p0_mpwldectrl1 = 0x001F001F,
 440         .p1_mpwldectrl0 = 0x001F004E,
 441         .p1_mpwldectrl1 = 0x0059001F,
 442         /* Read DQS Gating calibration */
 443         .p0_mpdgctrl0   = 0x42220225,
 444         .p0_mpdgctrl1   = 0x0213021F,
 445         .p1_mpdgctrl0   = 0x022C0242,
 446         .p1_mpdgctrl1   = 0x022C0244,
 447         /* Read Calibration: DQS delay relative to DQ read access */
 448         .p0_mprddlctl   = 0x474A4C4A,
 449         .p1_mprddlctl   = 0x48494C45,
 450         /* Write Calibration: DQ/DM delay relative to DQS write access */
 451         .p0_mpwrdlctl   = 0x3F3F3F36,
 452         .p1_mpwrdlctl   = 0x3F36363F,
 453 };
 454
 455 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 456         /* write leveling calibration determine */
 457         .p0_mpwldectrl0 = 0x002A0025,
 458         .p0_mpwldectrl1 = 0x003A002A,
 459         /* Read DQS Gating calibration */
 460         .p0_mpdgctrl0 = 0x43430356,
 461         .p0_mpdgctrl1 = 0x033C0335,
 462         /* Read Calibration: DQS delay relative to DQ read access */
 463         .p0_mprddlctl = 0x4B373F42,
 464         /* Write Calibration: DQ/DM delay relative to DQS write access */
 465         .p0_mpwrdlctl = 0x303E3C36,
 466 };
 467
 468 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
 469         /* write leveling calibration determine */
 470         .p0_mpwldectrl0 = 0x00230020,
 471         .p0_mpwldectrl1 = 0x002F002A,
 472         .p1_mpwldectrl0 = 0x001D0027,
 473         .p1_mpwldectrl1 = 0x00100023,
 474         /* Read DQS Gating calibration */
 475         .p0_mpdgctrl0 = 0x03250339,
 476         .p0_mpdgctrl1 = 0x031C0316,
 477         .p1_mpdgctrl0 = 0x03210331,
 478         .p1_mpdgctrl1 = 0x031C025A,
 479         /* Read Calibration: DQS delay relative to DQ read access */
 480         .p0_mprddlctl = 0x40373C40,
 481         .p1_mprddlctl = 0x3A373646,
 482         /* Write Calibration: DQ/DM delay relative to DQS write access */
 483         .p0_mpwrdlctl = 0x2E353933,
 484         .p1_mpwrdlctl = 0x3C2F3F35,
 485 };
 486
 487 static void spl_dram_init(int width, int size_mb, int board_model)
 488 {
 489         struct mx6_ddr3_cfg *mem = NULL;
 490         struct mx6_mmdc_calibration *calib = NULL;
 491         struct mx6_ddr_sysinfo sysinfo = {
 492                 /* width of data bus:0=16,1=32,2=64 */
 493                 .dsize = width/32,
 494                 /* config for full 4GB range so that get_mem_size() works */
 495                 .cs_density = 32, /* 32Gb per CS */
 496                 /* single chip select */
 497                 .ncs = 1,
 498                 .cs1_mirror = 0,
 499                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 500 #ifdef RTT_NOM_120OHM
 501                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 502 #else
 503                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 504 #endif
 505                 .walat = 1,     /* Write additional latency */
 506                 .ralat = 5,     /* Read additional latency */
 507                 .mif3_mode = 3, /* Command prediction working mode */
 508                 .bi_on = 1,     /* Bank interleaving enabled */
 509                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 510                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 511                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 512                 .ddr_type = DDR_TYPE_DDR3,
 513                 .refsel = 1,    /* Refresh cycles at 32KHz */
 514                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 515         };
 516
 517         /*
 518          * MMDC Calibration requires the following data:
 519          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 520          *      these calibration values depend on board routing, SoC, and DDR
 521          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 522          *   mx6_ddr_cfg - chip specific timing/layout details
 523          */
 524         if (width == 16 && size_mb == 128) {
 525                 mem = &mt41k64m16jt_125;
 526                 if (is_cpu_type(MXC_CPU_MX6Q))
 527                         ;
 528                 else
 529                         calib = &mx6sdl_64x16_mmdc_calib;
 530                 debug("1gB density\n");
 531         } else if (width == 16 && size_mb == 256) {
 532                 /* 1x 2Gb density chip - same calib as 2x 2Gb */
 533                 mem = &mt41k128m16jt_125;
 534                 if (is_cpu_type(MXC_CPU_MX6Q))
 535                         calib = &mx6dq_128x32_mmdc_calib;
 536                 else
 537                         calib = &mx6sdl_128x32_mmdc_calib;
 538                 debug("2gB density\n");
 539         } else if (width == 16 && size_mb == 512) {
 540                 mem = &mt41k256m16ha_125;
 541                 if (is_cpu_type(MXC_CPU_MX6Q))
 542                         calib = &mx6dq_256x16_mmdc_calib;
 543                 else
 544                         calib = &mx6sdl_256x16_mmdc_calib;
 545                 debug("4gB density\n");
 546         } else if (width == 16 && size_mb == 1024) {
 547                 mem = &mt41k512m16ha_125;
 548                 if (is_cpu_type(MXC_CPU_MX6Q))
 549                         calib = &mx6dq_512x32_mmdc_calib;
 550                 debug("8gB density\n");
 551         } else if (width == 32 && size_mb == 256) {
 552                 /* Same calib as width==16, size==128 */
 553                 mem = &mt41k64m16jt_125;
 554                 if (is_cpu_type(MXC_CPU_MX6Q))
 555                         ;
 556                 else
 557                         calib = &mx6sdl_64x16_mmdc_calib;
 558                 debug("1gB density\n");
 559         } else if (width == 32 && size_mb == 512) {
 560                 mem = &mt41k128m16jt_125;
 561                 if (is_cpu_type(MXC_CPU_MX6Q))
 562                         calib = &mx6dq_128x32_mmdc_calib;
 563                 else
 564                         calib = &mx6sdl_128x32_mmdc_calib;
 565                 debug("2gB density\n");
 566         }  else if (width == 32 && size_mb == 1024) {
 567                 mem = &mt41k256m16ha_125;
 568                 if (is_cpu_type(MXC_CPU_MX6Q))
 569                         calib = &mx6dq_256x32_mmdc_calib;
 570                 else
 571                         calib = &mx6sdl_256x32_mmdc_calib;
 572                 debug("4gB density\n");
 573         } else if (width == 32 && size_mb == 2048) {
 574                 mem = &mt41k512m16ha_125;
 575                 if (is_cpu_type(MXC_CPU_MX6Q))
 576                         calib = &mx6dq_512x32_mmdc_calib;
 577                 debug("8gB density\n");
 578         } else if (width == 64 && size_mb == 512) {
 579                 mem = &mt41k64m16jt_125;
 580                 debug("1gB density\n");
 581                 if (is_cpu_type(MXC_CPU_MX6Q))
 582                         calib = &mx6dq_64x64_mmdc_calib;
 583                 else
 584                         calib = &mx6sdl_64x64_mmdc_calib;
 585         } else if (width == 64 && size_mb == 1024) {
 586                 mem = &mt41k128m16jt_125;
 587                 if (is_cpu_type(MXC_CPU_MX6Q))
 588                         calib = &mx6dq_128x64_mmdc_calib;
 589                 else
 590                         calib = &mx6sdl_128x64_mmdc_calib;
 591                 debug("2gB density\n");
 592         } else if (width == 64 && size_mb == 2048) {
 593                 switch(board_model) {
 594                 case GW5905:
 595                         /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
 596                         mem = &mt41k128m16jt_125;
 597                         debug("2gB density - 2 chipsel\n");
 598                         if (!is_cpu_type(MXC_CPU_MX6Q)) {
 599                                 calib = &mx6sdl_128x64x2_mmdc_calib;
 600                                 sysinfo.ncs = 2;
 601                                 sysinfo.cs_density = 10; /* CS0_END=39 */
 602                                 sysinfo.cs1_mirror = 1; /* mirror enabled */
 603                         }
 604                         break;
 605                 default:
 606                         mem = &mt41k256m16ha_125;
 607                         if (is_cpu_type(MXC_CPU_MX6Q))
 608                                 calib = &mx6dq_256x64_mmdc_calib;
 609                         else
 610                                 calib = &mx6sdl_256x64_mmdc_calib;
 611                         debug("4gB density\n");
 612                         break;
 613                 }
 614         } else if (width == 64 && size_mb == 4096) {
 615                 switch(board_model) {
 616                 case GW5903:
 617                         /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
 618                         mem = &mt41k256m16ha_125;
 619                         debug("4gB density - 2 chipsel\n");
 620                         if (!is_cpu_type(MXC_CPU_MX6Q)) {
 621                                 calib = &mx6sdl_256x64x2_mmdc_calib;
 622                                 sysinfo.ncs = 2;
 623                                 sysinfo.cs_density = 18; /* CS0_END=71 */
 624                                 sysinfo.cs1_mirror = 1; /* mirror enabled */
 625                         }
 626                         break;
 627                 default:
 628                         mem = &mt41k512m16ha_125;
 629                         if (is_cpu_type(MXC_CPU_MX6Q))
 630                                 calib = &mx6dq_512x64_mmdc_calib;
 631                         debug("8gB density\n");
 632                         break;
 633                 }
 634         }
 635
 636         if (!(mem && calib)) {
 637                 puts("Error: Invalid Calibration/Board Configuration\n");
 638                 printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
 639                 printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
 640                 printf("CPUTYPE: %s\n",
 641                        is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
 642                 printf("SIZE_MB: %d\n", size_mb);
 643                 printf("WIDTH  : %d\n", width);
 644                 hang();
 645         }
 646
 647         if (is_cpu_type(MXC_CPU_MX6Q))
 648                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 649                                  &mx6dq_grp_ioregs);
 650         else
 651                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 652                                   &mx6sdl_grp_ioregs);
 653         mx6_dram_cfg(&sysinfo, calib, mem);
 654 }
 655
 656 static void ccgr_init(void)
 657 {
 658         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 659
 660         writel(0x00C03F3F, &ccm->CCGR0);
 661         writel(0x0030FC03, &ccm->CCGR1);
 662         writel(0x0FFFC000, &ccm->CCGR2);
 663         writel(0x3FF00000, &ccm->CCGR3);
 664         writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
 665         writel(0x0F0000C3, &ccm->CCGR5);
 666         writel(0x000003FF, &ccm->CCGR6);
 667 }
 668
 669 /*
 670  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 671  * - we have a stack and a place to store GD, both in SRAM
 672  * - no variable global data is available
 673  */
 674 void board_init_f(ulong dummy)
 675 {
 676         struct ventana_board_info ventana_info;
 677         int board_model;
 678
 679         /* setup clock gating */
 680         ccgr_init();
 681
 682         /* setup AIPS and disable watchdog */
 683         arch_cpu_init();
 684
 685         /* setup AXI */
 686         gpr_init();
 687
 688         /* iomux and setup of uart/i2c */
 689         setup_iomux_uart();
 690         setup_ventana_i2c(0);
 691         setup_ventana_i2c(1);
 692
 693         /* setup GP timer */
 694         timer_init();
 695
 696         /* UART clocks enabled and gd valid - init serial console */
 697         preloader_console_init();
 698
 699         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 700         board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 701
 702         /* configure model-specific gpio */
 703         setup_iomux_gpio(board_model, &ventana_info);
 704
 705         /* provide some some default: 32bit 128MB */
 706         if (GW_UNKNOWN == board_model)
 707                 hang();
 708
 709         /* configure MMDC for SDRAM width/size and per-model calibration */
 710         spl_dram_init(8 << ventana_info.sdram_width,
 711                       16 << ventana_info.sdram_size,
 712                       board_model);
 713 }
 714
 715 void board_boot_order(u32 *spl_boot_list)
 716 {
 717         spl_boot_list[0] = spl_boot_device();
 718         switch (spl_boot_list[0]) {
 719         case BOOT_DEVICE_NAND:
 720                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 721                 spl_boot_list[2] = BOOT_DEVICE_UART;
 722                 break;
 723         case BOOT_DEVICE_MMC1:
 724                 spl_boot_list[1] = BOOT_DEVICE_UART;
 725                 break;
 726         }
 727 }
 728
 729 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 730 /* its our chance to print info about boot device */
 731 void spl_board_init(void)
 732 {
 733         /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
 734         u32 boot_device = spl_boot_device();
 735
 736         switch (boot_device) {
 737         case BOOT_DEVICE_MMC1:
 738                 puts("Booting from MMC\n");
 739                 break;
 740         case BOOT_DEVICE_NAND:
 741                 puts("Booting from NAND\n");
 742                 break;
 743         case BOOT_DEVICE_SATA:
 744                 puts("Booting from SATA\n");
 745                 break;
 746         default:
 747                 puts("Unknown boot device\n");
 748         }
 749
 750         /* PMIC init */
 751         setup_pmic();
 752 }
 753
 754 #ifdef CONFIG_SPL_OS_BOOT
 755 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 756 int spl_start_uboot(void)
 757 {
 758         unsigned char ret = 1;
 759
 760         debug("%s\n", __func__);
 761 #ifdef CONFIG_SPL_ENV_SUPPORT
 762         env_init();
 763         env_load();
 764         debug("boot_os=%s\n", env_get("boot_os"));
 765         if (env_get_yesno("boot_os") == 1)
 766                 ret = 0;
 767 #else
 768         /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
 769         i2c_set_bus_num(0);
 770         gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 771 #endif
 772         if (!ret)
 773                 gsc_boot_wd_disable();
 774
 775         debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
 776         return ret;
 777 }
 778 #endif