1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <fsl_ddr_sdram.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
26 #include <fsl_dtsec.h>
27 #include <asm/fsl_serdes.h>
29 #include "../common/qixis.h"
30 #include "../common/fman.h"
31 #include <linux/libfdt.h>
33 #include "t4240qds_qixis.h"
35 #define EMI_NONE 0xFFFFFFFF
44 /* Slot6 and Slot8 do not have EMI connections */
46 static int mdio_mux[NUM_FM_PORTS];
48 static const char *mdio_names[] = {
60 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
61 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
62 static u8 slot_qsgmii_phyaddr[5][4] = {
63 {0, 0, 0, 0},/* not used, to make index match slot No. */
69 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
71 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
73 return mdio_names[muxval];
76 struct mii_dev *mii_dev_for_muxval(u8 muxval)
79 const char *name = t4240qds_mdio_name_for_muxval(muxval);
82 printf("No bus for muxval %x\n", muxval);
86 bus = miiphy_get_dev_by_name(name);
89 printf("No bus by name %s\n", name);
96 struct t4240qds_mdio {
98 struct mii_dev *realbus;
101 static void t4240qds_mux_mdio(u8 muxval)
104 if ((muxval < 6) || (muxval == 7)) {
105 brdcfg4 = QIXIS_READ(brdcfg[4]);
106 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
107 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
108 QIXIS_WRITE(brdcfg[4], brdcfg4);
112 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
115 struct t4240qds_mdio *priv = bus->priv;
117 t4240qds_mux_mdio(priv->muxval);
119 return priv->realbus->read(priv->realbus, addr, devad, regnum);
122 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
123 int regnum, u16 value)
125 struct t4240qds_mdio *priv = bus->priv;
127 t4240qds_mux_mdio(priv->muxval);
129 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
132 static int t4240qds_mdio_reset(struct mii_dev *bus)
134 struct t4240qds_mdio *priv = bus->priv;
136 return priv->realbus->reset(priv->realbus);
139 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
141 struct t4240qds_mdio *pmdio;
142 struct mii_dev *bus = mdio_alloc();
145 printf("Failed to allocate T4240QDS MDIO bus\n");
149 pmdio = malloc(sizeof(*pmdio));
151 printf("Failed to allocate T4240QDS private data\n");
156 bus->read = t4240qds_mdio_read;
157 bus->write = t4240qds_mdio_write;
158 bus->reset = t4240qds_mdio_reset;
159 strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
161 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
163 if (!pmdio->realbus) {
164 printf("No bus with name %s\n", realbusname);
170 pmdio->muxval = muxval;
173 return mdio_register(bus);
176 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
177 enum fm_port port, int offset)
179 int interface = fm_info_get_enet_if(port);
180 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
181 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
183 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
185 if (interface == PHY_INTERFACE_MODE_SGMII ||
186 interface == PHY_INTERFACE_MODE_QSGMII) {
189 if (qsgmiiphy_fix[port])
190 fdt_set_phy_handle(blob, prop, pa,
194 if (qsgmiiphy_fix[port])
195 fdt_set_phy_handle(blob, prop, pa,
199 if (qsgmiiphy_fix[port])
200 fdt_set_phy_handle(blob, prop, pa,
204 if (qsgmiiphy_fix[port])
205 fdt_set_phy_handle(blob, prop, pa,
209 if (qsgmiiphy_fix[port])
210 fdt_set_phy_handle(blob, prop, pa,
214 if (qsgmiiphy_fix[port])
215 fdt_set_phy_handle(blob, prop, pa,
218 fdt_set_phy_handle(blob, prop, pa,
222 if (qsgmiiphy_fix[port])
223 fdt_set_phy_handle(blob, prop, pa,
226 fdt_set_phy_handle(blob, prop, pa,
230 if (qsgmiiphy_fix[port])
231 fdt_set_phy_handle(blob, prop, pa,
235 if (qsgmiiphy_fix[port])
236 fdt_set_phy_handle(blob, prop, pa,
240 if (qsgmiiphy_fix[port])
241 fdt_set_phy_handle(blob, prop, pa,
245 if (qsgmiiphy_fix[port])
246 fdt_set_phy_handle(blob, prop, pa,
250 if (qsgmiiphy_fix[port])
251 fdt_set_phy_handle(blob, prop, pa,
255 if (qsgmiiphy_fix[port])
256 fdt_set_phy_handle(blob, prop, pa,
259 fdt_set_phy_handle(blob, prop, pa,
263 if (qsgmiiphy_fix[port])
264 fdt_set_phy_handle(blob, prop, pa,
267 fdt_set_phy_handle(blob, prop, pa,
273 } else if (interface == PHY_INTERFACE_MODE_XGMII &&
274 ((prtcl2 == 55) || (prtcl2 == 57))) {
276 * if the 10G is XFI, check hwconfig to see what is the
277 * media type, there are two types, fiber or copper,
278 * fix the dtb accordingly.
281 struct fixed_link f_link;
282 char lane_mode[20] = {"10GBASE-KR"};
283 char buf[32] = "serdes-2,";
288 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
290 fdt_set_phy_handle(blob, prop, pa,
292 sprintf(buf, "%s%s%s", buf, "lane-a,",
297 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
299 fdt_set_phy_handle(blob, prop, pa,
301 sprintf(buf, "%s%s%s", buf, "lane-b,",
306 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
308 fdt_set_phy_handle(blob, prop, pa,
310 sprintf(buf, "%s%s%s", buf, "lane-d,",
315 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
317 fdt_set_phy_handle(blob, prop, pa,
319 sprintf(buf, "%s%s%s", buf, "lane-c,",
328 /* fixed-link is used for XFI fiber cable */
329 fdt_delprop(blob, offset, "phy-handle");
330 f_link.phy_id = port;
332 f_link.link_speed = 10000;
334 f_link.asym_pause = 0;
335 fdt_setprop(blob, offset, "fixed-link", &f_link,
338 /* set property for copper cable */
339 off = fdt_node_offset_by_compat_reg(blob,
340 "fsl,fman-memac-mdio", pa + 0x1000);
341 fdt_setprop_string(blob, off, "lane-instance", buf);
346 void fdt_fixup_board_enet(void *fdt)
349 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
350 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
352 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
353 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
354 switch (fm_info_get_enet_if(i)) {
355 case PHY_INTERFACE_MODE_SGMII:
356 case PHY_INTERFACE_MODE_QSGMII:
357 switch (mdio_mux[i]) {
359 fdt_status_okay_by_alias(fdt, "emi1_slot1");
362 fdt_status_okay_by_alias(fdt, "emi1_slot2");
365 fdt_status_okay_by_alias(fdt, "emi1_slot3");
368 fdt_status_okay_by_alias(fdt, "emi1_slot4");
374 case PHY_INTERFACE_MODE_XGMII:
375 /* check if it's XFI interface for 10g */
376 if ((prtcl2 == 55) || (prtcl2 == 57)) {
377 if (i == FM1_10GEC1 && hwconfig_sub(
378 "fsl_10gkr_copper", "fm1_10g1"))
379 fdt_status_okay_by_alias(
380 fdt, "xfi_pcs_mdio1");
381 if (i == FM1_10GEC2 && hwconfig_sub(
382 "fsl_10gkr_copper", "fm1_10g2"))
383 fdt_status_okay_by_alias(
384 fdt, "xfi_pcs_mdio2");
385 if (i == FM2_10GEC1 && hwconfig_sub(
386 "fsl_10gkr_copper", "fm2_10g1"))
387 fdt_status_okay_by_alias(
388 fdt, "xfi_pcs_mdio3");
389 if (i == FM2_10GEC2 && hwconfig_sub(
390 "fsl_10gkr_copper", "fm2_10g2"))
391 fdt_status_okay_by_alias(
392 fdt, "xfi_pcs_mdio4");
397 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
400 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
403 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
406 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
418 static void initialize_qsgmiiphy_fix(void)
423 for (i = 1; i <= 4; i++) {
425 * Try to read if a SGMII card is used, we do it slot by slot.
426 * if a SGMII PHY address is valid on a slot, then we mark
427 * all ports on the slot, then fix the PHY address for the
428 * marked port when doing dtb fixup.
430 if (miiphy_read(mdio_names[i],
431 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
432 debug("Slot%d PHY ID register 2 read failed\n", i);
436 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
439 /* No physical device present at this address */
445 qsgmiiphy_fix[FM1_DTSEC5] = 1;
446 qsgmiiphy_fix[FM1_DTSEC6] = 1;
447 qsgmiiphy_fix[FM1_DTSEC9] = 1;
448 qsgmiiphy_fix[FM1_DTSEC10] = 1;
449 slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
450 slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
451 slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
452 slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
455 qsgmiiphy_fix[FM1_DTSEC1] = 1;
456 qsgmiiphy_fix[FM1_DTSEC2] = 1;
457 qsgmiiphy_fix[FM1_DTSEC3] = 1;
458 qsgmiiphy_fix[FM1_DTSEC4] = 1;
459 slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
460 slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
461 slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
462 slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
465 qsgmiiphy_fix[FM2_DTSEC5] = 1;
466 qsgmiiphy_fix[FM2_DTSEC6] = 1;
467 qsgmiiphy_fix[FM2_DTSEC9] = 1;
468 qsgmiiphy_fix[FM2_DTSEC10] = 1;
469 slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
470 slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
471 slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
472 slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
475 qsgmiiphy_fix[FM2_DTSEC1] = 1;
476 qsgmiiphy_fix[FM2_DTSEC2] = 1;
477 qsgmiiphy_fix[FM2_DTSEC3] = 1;
478 qsgmiiphy_fix[FM2_DTSEC4] = 1;
479 slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
480 slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
481 slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
482 slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
490 int board_eth_init(bd_t *bis)
492 #if defined(CONFIG_FMAN_ENET)
493 int i, idx, lane, slot, interface;
494 struct memac_mdio_info dtsec_mdio_info;
495 struct memac_mdio_info tgec_mdio_info;
496 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
497 u32 srds_prtcl_s1, srds_prtcl_s2;
499 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
500 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
501 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
502 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
503 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
504 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
506 /* Initialize the mdio_mux array so we can recognize empty elements */
507 for (i = 0; i < NUM_FM_PORTS; i++)
508 mdio_mux[i] = EMI_NONE;
510 dtsec_mdio_info.regs =
511 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
513 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
515 /* Register the 1G MDIO bus */
516 fm_memac_mdio_init(bis, &dtsec_mdio_info);
518 tgec_mdio_info.regs =
519 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
520 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
522 /* Register the 10G MDIO bus */
523 fm_memac_mdio_init(bis, &tgec_mdio_info);
525 /* Register the muxing front-ends to the MDIO buses */
526 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
527 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
528 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
529 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
530 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
531 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
532 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
533 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
535 initialize_qsgmiiphy_fix();
537 switch (srds_prtcl_s1) {
541 /* XAUI/HiGig in Slot1 and Slot2 */
542 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
543 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
549 /* SGMII in Slot1 and Slot2 */
550 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
551 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
552 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
553 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
554 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
555 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
556 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
557 fm_info_set_phy_address(FM1_DTSEC9,
558 slot_qsgmii_phyaddr[1][3]);
559 fm_info_set_phy_address(FM1_DTSEC10,
560 slot_qsgmii_phyaddr[1][2]);
565 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
566 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
567 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
568 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
569 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
570 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
571 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
572 fm_info_set_phy_address(FM1_DTSEC9,
573 slot_qsgmii_phyaddr[1][2]);
574 fm_info_set_phy_address(FM1_DTSEC10,
575 slot_qsgmii_phyaddr[1][3]);
584 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
585 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
586 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
587 fm_info_set_phy_address(FM1_DTSEC10,
588 slot_qsgmii_phyaddr[1][2]);
589 fm_info_set_phy_address(FM1_DTSEC9,
590 slot_qsgmii_phyaddr[1][3]);
592 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
593 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
594 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
595 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
598 puts("Invalid SerDes1 protocol for T4240QDS\n");
602 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
603 idx = i - FM1_DTSEC1;
604 interface = fm_info_get_enet_if(i);
606 case PHY_INTERFACE_MODE_SGMII:
607 case PHY_INTERFACE_MODE_QSGMII:
608 if (interface == PHY_INTERFACE_MODE_QSGMII) {
610 lane = serdes_get_first_lane(FSL_SRDS_1,
613 lane = serdes_get_first_lane(FSL_SRDS_1,
617 slot = lane_to_slot_fsm1[lane];
618 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
621 lane = serdes_get_first_lane(FSL_SRDS_1,
622 SGMII_FM1_DTSEC1 + idx);
625 slot = lane_to_slot_fsm1[lane];
626 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
629 if (QIXIS_READ(present2) & (1 << (slot - 1)))
633 mdio_mux[i] = EMI1_SLOT1;
635 mii_dev_for_muxval(mdio_mux[i]));
638 mdio_mux[i] = EMI1_SLOT2;
640 mii_dev_for_muxval(mdio_mux[i]));
644 case PHY_INTERFACE_MODE_RGMII:
645 /* FM1 DTSEC5 routes to RGMII with EC2 */
646 debug("FM1@DTSEC%u is RGMII at address %u\n",
649 fm_info_set_phy_address(i, 2);
650 mdio_mux[i] = EMI1_RGMII;
652 mii_dev_for_muxval(mdio_mux[i]));
659 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
660 idx = i - FM1_10GEC1;
661 switch (fm_info_get_enet_if(i)) {
662 case PHY_INTERFACE_MODE_XGMII:
663 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
664 /* A fake PHY address to make U-Boot happy */
665 fm_info_set_phy_address(i, i);
667 lane = serdes_get_first_lane(FSL_SRDS_1,
668 XAUI_FM1_MAC9 + idx);
671 slot = lane_to_slot_fsm1[lane];
672 if (QIXIS_READ(present2) & (1 << (slot - 1)))
676 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
683 #if (CONFIG_SYS_NUM_FMAN == 2)
684 switch (srds_prtcl_s2) {
688 /* XAUI/HiGig in Slot3 and Slot4 */
689 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
690 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
705 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
706 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
707 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
708 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
709 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
710 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
716 /* SGMII in Slot3 and Slot4 */
717 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
718 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
719 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
720 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
721 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
722 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
723 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
724 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
728 /* QSGMII in Slot3 and Slot4 */
729 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
730 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
731 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
732 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
733 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
734 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
735 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
736 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
745 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
746 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
747 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
748 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
749 /* QSGMII in Slot4 */
750 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
751 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
752 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
753 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
761 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
762 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
763 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
764 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
765 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
769 /* XFI in Slot3, SGMII in Slot4 */
770 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
771 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
772 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
773 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
776 puts("Invalid SerDes2 protocol for T4240QDS\n");
780 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
781 idx = i - FM2_DTSEC1;
782 interface = fm_info_get_enet_if(i);
784 case PHY_INTERFACE_MODE_SGMII:
785 case PHY_INTERFACE_MODE_QSGMII:
786 if (interface == PHY_INTERFACE_MODE_QSGMII) {
788 lane = serdes_get_first_lane(FSL_SRDS_2,
791 lane = serdes_get_first_lane(FSL_SRDS_2,
795 slot = lane_to_slot_fsm2[lane];
796 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
799 lane = serdes_get_first_lane(FSL_SRDS_2,
800 SGMII_FM2_DTSEC1 + idx);
803 slot = lane_to_slot_fsm2[lane];
804 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
807 if (QIXIS_READ(present2) & (1 << (slot - 1)))
811 mdio_mux[i] = EMI1_SLOT3;
813 mii_dev_for_muxval(mdio_mux[i]));
816 mdio_mux[i] = EMI1_SLOT4;
818 mii_dev_for_muxval(mdio_mux[i]));
822 case PHY_INTERFACE_MODE_RGMII:
824 * If DTSEC5 is RGMII, then it's routed via via EC1 to
825 * the first on-board RGMII port. If DTSEC6 is RGMII,
826 * then it's routed via via EC2 to the second on-board
829 debug("FM2@DTSEC%u is RGMII at address %u\n",
830 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
831 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
832 mdio_mux[i] = EMI1_RGMII;
833 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
840 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
841 idx = i - FM2_10GEC1;
842 switch (fm_info_get_enet_if(i)) {
843 case PHY_INTERFACE_MODE_XGMII:
844 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
845 /* A fake PHY address to make U-Boot happy */
846 fm_info_set_phy_address(i, i);
848 lane = serdes_get_first_lane(FSL_SRDS_2,
849 XAUI_FM2_MAC9 + idx);
852 slot = lane_to_slot_fsm2[lane];
853 if (QIXIS_READ(present2) & (1 << (slot - 1)))
857 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
863 #endif /* CONFIG_SYS_NUM_FMAN */
866 #endif /* CONFIG_FMAN_ENET */
868 return pci_eth_init(bis);