1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
10 #include <asm/processor.h>
11 #include <asm/immap_86xx.h>
12 #include <asm/fsl_pci.h>
13 #include <fsl_ddr_sdram.h>
14 #include <asm/fsl_serdes.h>
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 phys_size_t fixed_sdram(void);
27 u8 *pixis_base = (u8 *)PIXIS_BASE;
29 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
30 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
31 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
32 in_8(pixis_base + PIXIS_PVER));
34 vboot = in_8(pixis_base + PIXIS_VBOOT);
35 if (vboot & PIXIS_VBOOT_FMAP)
36 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
45 phys_size_t dram_size = 0;
47 #if defined(CONFIG_SPD_EEPROM)
48 dram_size = fsl_ddr_sdram();
50 dram_size = fixed_sdram();
53 setup_ddr_bat(dram_size);
56 gd->ram_size = dram_size;
62 #if !defined(CONFIG_SPD_EEPROM)
64 * Fixed sdram init -- doesn't use serial presence detect.
69 #if !defined(CONFIG_SYS_RAMBOOT)
70 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
71 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
73 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
74 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
75 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
80 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
81 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
82 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
83 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
84 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
85 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
87 #if defined (CONFIG_DDR_ECC)
88 ddr->err_disable = 0x0000008D;
89 ddr->err_sbe = 0x00ff0000;
95 #if defined (CONFIG_DDR_ECC)
96 /* Enable ECC checking */
97 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
99 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
100 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
106 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
108 #endif /* !defined(CONFIG_SPD_EEPROM) */
110 void pci_init_board(void)
112 fsl_pcie_init_board(0);
116 * Activate ULI1575 legacy chip by performing a fake
117 * memory access. Needed to make ULI RTC work.
119 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
120 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
121 #endif /* CONFIG_PCIE1 */
125 #if defined(CONFIG_OF_BOARD_SETUP)
126 int ft_board_setup(void *blob, bd_t *bd)
132 ft_cpu_setup(blob, bd);
137 * Warn if it looks like the device tree doesn't match u-boot.
138 * This is just an estimation, based on the location of CCSR,
139 * which is defined by the "reg" property in the soc node.
141 off = fdt_path_offset(blob, "/soc8641");
142 addrcells = fdt_address_cells(blob, 0);
143 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
153 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
154 printf("WARNING: The CCSRBAR address in your .dts "
155 "does not match the address of the CCSR "
156 "in u-boot. This means your .dts might "
167 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
171 get_board_sys_clk(ulong dummy)
173 u8 i, go_bit, rd_clks;
175 u8 *pixis_base = (u8 *)PIXIS_BASE;
177 go_bit = in_8(pixis_base + PIXIS_VCTL);
180 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
184 * Only if both go bit and the SCLK bit in VCFGEN0 are set
185 * should we be using the AUX register. Remember, we also set the
186 * GO bit to boot from the alternate bank on the on-board flash
191 i = in_8(pixis_base + PIXIS_AUX);
193 i = in_8(pixis_base + PIXIS_SPD);
195 i = in_8(pixis_base + PIXIS_SPD);
230 int board_eth_init(bd_t *bis)
232 /* Initialize TSECs */
234 return pci_eth_init(bis);
237 void board_reset(void)
239 u8 *pixis_base = (u8 *)PIXIS_BASE;
241 out_8(pixis_base + PIXIS_RST, 0);