board/freescale/mpc8548cds/mpc8548cds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <display_options.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <pci.h>
  13 #include <vsprintf.h>
  14 #include <asm/processor.h>
  15 #include <asm/mmu.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_pci.h>
  18 #include <fsl_ddr_sdram.h>
  19 #include <asm/fsl_serdes.h>
  20 #include <miiphy.h>
  21 #include <linux/delay.h>
  22 #include <linux/libfdt.h>
  23 #include <fdt_support.h>
  24 #include <tsec.h>
  25 #include <fsl_mdio.h>
  26 #include <netdev.h>
  27
  28 #include "../common/cadmus.h"
  29 #include "../common/eeprom.h"
  30 #include "../common/via.h"
  31
  32 void local_bus_init(void);
  33
  34 int checkboard (void)
  35 {
  36         volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  37         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
  38
  39         /* PCI slot in USER bits CSR[6:7] by convention. */
  40         uint pci_slot = get_pci_slot ();
  41
  42         uint cpu_board_rev = get_cpu_board_revision ();
  43
  44         puts("Board: MPC8548CDS");
  45         printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
  46                         get_board_version(), pci_slot);
  47         printf("       Daughtercard Rev: %d.%d (0x%04x)\n",
  48                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  49                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  50         /*
  51          * Initialize local bus.
  52          */
  53         local_bus_init ();
  54
  55         /*
  56          * Hack TSEC 3 and 4 IO voltages.
  57          */
  58         gur->tsec34ioovcr = 0xe7e0;     /*  1110 0111 1110 0xxx */
  59
  60         ecm->eedr = 0xffffffff;         /* clear ecm errors */
  61         ecm->eeer = 0xffffffff;         /* enable ecm errors */
  62         return 0;
  63 }
  64
  65 /*
  66  * Initialize Local Bus
  67  */
  68 void
  69 local_bus_init(void)
  70 {
  71         volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  72         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  73
  74         uint clkdiv;
  75         sys_info_t sysinfo;
  76
  77         get_sys_info(&sysinfo);
  78         clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  79
  80         gur->lbiuiplldcr1 = 0x00078080;
  81         if (clkdiv == 16) {
  82                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
  83         } else if (clkdiv == 8) {
  84                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
  85         } else if (clkdiv == 4) {
  86                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
  87         }
  88
  89         lbc->lcrr |= 0x00030000;
  90
  91         asm("sync;isync;msync");
  92
  93         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  94         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  95 }
  96
  97 /*
  98  * Initialize SDRAM memory on the Local Bus.
  99  */
 100 void lbc_sdram_init(void)
 101 {
 102 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 103
 104         uint idx;
 105         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 106         uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
 107         uint lsdmr_common;
 108
 109         puts("LBC SDRAM: ");
 110         print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 111                    "\n");
 112
 113         /*
 114          * Setup SDRAM Base and Option Registers
 115          */
 116         set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 117         set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 118         lbc->lbcr = CFG_SYS_LBC_LBCR;
 119         asm("msync");
 120
 121         lbc->lsrt = CFG_SYS_LBC_LSRT;
 122         lbc->mrtpr = CFG_SYS_LBC_MRTPR;
 123         asm("msync");
 124
 125         /*
 126          * MPC8548 uses "new" 15-16 style addressing.
 127          */
 128         lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
 129         lsdmr_common |= LSDMR_BSMA1516;
 130
 131         /*
 132          * Issue PRECHARGE ALL command.
 133          */
 134         lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 135         asm("sync;msync");
 136         *sdram_addr = 0xff;
 137         ppcDcbf((unsigned long) sdram_addr);
 138         udelay(100);
 139
 140         /*
 141          * Issue 8 AUTO REFRESH commands.
 142          */
 143         for (idx = 0; idx < 8; idx++) {
 144                 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 145                 asm("sync;msync");
 146                 *sdram_addr = 0xff;
 147                 ppcDcbf((unsigned long) sdram_addr);
 148                 udelay(100);
 149         }
 150
 151         /*
 152          * Issue 8 MODE-set command.
 153          */
 154         lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 155         asm("sync;msync");
 156         *sdram_addr = 0xff;
 157         ppcDcbf((unsigned long) sdram_addr);
 158         udelay(100);
 159
 160         /*
 161          * Issue NORMAL OP command.
 162          */
 163         lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 164         asm("sync;msync");
 165         *sdram_addr = 0xff;
 166         ppcDcbf((unsigned long) sdram_addr);
 167         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 168
 169 #endif  /* enable SDRAM init */
 170 }
 171
 172 #ifndef CONFIG_DM_ETH
 173 static void configure_rgmii(void)
 174 {
 175         unsigned short temp;
 176
 177         /* Change the resistors for the PHY */
 178         /* This is needed to get the RGMII working for the 1.3+
 179          * CDS cards */
 180         if (get_board_version() ==  0x13) {
 181                 miiphy_write(DEFAULT_MII_NAME,
 182                                 TSEC1_PHY_ADDR, 29, 18);
 183
 184                 miiphy_read(DEFAULT_MII_NAME,
 185                                 TSEC1_PHY_ADDR, 30, &temp);
 186
 187                 temp = (temp & 0xf03f);
 188                 temp |= 2 << 9;         /* 36 ohm */
 189                 temp |= 2 << 6;         /* 39 ohm */
 190
 191                 miiphy_write(DEFAULT_MII_NAME,
 192                                 TSEC1_PHY_ADDR, 30, temp);
 193
 194                 miiphy_write(DEFAULT_MII_NAME,
 195                                 TSEC1_PHY_ADDR, 29, 3);
 196
 197                 miiphy_write(DEFAULT_MII_NAME,
 198                                 TSEC1_PHY_ADDR, 30, 0x8000);
 199         }
 200
 201         return;
 202 }
 203
 204 int board_eth_init(struct bd_info *bis)
 205 {
 206 #ifdef CONFIG_TSEC_ENET
 207         struct fsl_pq_mdio_info mdio_info;
 208         struct tsec_info_struct tsec_info[4];
 209         int num = 0;
 210
 211 #ifdef CONFIG_TSEC1
 212         SET_STD_TSEC_INFO(tsec_info[num], 1);
 213         num++;
 214 #endif
 215 #ifdef CONFIG_TSEC2
 216         SET_STD_TSEC_INFO(tsec_info[num], 2);
 217         num++;
 218 #endif
 219 #ifdef CONFIG_TSEC3
 220         /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
 221         if (get_board_version() >= 0x13) {
 222                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 223                 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
 224                 num++;
 225         }
 226 #endif
 227 #ifdef CONFIG_TSEC4
 228         /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
 229         if (get_board_version() >= 0x13) {
 230                 SET_STD_TSEC_INFO(tsec_info[num], 4);
 231                 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
 232                 num++;
 233         }
 234 #endif
 235
 236         if (!num) {
 237                 printf("No TSECs initialized\n");
 238
 239                 return 0;
 240         }
 241
 242         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 243         mdio_info.name = DEFAULT_MII_NAME;
 244         fsl_pq_mdio_init(bis, &mdio_info);
 245
 246         tsec_eth_init(bis, tsec_info, num);
 247         configure_rgmii();
 248 #endif
 249
 250         return pci_eth_init(bis);
 251 }
 252 #endif