1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 #include <asm/immap.h>
15 #include <linux/delay.h>
17 DECLARE_GLOBAL_DATA_PTR;
22 puts("Freescale M54455 EVB\n");
31 * Serial Boot: The dram is already initialized in start.S
32 * only require to return DRAM size
34 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
36 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
37 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
40 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
42 for (i = 0x13; i < 0x20; i++) {
43 if (dramsize == (1 << i))
48 out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
50 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
51 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
53 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
54 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
57 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
60 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
66 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
68 /* Perform two refresh cycles */
69 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
72 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
74 out_be32(&sdram->sdcr,
75 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
79 gd->ram_size = dramsize << 1;
86 /* TODO: XXX XXX XXX */
87 printf("DRAM test not implemented!\n");
92 #if defined(CONFIG_IDE)
97 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
100 tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
101 setbits_8(&gpio->par_fec, tmp);
102 tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
103 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
104 setbits_be16(&gpio->par_feci2c, tmp);
106 setbits_be16(&gpio->par_ata,
107 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
108 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
109 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
110 GPIO_PAR_ATA_IORDY_IORDY);
111 setbits_be16(&gpio->par_pci,
112 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
117 void ide_set_reset(int idereset)
119 atac_t *ata = (atac_t *) MMAP_ATA;
121 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
123 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
124 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
125 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
126 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
127 {25, 70, 20, 10, 20, 5, 10, 0, 35}
135 #define CALC_TIMING(t) (t + period - 1) / period
136 period = 1000000000 / gd->bus_clk; /* period in ns */
138 /*ata->ton = CALC_TIMING (180); */
139 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
140 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
141 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
142 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
143 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
144 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
145 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
148 out_8(&ata->cr, 0x40);
151 setbits_8(&ata->cr, 0x01);
156 #if defined(CONFIG_PCI)
158 * Initialize PCI devices, report devices found.
160 static struct pci_controller hose;
161 extern void pci_mcf5445x_init(struct pci_controller *hose);
163 void pci_init_board(void)
165 pci_mcf5445x_init(&hose);
167 #endif /* CONFIG_PCI */
169 #if defined(CONFIG_FLASH_CFI_LEGACY)
171 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
173 int sect[] = CONFIG_SYS_ATMEL_SECT;
174 int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
177 if (base != CONFIG_SYS_ATMEL_BASE)
180 info->flash_id = 0x01000000;
183 info->buffer_size = 1;
184 info->erase_blk_tout = 16384;
185 info->write_tout = 2;
186 info->buffer_write_tout = 5;
187 info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
188 info->cmd_reset = 0x00F0;
189 info->interface = FLASH_CFI_X8;
190 info->legacy_unlock = 0;
191 info->manufacturer_id = (u16) ATM_MANUFACT;
192 info->device_id = ATM_ID_LV040;
193 info->device_id2 = 0;
196 info->cfi_version = 0x3133;
197 info->cfi_offset = 0x0000;
198 info->addr_unlock1 = 0x00000555;
199 info->addr_unlock2 = 0x000002AA;
200 info->name = "CFI conformant";
203 info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
204 info->start[0] = base;
205 for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
206 info->size += sect[i] * sectsz[i];
208 for (j = 0; j < sect[i]; j++, k++) {
209 info->start[k + 1] = info->start[k] + sectsz[i];
210 info->protect[k] = 0;
216 #endif /* CONFIG_SYS_FLASH_CFI */