1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/fsl_serdes.h>
15 #include <asm/arch/ppa.h>
16 #include <asm/arch/fdt.h>
17 #include <asm/arch/mmu.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/arch-fsl-layerscape/fsl_icid.h>
26 #include <fsl_esdhc.h>
30 #include "../common/qixis.h"
31 #include "ls1043aqds_qixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
39 /* LS1043AQDS serdes mux */
40 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
41 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
42 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
43 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
44 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
45 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
46 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
47 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
48 #define CFG_UART_MUX_MASK 0x6
49 #define CFG_UART_MUX_SHIFT 1
50 #define CFG_LPUART_EN 0x1
53 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
57 CONFIG_SYS_NOR0_CSPR_EXT,
71 CONFIG_SYS_NOR1_CSPR_EXT,
84 CONFIG_SYS_NAND_CSPR_EXT,
85 CONFIG_SYS_NAND_AMASK,
88 CONFIG_SYS_NAND_FTIM0,
89 CONFIG_SYS_NAND_FTIM1,
90 CONFIG_SYS_NAND_FTIM2,
97 CONFIG_SYS_FPGA_CSPR_EXT,
98 CONFIG_SYS_FPGA_AMASK,
101 CONFIG_SYS_FPGA_FTIM0,
102 CONFIG_SYS_FPGA_FTIM1,
103 CONFIG_SYS_FPGA_FTIM2,
104 CONFIG_SYS_FPGA_FTIM3
109 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
112 CONFIG_SYS_NAND_CSPR,
113 CONFIG_SYS_NAND_CSPR_EXT,
114 CONFIG_SYS_NAND_AMASK,
115 CONFIG_SYS_NAND_CSOR,
117 CONFIG_SYS_NAND_FTIM0,
118 CONFIG_SYS_NAND_FTIM1,
119 CONFIG_SYS_NAND_FTIM2,
120 CONFIG_SYS_NAND_FTIM3
125 CONFIG_SYS_NOR0_CSPR,
126 CONFIG_SYS_NOR0_CSPR_EXT,
127 CONFIG_SYS_NOR_AMASK,
130 CONFIG_SYS_NOR_FTIM0,
131 CONFIG_SYS_NOR_FTIM1,
132 CONFIG_SYS_NOR_FTIM2,
138 CONFIG_SYS_NOR1_CSPR,
139 CONFIG_SYS_NOR1_CSPR_EXT,
140 CONFIG_SYS_NOR_AMASK,
143 CONFIG_SYS_NOR_FTIM0,
144 CONFIG_SYS_NOR_FTIM1,
145 CONFIG_SYS_NOR_FTIM2,
151 CONFIG_SYS_FPGA_CSPR,
152 CONFIG_SYS_FPGA_CSPR_EXT,
153 CONFIG_SYS_FPGA_AMASK,
154 CONFIG_SYS_FPGA_CSOR,
156 CONFIG_SYS_FPGA_FTIM0,
157 CONFIG_SYS_FPGA_FTIM1,
158 CONFIG_SYS_FPGA_FTIM2,
159 CONFIG_SYS_FPGA_FTIM3
164 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
166 enum boot_src src = get_boot_src();
168 if (src == BOOT_SOURCE_IFC_NAND)
169 regs_info->regs = ifc_cfg_nand_boot;
171 regs_info->regs = ifc_cfg_nor_boot;
172 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
178 #ifdef CONFIG_TFABOOT
179 enum boot_src src = get_boot_src();
182 #ifndef CONFIG_SD_BOOT
186 puts("Board: LS1043AQDS, boot from ");
188 #ifdef CONFIG_TFABOOT
189 if (src == BOOT_SOURCE_SD_MMC)
194 #ifdef CONFIG_SD_BOOT
197 sw = QIXIS_READ(brdcfg[0]);
198 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
201 printf("vBank: %d\n", sw);
209 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
212 #ifdef CONFIG_TFABOOT
215 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
216 QIXIS_READ(id), QIXIS_READ(arch));
218 printf("FPGA: v%d (%s), build %d\n",
219 (int)QIXIS_READ(scver), qixis_read_tag(buf),
220 (int)qixis_read_minor());
225 bool if_board_diff_clk(void)
227 u8 diff_conf = QIXIS_READ(brdcfg[11]);
229 return diff_conf & 0x40;
232 unsigned long get_board_sys_clk(void)
234 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
236 switch (sysclk_conf & 0x0f) {
237 case QIXIS_SYSCLK_64:
239 case QIXIS_SYSCLK_83:
241 case QIXIS_SYSCLK_100:
243 case QIXIS_SYSCLK_125:
245 case QIXIS_SYSCLK_133:
247 case QIXIS_SYSCLK_150:
249 case QIXIS_SYSCLK_160:
251 case QIXIS_SYSCLK_166:
258 unsigned long get_board_ddr_clk(void)
260 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
262 if (if_board_diff_clk())
263 return get_board_sys_clk();
264 switch ((ddrclk_conf & 0x30) >> 4) {
265 case QIXIS_DDRCLK_100:
267 case QIXIS_DDRCLK_125:
269 case QIXIS_DDRCLK_133:
276 int select_i2c_ch_pca9547(u8 ch, int bus_num)
283 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
286 printf("%s: Cannot find udev for a bus %d\n", __func__,
290 ret = dm_i2c_write(dev, 0, &ch, 1);
292 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
295 puts("PCA: failed to select proper channel\n");
305 * When resuming from deep sleep, the I2C channel may not be
306 * in the default channel. So, switch to the default channel
307 * before accessing DDR SPD.
309 * PCA9547 mount on I2C1 bus
311 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
313 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
314 defined(CONFIG_SPL_BUILD)
315 /* This will break-before-make MMU for DDR */
316 update_early_mmu_table();
322 int i2c_multiplexer_select_vid_channel(u8 channel)
324 return select_i2c_ch_pca9547(channel, 0);
327 void board_retimer_init(void)
332 /* Retimer is connected to I2C1_CH7_CH5 */
333 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
339 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
342 printf("%s: Cannot find udev for a bus %d\n", __func__,
346 dm_i2c_write(dev, 0, ®, 1);
348 /* Access to Control/Shared register */
349 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
352 printf("%s: Cannot find udev for a bus %d\n", __func__,
358 dm_i2c_write(dev, 0xff, ®, 1);
360 /* Read device revision and ID */
361 dm_i2c_read(dev, 1, ®, 1);
362 debug("Retimer version id = 0x%x\n", reg);
364 /* Enable Broadcast. All writes target all channel register sets */
366 dm_i2c_write(dev, 0xff, ®, 1);
368 /* Reset Channel Registers */
369 dm_i2c_read(dev, 0, ®, 1);
371 dm_i2c_write(dev, 0, ®, 1);
373 /* Enable override divider select and Enable Override Output Mux */
374 dm_i2c_read(dev, 9, ®, 1);
376 dm_i2c_write(dev, 9, ®, 1);
378 /* Select VCO Divider to full rate (000) */
379 dm_i2c_read(dev, 0x18, ®, 1);
381 dm_i2c_write(dev, 0x18, ®, 1);
383 /* Selects active PFD MUX Input as Re-timed Data (001) */
384 dm_i2c_read(dev, 0x1e, ®, 1);
387 dm_i2c_write(dev, 0x1e, ®, 1);
389 /* Set data rate as 10.3125 Gbps */
391 dm_i2c_write(dev, 0x60, ®, 1);
393 dm_i2c_write(dev, 0x61, ®, 1);
395 dm_i2c_write(dev, 0x62, ®, 1);
397 dm_i2c_write(dev, 0x63, ®, 1);
399 dm_i2c_write(dev, 0x64, ®, 1);
401 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
403 /* Access to Control/Shared register */
405 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
407 /* Read device revision and ID */
408 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
409 debug("Retimer version id = 0x%x\n", reg);
411 /* Enable Broadcast. All writes target all channel register sets */
413 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
415 /* Reset Channel Registers */
416 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
418 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
420 /* Enable override divider select and Enable Override Output Mux */
421 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
423 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
425 /* Select VCO Divider to full rate (000) */
426 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
428 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
430 /* Selects active PFD MUX Input as Re-timed Data (001) */
431 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
434 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
436 /* Set data rate as 10.3125 Gbps */
438 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
440 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
442 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
444 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
446 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
449 /* Return the default channel */
450 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
453 int board_early_init_f(void)
455 #ifdef CONFIG_HAS_FSL_XHCI_USB
456 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
463 #ifdef CONFIG_SYS_I2C
464 #ifdef CONFIG_SYS_I2C_EARLY_INIT
468 fsl_lsch2_early_init_f();
470 #ifdef CONFIG_HAS_FSL_XHCI_USB
471 out_be32(&scfg->rcwpmuxcr0, 0x3333);
472 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
474 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
475 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
476 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
477 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
481 /* We use lpuart0 as system console */
482 uart = QIXIS_READ(brdcfg[14]);
483 uart &= ~CFG_UART_MUX_MASK;
484 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
485 QIXIS_WRITE(brdcfg[14], uart);
491 #ifdef CONFIG_FSL_DEEP_SLEEP
492 /* determine if it is a warm boot */
493 bool is_warm_boot(void)
495 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
496 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
498 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
505 int config_board_mux(int ctrl_type)
509 reg14 = QIXIS_READ(brdcfg[14]);
513 reg14 = (reg14 & (~0x30)) | 0x20;
516 puts("Unsupported mux interface type\n");
520 QIXIS_WRITE(brdcfg[14], reg14);
525 int config_serdes_mux(void)
531 #ifdef CONFIG_MISC_INIT_R
532 int misc_init_r(void)
534 if (hwconfig("gpio"))
535 config_board_mux(MUX_TYPE_GPIO);
543 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
547 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
548 board_retimer_init();
550 #ifdef CONFIG_SYS_FSL_SERDES
554 #ifdef CONFIG_FSL_LS_PPA
561 #ifdef CONFIG_OF_BOARD_SETUP
562 int ft_board_setup(void *blob, bd_t *bd)
564 u64 base[CONFIG_NR_DRAM_BANKS];
565 u64 size[CONFIG_NR_DRAM_BANKS];
568 /* fixup DT for the two DDR banks */
569 base[0] = gd->bd->bi_dram[0].start;
570 size[0] = gd->bd->bi_dram[0].size;
571 base[1] = gd->bd->bi_dram[1].start;
572 size[1] = gd->bd->bi_dram[1].size;
574 fdt_fixup_memory_banks(blob, base, size, 2);
575 ft_cpu_setup(blob, bd);
577 #ifdef CONFIG_SYS_DPAA_FMAN
578 fdt_fixup_fman_ethernet(blob);
579 fdt_fixup_board_enet(blob);
582 fdt_fixup_icid(blob);
584 reg = QIXIS_READ(brdcfg[0]);
585 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
587 /* Disable IFC if QSPI is enabled */
589 do_fixup_by_compat(blob, "fsl,ifc",
590 "status", "disabled", 8 + 1, 1);
596 u8 flash_read8(void *addr)
598 return __raw_readb(addr + 1);
601 void flash_write16(u16 val, void *addr)
603 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
605 __raw_writew(shftval, addr);
608 u16 flash_read16(void *addr)
610 u16 val = __raw_readw(addr);
612 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
615 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
616 void *env_sf_get_env_addr(void)
618 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);