1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #ifdef CONFIG_FSL_LS_PPA
15 #include <asm/arch/ppa.h>
17 #include <asm/arch/fdt.h>
18 #include <asm/arch/mmu.h>
19 #include <asm/arch/soc.h>
23 #include <env_internal.h>
26 #include <fsl_esdhc.h>
31 #include "../common/qixis.h"
32 #include "ls1012aqds_qixis.h"
33 #include "ls1012aqds_pfe.h"
35 DECLARE_GLOBAL_DATA_PTR;
42 sw = QIXIS_READ(arch);
43 printf("Board Arch: V%d, ", sw >> 4);
44 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
46 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
48 if (sw & QIXIS_LBMAP_ALTBANK)
53 printf("FPGA: v%d (%s), build %d",
54 (int)QIXIS_READ(scver), qixis_read_tag(buf),
55 (int)qixis_read_minor());
57 /* the timestamp string contains "\n" at the end */
58 printf(" on %s", qixis_read_time(buf));
65 gd->ram_size = tfa_get_dram_size();
67 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
74 static const struct fsl_mmdc_info mparam = {
75 0x05180000, /* mdctl */
76 0x00030035, /* mdpdc */
77 0x12554000, /* mdotc */
78 0xbabf7954, /* mdcfg0 */
79 0xdb328f64, /* mdcfg1 */
80 0x01ff00db, /* mdcfg2 */
81 0x00001680, /* mdmisc */
82 0x0f3c8000, /* mdref */
83 0x00002000, /* mdrwd */
84 0x00bf1023, /* mdor */
85 0x0000003f, /* mdasp */
86 0x0000022a, /* mpodtctrl */
87 0xa1390003, /* mpzqhwctrl */
91 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
92 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
93 /* This will break-before-make MMU for DDR */
94 update_early_mmu_table();
101 int board_early_init_f(void)
103 fsl_lsch2_early_init_f();
108 #ifdef CONFIG_MISC_INIT_R
109 int misc_init_r(void)
111 u8 mux_sdhc_cd = 0x80;
118 ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
121 printf("%s: Cannot find udev for a bus %d\n", __func__,
125 dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
127 i2c_set_bus_num(bus_num);
129 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
138 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
139 CONFIG_SYS_CCI400_OFFSET);
141 /* Set CCI-400 control override register to enable barrier
143 if (current_el() == 3)
144 out_le32(&cci->ctrl_ord,
145 CCI400_CTRLORD_EN_BARRIER);
147 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
151 #ifdef CONFIG_ENV_IS_NOWHERE
152 gd->env_addr = (ulong)&default_environment[0];
155 #ifdef CONFIG_FSL_CAAM
159 #ifdef CONFIG_FSL_LS_PPA
165 int esdhc_status_fixup(void *blob, const char *compat)
167 char esdhc0_path[] = "/soc/esdhc@1560000";
168 char esdhc1_path[] = "/soc/esdhc@1580000";
171 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
175 * The Presence Detect 2 register detects the installation
176 * of cards in various PCI Express or SGMII slots.
178 * STAT_PRS2[7:5]: Specifies the type of card installed in the
179 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
181 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
183 /* If no adapter is installed in SDHC2, disable SDHC2 */
185 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
186 sizeof("disabled"), 1);
188 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
193 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
194 char *enet_path, char *mdio_path)
196 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
197 &prop_val.busid, PFE_PROP_LEN, 1);
198 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
199 &prop_val.phyid, PFE_PROP_LEN, 1);
200 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
201 &prop_val.mux_val, PFE_PROP_LEN, 1);
202 do_fixup_by_path(set_blob, enet_path, "phy-mode",
203 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
204 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
205 &prop_val.phy_mask, PFE_PROP_LEN, 1);
209 static void fdt_fsl_fixup_of_pfe(void *blob)
212 struct pfe_prop_val prop_val;
215 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
216 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
217 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
218 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
220 for (i = 0; i < NUM_ETH_NODE; i++) {
222 case SERDES_1_G_PROTOCOL:
224 prop_val.busid = cpu_to_fdt32(
226 prop_val.phyid = cpu_to_fdt32(
228 prop_val.mux_val = cpu_to_fdt32(
230 prop_val.phy_mask = cpu_to_fdt32(
231 ETH_1G_MDIO_PHY_MASK);
232 prop_val.phy_mode = "sgmii";
233 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
236 prop_val.busid = cpu_to_fdt32(
238 prop_val.phyid = cpu_to_fdt32(
240 prop_val.mux_val = cpu_to_fdt32(
242 prop_val.phy_mask = cpu_to_fdt32(
243 ETH_1G_MDIO_PHY_MASK);
244 prop_val.phy_mode = "rgmii";
245 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
249 case SERDES_2_5_G_PROTOCOL:
251 prop_val.busid = cpu_to_fdt32(
253 prop_val.phyid = cpu_to_fdt32(
255 prop_val.mux_val = cpu_to_fdt32(
256 ETH_1_2_5G_MDIO_MUX);
257 prop_val.phy_mask = cpu_to_fdt32(
258 ETH_2_5G_MDIO_PHY_MASK);
259 prop_val.phy_mode = "sgmii-2500";
260 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
263 prop_val.busid = cpu_to_fdt32(
265 prop_val.phyid = cpu_to_fdt32(
267 prop_val.mux_val = cpu_to_fdt32(
268 ETH_2_2_5G_MDIO_MUX);
269 prop_val.phy_mask = cpu_to_fdt32(
270 ETH_2_5G_MDIO_PHY_MASK);
271 prop_val.phy_mode = "sgmii-2500";
272 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
277 printf("serdes:[%d]\n", srds_s1);
282 #ifdef CONFIG_OF_BOARD_SETUP
283 int ft_board_setup(void *blob, bd_t *bd)
285 arch_fixup_fdt(blob);
287 ft_cpu_setup(blob, bd);
288 fdt_fsl_fixup_of_pfe(blob);