1 // SPDX-License-Identifier: GPL-2.0+
3 * Creative ZEN X-Fi3 board
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
7 * Hardware investigation done by:
9 * Amaury Pouly <amaury.pouly@gmail.com>
18 #include <asm/arch/iomux-mx23.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/sys_proto.h>
23 DECLARE_GLOBAL_DATA_PTR;
28 int board_early_init_f(void)
30 /* IO0 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK0, 480000);
33 /* SSP0 clock at 96MHz */
34 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
41 return mxs_dram_init();
45 static int xfi3_mmc_cd(int id)
49 /* The SSP_DETECT is inverted on this board. */
50 return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
52 /* Phison bridge always present */
59 int board_mmc_init(bd_t *bis)
64 gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
65 gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
66 ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
70 /* Phison SD-NAND bridge */
71 ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
77 #ifdef CONFIG_VIDEO_MXS
78 static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
80 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
81 const unsigned int timeout = 0x10000;
83 if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
87 writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
88 (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
89 ®s->hw_lcdif_transfer_count);
91 writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
92 ®s->hw_lcdif_ctrl_clr);
95 writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
97 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
99 if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
103 writel(payload, ®s->hw_lcdif_data);
104 return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
108 static void mxsfb_write_register(uint32_t reg, uint32_t data)
110 mxsfb_write_byte(reg, 0);
111 mxsfb_write_byte(data, 1);
114 static const struct {
121 /* Writing 0x30 to reg. 0x03 flips the LCD */
124 /* This can contain 0x111 to rotate the LCD. */
128 { 0x21, 30, 0x0000 },
129 /* Wait 30 mS here */
131 { 0x11, 30, 0x1038 },
132 /* Wait 30 mS here */
155 { 0x59, 30, 0x0a09 },
156 /* Wait 30 mS here */
157 { 0x07, 30, 0x1017 },
158 /* Wait 40 mS here */
167 void mxsfb_system_setup(void)
169 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
172 /* Switch the LCDIF into System-Mode */
173 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
174 LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
176 /* Restart the SmartLCD controller */
178 writel(1, ®s->hw_lcdif_ctrl1_set);
180 writel(1, ®s->hw_lcdif_ctrl1_clr);
182 writel(1, ®s->hw_lcdif_ctrl1_set);
185 /* Program the SmartLCD controller */
186 writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
188 writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
189 (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
190 (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
191 (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
192 ®s->hw_lcdif_timing);
195 * OTM2201A init and configuration sequence.
197 for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
198 mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
199 if (lcd_regs[i].delay)
200 mdelay(lcd_regs[i].delay);
202 /* Turn on Framebuffer Upload Mode */
203 mxsfb_write_byte(0x22, 0);
205 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
206 ®s->hw_lcdif_ctrl_set);
212 /* Adress of boot parameters */
213 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
215 /* Turn on PWM backlight */
216 gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
221 int board_eth_init(bd_t *bis)
223 usb_eth_initialize(bis);