1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot board functions for CompuLab CL-SOM-iMX7 module
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
17 #include <fsl_esdhc_imx.h>
18 #include <power/pmic.h>
19 #include <power/pfuze3000_pmic.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/iomux-v3.h>
22 #include <asm/arch-mx7/mx7-pins.h>
23 #include <asm/arch-mx7/sys_proto.h>
24 #include <asm/arch-mx7/clock.h>
25 #include "../common/eeprom.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #ifdef CONFIG_SYS_I2C_MXC
32 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
35 #define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6)
36 #define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7)
38 static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
40 .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
41 MUX_PAD_CTRL(I2C_PAD_CTRL),
42 .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
43 MUX_PAD_CTRL(I2C_PAD_CTRL),
44 .gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
47 .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
48 MUX_PAD_CTRL(I2C_PAD_CTRL),
49 .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
50 MUX_PAD_CTRL(I2C_PAD_CTRL),
51 .gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
56 * cl_som_imx7_setup_i2c() - I2C pinmux configuration.
58 static void cl_som_imx7_setup_i2c(void)
60 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
62 #else /* !CONFIG_SYS_I2C_MXC */
63 static void cl_som_imx7_setup_i2c(void) {}
64 #endif /* CONFIG_SYS_I2C_MXC */
68 gd->ram_size = imx_ddr_size();
73 #ifdef CONFIG_FSL_ESDHC_IMX
75 #define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
77 static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
78 {USDHC1_BASE_ADDR, 0, 4},
82 int board_mmc_init(bd_t *bis)
86 * According to the board_mmc_init() the following map is done:
87 * (U-boot device node) (Physical Port)
91 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
94 cl_som_imx7_usdhc1_pads_set();
95 gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
96 cl_som_imx7_usdhc_cfg[0].sdhc_clk =
97 mxc_get_clock(MXC_ESDHC_CLK);
100 cl_som_imx7_usdhc3_emmc_pads_set();
101 gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
102 gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
104 gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
105 cl_som_imx7_usdhc_cfg[1].sdhc_clk =
106 mxc_get_clock(MXC_ESDHC3_CLK);
109 printf("Warning: you configured more USDHC controllers "
110 "(%d) than supported by the board\n", i + 1);
114 ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
121 #endif /* CONFIG_FSL_ESDHC_IMX */
123 #ifdef CONFIG_FEC_MXC
125 #define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4)
128 * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
130 static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
134 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
135 * which cause ethernet link down/up issue, so disable SmartEEE
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
139 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
142 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
144 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
146 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
149 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
152 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
154 /* introduce tx clock delay */
155 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
156 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
158 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
161 int board_phy_config(struct phy_device *phydev)
163 cl_som_imx7_rgmii_rework(phydev);
165 if (phydev->drv->config)
166 phydev->drv->config(phydev);
172 * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
174 * @env_var: MAC address environment variable
175 * @eeprom_bus: I2C bus of the environment EEPROM
177 * @return: 0 on success, < 0 on failure
179 static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
182 unsigned char enetaddr[6];
184 ret = eth_env_get_enetaddr(env_var, enetaddr);
188 ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
192 ret = is_valid_ethaddr(enetaddr);
196 return eth_env_set_enetaddr(env_var, enetaddr);
199 #define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
201 int board_eth_init(bd_t *bis)
203 /* set Ethernet MAC address environment */
204 cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
205 /* Ethernet interface pinmux configuration */
206 cl_som_imx7_phy1_rst_pads_set();
207 cl_som_imx7_fec1_pads_set();
209 gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
210 gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
212 gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
213 /* MAC initialization */
214 return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
215 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
219 * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
220 * - ENET1 reference clock mode select.
221 * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
223 static void cl_som_imx7_setup_fec(void)
225 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
226 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
228 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
229 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
230 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
231 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
233 set_clk_enet(ENET_125MHZ);
235 #else /* !CONFIG_FEC_MXC */
236 static void cl_som_imx7_setup_fec(void) {}
237 #endif /* CONFIG_FEC_MXC */
241 static void cl_som_imx7_spi_init(void)
243 cl_som_imx7_espi1_pads_set();
245 #else /* !CONFIG_SPI */
246 static void cl_som_imx7_spi_init(void) {}
247 #endif /* CONFIG_SPI */
249 int board_early_init_f(void)
251 cl_som_imx7_uart1_pads_set();
252 cl_som_imx7_usb_otg1_pads_set();
259 /* address of boot parameters */
260 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
261 cl_som_imx7_setup_i2c();
262 cl_som_imx7_setup_fec();
263 cl_som_imx7_spi_init();
270 int power_init_board(void)
274 unsigned int reg, rev_id;
276 ret = power_pfuze3000_init(I2C_PMIC);
280 p = pmic_get("PFUZE3000");
285 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
286 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
287 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
289 /* disable Low Power Mode during standby mode */
290 pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
294 #endif /* CONFIG_POWER */
297 * cl_som_imx7_setup_wdog() - watchdog configuration.
298 * - Output WDOG_B signal to reset external pmic.
299 * - Suspend the watchdog timer during low-power modes.
301 void cl_som_imx7_setup_wdog(void)
303 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
305 cl_som_imx7_wdog_pads_set();
306 set_wdog_reset(wdog);
308 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
309 * since we use PMIC_PWRON to reset the board.
311 clrsetbits_le16(&wdog->wcr, 0, 0x10);
314 int board_late_init(void)
316 env_set("board_name", "CL-SOM-iMX7");
317 cl_som_imx7_setup_wdog();
325 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
330 printf("Board: CL-SOM-iMX7 in %s mode\n", mode);