board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <image.h>
  13 #include <init.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <linux/errno.h>
  19 #include <asm/gpio.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <asm/arch/crm_regs.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <bmp_logo.h>
  27 #include <dm/root.h>
  28 #include <env.h>
  29 #include <i2c_eeprom.h>
  30 #include <i2c.h>
  31 #include <micrel.h>
  32 #include <miiphy.h>
  33 #include <lcd.h>
  34 #include <led.h>
  35 #include <power/pmic.h>
  36 #include <power/regulator.h>
  37 #include <power/da9063_pmic.h>
  38 #include <splash.h>
  39 #include <video_fb.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 enum {
  44         BOARD_TYPE_4 = 4,
  45         BOARD_TYPE_7 = 7,
  46 };
  47
  48 #define ARI_BT_4 "aristainetos2_4@2"
  49 #define ARI_BT_7 "aristainetos2_7@1"
  50
  51 int board_phy_config(struct phy_device *phydev)
  52 {
  53         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  54         ksz9031_phy_extended_write(phydev, 0x02,
  55                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  56                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  57         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  58         ksz9031_phy_extended_write(phydev, 0x02,
  59                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  60                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  61         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  62         ksz9031_phy_extended_write(phydev, 0x02,
  63                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  64                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  65         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  66         ksz9031_phy_extended_write(phydev, 0x02,
  67                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  68                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  69
  70         if (phydev->drv->config)
  71                 phydev->drv->config(phydev);
  72
  73         return 0;
  74 }
  75
  76 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  77 {
  78         int   i, j;
  79
  80         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  81                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  82                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  83                         in[i * BMP_LOGO_WIDTH + j];
  84         return 0;
  85 }
  86
  87 /*
  88  * Rotate the BMP_LOGO (only)
  89  * Will only work, if the logo is square, as
  90  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  91  */
  92 void rotate_logo(int rotations)
  93 {
  94         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  95         struct bmp_header *header;
  96         unsigned char *in_logo;
  97         int   i, j;
  98
  99         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 100                 return;
 101
 102         header = (struct bmp_header *)bmp_logo_bitmap;
 103         in_logo = bmp_logo_bitmap + header->data_offset;
 104
 105         /* one 90 degree rotation */
 106         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 107                 rotate_logo_one(out_logo, in_logo);
 108
 109         /* second 90 degree rotation */
 110         if (rotations == 2  ||  rotations == 3)
 111                 rotate_logo_one(in_logo, out_logo);
 112
 113         /* third 90 degree rotation */
 114         if (rotations == 3)
 115                 rotate_logo_one(out_logo, in_logo);
 116
 117         /* copy result back to original array */
 118         if (rotations == 1  ||  rotations == 3)
 119                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 120                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 121                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 122                                 out_logo[i * BMP_LOGO_WIDTH + j];
 123 }
 124
 125 static void enable_lvds(struct display_info_t const *dev)
 126 {
 127         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 128         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 129         int reg;
 130         s32 timeout = 100000;
 131
 132         /* set PLL5 clock */
 133         reg = readl(&ccm->analog_pll_video);
 134         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 135         writel(reg, &ccm->analog_pll_video);
 136
 137         /* set PLL5 to 232720000Hz */
 138         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 139         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 140         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 141         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 142         writel(reg, &ccm->analog_pll_video);
 143
 144         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 145                &ccm->analog_pll_video_num);
 146         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 147                &ccm->analog_pll_video_denom);
 148
 149         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 150         writel(reg, &ccm->analog_pll_video);
 151
 152         while (timeout--)
 153                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 154                         break;
 155         if (timeout < 0)
 156                 printf("Warning: video pll lock timeout!\n");
 157
 158         reg = readl(&ccm->analog_pll_video);
 159         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 160         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 161         writel(reg, &ccm->analog_pll_video);
 162
 163         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 164         reg = readl(&ccm->cs2cdr);
 165         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 166                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 167         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 168                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 169         writel(reg, &ccm->cs2cdr);
 170
 171         reg = readl(&ccm->cscmr2);
 172         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 173         writel(reg, &ccm->cscmr2);
 174
 175         reg = readl(&ccm->chsccdr);
 176         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 177                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 178         writel(reg, &ccm->chsccdr);
 179
 180         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 181               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 182               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 183               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 184               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 185               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 186               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 187         writel(reg, &iomux->gpr[2]);
 188
 189         reg = readl(&iomux->gpr[3]);
 190         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 191                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 192                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 193         writel(reg, &iomux->gpr[3]);
 194 }
 195
 196 static void enable_spi_display(struct display_info_t const *dev)
 197 {
 198         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 199         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 200         int reg;
 201         s32 timeout = 100000;
 202
 203 #if defined(CONFIG_VIDEO_BMP_LOGO)
 204         rotate_logo(3);  /* portrait display in landscape mode */
 205 #endif
 206
 207         reg = readl(&ccm->cs2cdr);
 208
 209         /* select pll 5 clock */
 210         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 211                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 212         writel(reg, &ccm->cs2cdr);
 213
 214         /* set PLL5 to 197994996Hz */
 215         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 216         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 217         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 218         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 219         writel(reg, &ccm->analog_pll_video);
 220
 221         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 222                &ccm->analog_pll_video_num);
 223         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 224                &ccm->analog_pll_video_denom);
 225
 226         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 227         writel(reg, &ccm->analog_pll_video);
 228
 229         while (timeout--)
 230                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 231                         break;
 232         if (timeout < 0)
 233                 printf("Warning: video pll lock timeout!\n");
 234
 235         reg = readl(&ccm->analog_pll_video);
 236         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 237         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 238         writel(reg, &ccm->analog_pll_video);
 239
 240         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 241         reg = readl(&ccm->cs2cdr);
 242         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 243                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 244         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 245                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 246         writel(reg, &ccm->cs2cdr);
 247
 248         reg = readl(&ccm->cscmr2);
 249         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 250         writel(reg, &ccm->cscmr2);
 251
 252         reg = readl(&ccm->chsccdr);
 253         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 254                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 255         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 256         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 257         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 258         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 259         writel(reg, &ccm->chsccdr);
 260
 261         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 262               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 263               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 264               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 265               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 266               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 267               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 268         writel(reg, &iomux->gpr[2]);
 269
 270         reg = readl(&iomux->gpr[3]);
 271         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 272                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 273                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 274         writel(reg, &iomux->gpr[3]);
 275 }
 276
 277 static void setup_display(void)
 278 {
 279         enable_ipu_clock();
 280 }
 281
 282 static void set_gpr_register(void)
 283 {
 284         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 285
 286         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 287                IOMUXC_GPR1_EXC_MON_SLVE |
 288                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 289                IOMUXC_GPR1_ACT_CS0,
 290                &iomuxc_regs->gpr[1]);
 291         writel(0x0, &iomuxc_regs->gpr[8]);
 292         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 293                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 294                &iomuxc_regs->gpr[12]);
 295 }
 296
 297 extern char __bss_start[], __bss_end[];
 298 int board_early_init_f(void)
 299 {
 300         select_ldb_di_clock_source(MXC_PLL5_CLK);
 301         set_gpr_register();
 302
 303         /*
 304          * clear bss here, so we can use spi driver
 305          * before relocation and read Environment
 306          * from spi flash.
 307          */
 308         memset(__bss_start, 0x00, __bss_end - __bss_start);
 309
 310         return 0;
 311 }
 312
 313 static void setup_one_led(char *label, int state)
 314 {
 315         struct udevice *dev;
 316         int ret;
 317
 318         ret = led_get_by_label(label, &dev);
 319         if (ret == 0)
 320                 led_set_state(dev, state);
 321 }
 322
 323 static void setup_board_gpio(void)
 324 {
 325         setup_one_led("led_ena", LEDST_ON);
 326         /* switch off Status LEDs */
 327         setup_one_led("led_yellow", LEDST_OFF);
 328         setup_one_led("led_red", LEDST_OFF);
 329         setup_one_led("led_green", LEDST_OFF);
 330         setup_one_led("led_blue", LEDST_OFF);
 331 }
 332
 333 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
 334                 " rescueReason=%d "
 335
 336 static void aristainetos_run_rescue_command(int reason)
 337 {
 338         char rescue_reason_command[80];
 339
 340         sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
 341         run_command(rescue_reason_command, 0);
 342 }
 343
 344 static int aristainetos_eeprom(void)
 345 {
 346         struct udevice *dev;
 347         int off;
 348         int ret;
 349         u8 data[0x10];
 350         u8 rescue_reason;
 351
 352         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 353         if (off < 0) {
 354                 printf("%s: No eeprom0 path offset\n", __func__);
 355                 return off;
 356         }
 357
 358         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 359         if (ret) {
 360                 printf("%s: Could not find EEPROM\n", __func__);
 361                 return ret;
 362         }
 363
 364         ret = i2c_set_chip_offset_len(dev, 2);
 365         if (ret)
 366                 return ret;
 367
 368         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
 369         if (ret) {
 370                 printf("%s: Could not read EEPROM\n", __func__);
 371                 return ret;
 372         }
 373
 374         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 375                 rescue_reason = *(uint8_t *)&data[9];
 376                 memset(&data[3], 0xff, 7);
 377                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 378                 printf("\nBooting into Rescue System (EEPROM)\n");
 379                 aristainetos_run_rescue_command(rescue_reason);
 380                 run_command("run rescue_load_fit rescueboot", 0);
 381         } else if (strncmp((char *)data, "DeF", 3) == 0) {
 382                 memset(data, 0xff, 3);
 383                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 384                 printf("\nClear u-boot environment (set back to defaults)\n");
 385                 run_command("run default_env; saveenv; saveenv", 0);
 386         }
 387
 388         return 0;
 389 };
 390
 391 static void aristainetos_bootmode_settings(void)
 392 {
 393         struct gpio_desc *desc;
 394         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 395         unsigned int sbmr1 = readl(&psrc->sbmr1);
 396         char *my_bootdelay;
 397         char bootmode = 0;
 398         int ret;
 399
 400         /*
 401          * Check the boot-source. If booting from NOR Flash,
 402          * disable bootdelay
 403          */
 404         ret = gpio_hog_lookup_name("bootsel0", &desc);
 405         if (!ret)
 406                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 407         ret = gpio_hog_lookup_name("bootsel1", &desc);
 408         if (!ret)
 409                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 410         ret = gpio_hog_lookup_name("bootsel2", &desc);
 411         if (!ret)
 412                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 413
 414         if (bootmode == 7) {
 415                 my_bootdelay = env_get("nor_bootdelay");
 416                 if (my_bootdelay)
 417                         env_set("bootdelay", my_bootdelay);
 418                 else
 419                         env_set("bootdelay", "-2");
 420         }
 421
 422         if (sbmr1 & 0x40) {
 423                 env_set("bootmode", "1");
 424                 printf("SD bootmode jumper set!\n");
 425         } else {
 426                 env_set("bootmode", "0");
 427         }
 428
 429         /* read out some jumper values*/
 430         ret = gpio_hog_lookup_name("env_reset", &desc);
 431         if (!ret) {
 432                 if (dm_gpio_get_value(desc)) {
 433                         printf("\nClear env (set back to defaults)\n");
 434                         run_command("run default_env; saveenv; saveenv", 0);
 435                 }
 436         }
 437         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 438         if (!ret) {
 439                 if (dm_gpio_get_value(desc)) {
 440                         aristainetos_run_rescue_command(16);
 441                         run_command("run rescue_xload_boot", 0);
 442                 }
 443         }
 444 }
 445
 446 #if defined(CONFIG_DM_PMIC_DA9063)
 447 /*
 448  * On the aristainetos2c boards the PMIC needs to be initialized,
 449  * because the Ethernet PHY uses a different regulator that is not
 450  * setup per hardware default. This does not influence the other versions
 451  * as this regulator isn't used there at all.
 452  *
 453  * Unfortunately we have not yet a interface to setup all
 454  * values we need.
 455  */
 456 static int setup_pmic_voltages(void)
 457 {
 458         struct udevice *dev;
 459         int off;
 460         int ret;
 461
 462         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 463         if (off < 0) {
 464                 printf("%s: No pmic path offset\n", __func__);
 465                 return off;
 466         }
 467
 468         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 469         if (ret) {
 470                 printf("%s: Could not find PMIC\n", __func__);
 471                 return ret;
 472         }
 473
 474         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 475         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 476         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 477         if (ret < 0) {
 478                 printf("%s: error %d get register\n", __func__, ret);
 479                 return ret;
 480         }
 481         ret &= 0xf0;
 482         ret |= 0x09;
 483         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 484         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 485         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 486
 487         return 0;
 488 }
 489 #else
 490 static int setup_pmic_voltages(void)
 491 {
 492         return 0;
 493 }
 494 #endif
 495
 496 int board_late_init(void)
 497 {
 498         int x, y;
 499
 500         led_default_state();
 501         splash_get_pos(&x, &y);
 502         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 503
 504         aristainetos_bootmode_settings();
 505
 506         /* eeprom work */
 507         aristainetos_eeprom();
 508
 509         /* set board_type */
 510         if (gd->board_type == BOARD_TYPE_4)
 511                 env_set("board_type", ARI_BT_4);
 512         else
 513                 env_set("board_type", ARI_BT_7);
 514
 515         if (setup_pmic_voltages())
 516                 printf("Error setup PMIC\n");
 517
 518         return 0;
 519 }
 520
 521 int dram_init(void)
 522 {
 523         gd->ram_size = imx_ddr_size();
 524
 525         return 0;
 526 }
 527
 528 struct display_info_t const displays[] = {
 529         {
 530                 .bus    = -1,
 531                 .addr   = 0,
 532                 .pixfmt = IPU_PIX_FMT_RGB24,
 533                 .detect = NULL,
 534                 .enable = enable_lvds,
 535                 .mode   = {
 536                         .name           = "lb07wv8",
 537                         .refresh        = 60,
 538                         .xres           = 800,
 539                         .yres           = 480,
 540                         .pixclock       = 30066,
 541                         .left_margin    = 88,
 542                         .right_margin   = 88,
 543                         .upper_margin   = 20,
 544                         .lower_margin   = 20,
 545                         .hsync_len      = 80,
 546                         .vsync_len      = 5,
 547                         .sync           = FB_SYNC_EXT,
 548                         .vmode          = FB_VMODE_NONINTERLACED
 549                 }
 550         }
 551 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
 552         (CONFIG_SYS_BOARD_VERSION == 3) || \
 553         (CONFIG_SYS_BOARD_VERSION == 4) || \
 554         (CONFIG_SYS_BOARD_VERSION == 5))
 555         , {
 556                 .bus    = -1,
 557                 .addr   = 0,
 558                 .pixfmt = IPU_PIX_FMT_RGB24,
 559                 .detect = NULL,
 560                 .enable = enable_spi_display,
 561                 .mode   = {
 562                         .name           = "lg4573",
 563                         .refresh        = 57,
 564                         .xres           = 480,
 565                         .yres           = 800,
 566                         .pixclock       = 37037,
 567                         .left_margin    = 59,
 568                         .right_margin   = 10,
 569                         .upper_margin   = 15,
 570                         .lower_margin   = 15,
 571                         .hsync_len      = 10,
 572                         .vsync_len      = 15,
 573                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 574                                           FB_SYNC_VERT_HIGH_ACT,
 575                         .vmode          = FB_VMODE_NONINTERLACED
 576                 }
 577         }
 578 #endif
 579 };
 580 size_t display_count = ARRAY_SIZE(displays);
 581
 582 #if defined(CONFIG_MTD_RAW_NAND)
 583 iomux_v3_cfg_t nfc_pads[] = {
 584         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 585         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 586         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 587         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 588         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 589         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 590         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 591         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 592         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 593         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 594         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 595         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 596         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 597         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 598         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 599         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 600 };
 601
 602 static void setup_gpmi_nand(void)
 603 {
 604         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 605
 606         /* config gpmi nand iomux */
 607         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 608                                          ARRAY_SIZE(nfc_pads));
 609
 610         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 611         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 612
 613         /* config gpmi and bch clock to 100 MHz */
 614         clrsetbits_le32(&mxc_ccm->cs2cdr,
 615                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 616                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 617                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 618                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 619                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 620                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 621
 622         /* enable ENFC_CLK_ROOT clock */
 623         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 624
 625         /* enable gpmi and bch clock gating */
 626         setbits_le32(&mxc_ccm->CCGR4,
 627                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 628                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 629                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 630                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 631                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 632
 633         /* enable apbh clock gating */
 634         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 635 }
 636 #else
 637 static void setup_gpmi_nand(void)
 638 {
 639 }
 640 #endif
 641
 642 int board_init(void)
 643 {
 644         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 645
 646         /* address of boot parameters */
 647         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 648
 649         setup_board_gpio();
 650         setup_gpmi_nand();
 651         setup_display();
 652
 653         /* GPIO_1 for USB_OTG_ID */
 654         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 655         return 0;
 656 }
 657
 658 int board_fit_config_name_match(const char *name)
 659 {
 660         if (gd->board_type == BOARD_TYPE_4 &&
 661             strchr(name, 0x34))
 662                 return 0;
 663
 664         if (gd->board_type == BOARD_TYPE_7 &&
 665             strchr(name, 0x37))
 666                 return 0;
 667
 668         return -1;
 669 }
 670
 671 static void do_board_detect(void)
 672 {
 673         int ret;
 674         char s[30];
 675
 676         /* default use board type 7 */
 677         gd->board_type = BOARD_TYPE_7;
 678         if (env_init())
 679                 return;
 680
 681         ret = env_get_f("panel", s, sizeof(s));
 682         if (ret < 0)
 683                 return;
 684
 685         if (!strncmp("lg4573", s, 6))
 686                 gd->board_type = BOARD_TYPE_4;
 687 }
 688
 689 #ifdef CONFIG_DTB_RESELECT
 690 int embedded_dtb_select(void)
 691 {
 692         int rescan;
 693
 694         do_board_detect();
 695         fdtdec_resetup(&rescan);
 696
 697         return 0;
 698 }
 699 #endif