1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
10 #include <fsl_esdhc.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sci/sci.h>
16 #include <asm/arch/imx8-pins.h>
17 #include <asm/arch/iomux.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
22 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
23 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
24 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
26 #define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
27 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
28 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
29 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
31 #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
32 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
33 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
34 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
36 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
37 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
38 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
39 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
41 #define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
42 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
43 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
44 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
46 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
47 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
48 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
49 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
51 #define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
52 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
53 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
54 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
56 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
57 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
58 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
59 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
60 #ifdef CONFIG_FSL_ESDHC
62 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
63 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
65 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
66 {USDHC1_BASE_ADDR, 0, 8},
67 {USDHC2_BASE_ADDR, 0, 4},
68 {USDHC3_BASE_ADDR, 0, 4},
71 static iomux_cfg_t emmc0[] = {
72 SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
73 SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
74 SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
75 SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
76 SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
77 SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
78 SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
79 SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
80 SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
81 SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
82 SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
83 SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
86 static iomux_cfg_t usdhc2_sd[] = {
87 SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
88 SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
89 SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
90 SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
91 SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
92 SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
93 SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
94 SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
95 SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
98 int board_mmc_init(bd_t *bis)
103 * According to the board_mmc_init() the following map is done:
104 * (U-Boot device node) (Physical Port)
109 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
112 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
113 if (ret != SC_ERR_NONE)
116 imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
118 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
121 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
122 if (ret != SC_ERR_NONE)
124 ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
125 if (ret != SC_ERR_NONE)
128 imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
130 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
131 gpio_request(USDHC2_CD_GPIO, "sd2_cd");
132 gpio_direction_input(USDHC2_CD_GPIO);
135 printf("Warning: you configured more USDHC controllers"
136 "(%d) than supported by the board\n", i + 1);
139 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
141 printf("Warning: failed to initialize mmc dev %d\n", i);
149 int board_mmc_getcd(struct mmc *mmc)
151 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
154 switch (cfg->esdhc_base) {
155 case USDHC1_BASE_ADDR:
158 case USDHC2_BASE_ADDR:
159 ret = !gpio_get_value(USDHC1_CD_GPIO);
161 case USDHC3_BASE_ADDR:
162 ret = !gpio_get_value(USDHC2_CD_GPIO);
169 #endif /* CONFIG_FSL_ESDHC */
171 void spl_board_init(void)
173 #if defined(CONFIG_SPL_SPI_SUPPORT)
174 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
175 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
176 puts("Warning: failed to initialize FSPI0\n");
181 puts("Normal Boot\n");
184 void spl_board_prepare_for_boot(void)
186 #if defined(CONFIG_SPL_SPI_SUPPORT)
187 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
188 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
189 puts("Warning: failed to turn off FSPI0\n");
195 #ifdef CONFIG_SPL_LOAD_FIT
196 int board_fit_config_name_match(const char *name)
198 /* Just empty function now - can't decide what to choose */
199 debug("%s: %s\n", __func__, name);
205 void board_init_f(ulong dummy)
207 /* Clear global data */
208 memset((void *)gd, 0, sizeof(gd_t));
212 board_early_init_f();
216 preloader_console_init();
219 memset(__bss_start, 0, __bss_end - __bss_start);
221 board_init_r(NULL, 0);