1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
16 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
17 #include <../serdes/a38x/high_speed_env_spec.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 * Those values and defines are taken from the Marvell U-Boot version
23 * "u-boot-2013.01-2014_T3.0"
25 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
26 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
27 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
28 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
29 #define DB_GP_88F68XX_GPP_OUT_ENA_MID \
30 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
31 BIT(16) | BIT(17) | BIT(18)))
33 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
34 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
35 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
36 #define DB_GP_88F68XX_GPP_POL_MID 0x0
38 /* IO expander on Marvell GP board includes e.g. fan enabling */
39 struct marvell_io_exp {
45 static struct marvell_io_exp io_exp[] = {
46 { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
47 { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
48 { 0x20, 2, 0x1D }, /* Output Data, register#0 */
49 { 0x20, 3, 0x18 }, /* Output Data, register#1 */
50 { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
51 { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
52 { 0x21, 2, 0x08 }, /* Output Data, register#0 */
53 { 0x21, 3, 0xC0 } /* Output Data, register#1 */
56 static struct serdes_map board_serdes_map[] = {
57 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
58 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
59 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
60 {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
61 {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
62 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
65 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
67 *serdes_map_array = board_serdes_map;
68 *count = ARRAY_SIZE(board_serdes_map);
73 * Define the DDR layout / topology here in the board file. This will
74 * be used by the DDR3 init code in the SPL U-Boot version to configure
75 * the DDR3 controller.
77 static struct mv_ddr_topology_map board_topology_map = {
79 0x1, /* active interfaces */
80 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
86 SPEED_BIN_DDR_1866L, /* speed_bin */
87 MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
88 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
89 MV_DDR_FREQ_800, /* frequency */
90 0, 0, /* cas_wl cas_l */
91 MV_DDR_TEMP_LOW, /* temperature */
92 MV_DDR_TIM_DEFAULT} }, /* timing */
93 BUS_MASK_32BIT, /* Busses mask */
94 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
95 { {0} }, /* raw spd data */
96 {0} /* timing parameters */
99 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
101 /* Return the board topology as defined in the board code */
102 return &board_topology_map;
105 int board_early_init_f(void)
108 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
109 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
110 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
111 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
112 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
113 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
114 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
115 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
117 /* Set GPP Out value */
118 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
119 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
121 /* Set GPP Polarity */
122 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
123 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
125 /* Set GPP Out Enable */
126 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
127 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
136 /* adress of boot parameters */
137 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
139 /* Init I2C IO expanders */
140 for (i = 0; i < ARRAY_SIZE(io_exp); i++)
141 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
148 puts("Board: Marvell DB-88F6820-GP\n");
153 int board_eth_init(bd_t *bis)
155 cpu_eth_init(bis); /* Built in controller(s) come first */
156 return pci_eth_init(bis);