1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 * Those values and defines are taken from the Marvell U-Boot version
19 * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
21 #define DB_88F6720_MPP0_7 0x00020020 /* SPI */
22 #define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
23 #define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
24 #define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
25 #define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
26 #define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
27 #define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
28 #define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
29 #define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
31 #define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
32 #define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
33 #define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
34 #define DB_88F6720_GPP_OUT_VAL_LOW 0x0
35 #define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
36 #define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
37 #define DB_88F6720_GPP_POL_LOW 0x0
38 #define DB_88F6720_GPP_POL_MID 0x0
39 #define DB_88F6720_GPP_POL_HIGH 0x0
41 int board_early_init_f(void)
44 writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
45 writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
46 writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
47 writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
48 writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
49 writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
50 writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
51 writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
52 writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
55 /* Set GPP Out value */
56 writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
57 writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
58 writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
60 /* Set GPP Polarity */
61 writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
62 writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
63 writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
65 /* Set GPP Out Enable */
66 writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
67 writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
68 writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
75 /* adress of boot parameters */
76 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
83 puts("Board: Marvell DB-88F6720\n");
88 int board_eth_init(bd_t *bis)
90 cpu_eth_init(bis); /* Built in controller(s) come first */
91 return pci_eth_init(bis);