1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
12 #include <environment.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <dm/uclass.h>
20 #include <fdt_support.h>
22 # include <atsha204a-i2c.h>
24 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
25 #include <../serdes/a38x/high_speed_env_spec.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
31 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
32 #define OMNIA_I2C_MCU_CHIP_LEN 1
34 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
35 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
36 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
39 CMD_GET_STATUS_WORD = 0x01,
41 CMD_WATCHDOG_STATE = 0x0b,
44 enum status_word_bits {
45 CARD_DET_STSBIT = 0x0010,
46 MSATA_IND_STSBIT = 0x0020,
49 #define OMNIA_ATSHA204_OTP_VERSION 0
50 #define OMNIA_ATSHA204_OTP_SERIAL 1
51 #define OMNIA_ATSHA204_OTP_MAC0 3
52 #define OMNIA_ATSHA204_OTP_MAC1 4
55 * Those values and defines are taken from the Marvell U-Boot version
56 * "u-boot-2013.01-2014_T3.0"
58 #define OMNIA_GPP_OUT_ENA_LOW \
59 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
60 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
61 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
62 #define OMNIA_GPP_OUT_ENA_MID \
63 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
64 BIT(16) | BIT(17) | BIT(18)))
66 #define OMNIA_GPP_OUT_VAL_LOW 0x0
67 #define OMNIA_GPP_OUT_VAL_MID 0x0
68 #define OMNIA_GPP_POL_LOW 0x0
69 #define OMNIA_GPP_POL_MID 0x0
71 static struct serdes_map board_serdes_map_pex[] = {
72 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
73 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
74 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
75 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
76 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
77 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
80 static struct serdes_map board_serdes_map_sata[] = {
81 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
82 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
83 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
84 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
85 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
86 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
89 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
92 struct udevice *bus, *dev;
95 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
97 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
98 OMNIA_I2C_BUS_NAME, ret);
102 ret = i2c_get_chip(bus, addr, offset_len, &dev);
104 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
112 static int omnia_mcu_read(u8 cmd, void *buf, int len)
114 struct udevice *chip;
116 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
117 OMNIA_I2C_MCU_CHIP_LEN);
121 return dm_i2c_read(chip, cmd, buf, len);
124 #ifndef CONFIG_SPL_BUILD
125 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
127 struct udevice *chip;
129 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
130 OMNIA_I2C_MCU_CHIP_LEN);
134 return dm_i2c_write(chip, cmd, buf, len);
137 static bool disable_mcu_watchdog(void)
141 puts("Disabling MCU watchdog... ");
143 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
145 printf("omnia_mcu_write failed: %i\n", ret);
155 static bool omnia_detect_sata(void)
160 puts("MiniPCIe/mSATA card detection... ");
162 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
164 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
169 if (!(stsword & CARD_DET_STSBIT)) {
174 if (stsword & MSATA_IND_STSBIT)
179 return stsword & MSATA_IND_STSBIT ? true : false;
182 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
184 if (omnia_detect_sata()) {
185 *serdes_map_array = board_serdes_map_sata;
186 *count = ARRAY_SIZE(board_serdes_map_sata);
188 *serdes_map_array = board_serdes_map_pex;
189 *count = ARRAY_SIZE(board_serdes_map_pex);
195 struct omnia_eeprom {
202 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
204 struct udevice *chip;
208 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
209 OMNIA_I2C_EEPROM_CHIP_LEN);
214 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
216 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
220 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
221 printf("bad EEPROM magic number (%08x, should be %08x)\n",
222 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
226 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
227 if (crc != oep->crc) {
228 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
236 static int omnia_get_ram_size_gb(void)
239 struct omnia_eeprom oep;
242 /* Get the board config from EEPROM */
243 if (omnia_read_eeprom(&oep)) {
244 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
246 if (oep.ramsize == 0x2)
251 /* Hardcoded fallback */
252 puts("Memory config from EEPROM read failed!\n");
253 puts("Falling back to default 1 GiB!\n");
262 * Define the DDR layout / topology here in the board file. This will
263 * be used by the DDR3 init code in the SPL U-Boot version to configure
264 * the DDR3 controller.
266 static struct mv_ddr_topology_map board_topology_map_1g = {
268 0x1, /* active interfaces */
269 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
270 { { { {0x1, 0, 0, 0},
275 SPEED_BIN_DDR_1600K, /* speed_bin */
276 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
277 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
278 MV_DDR_FREQ_800, /* frequency */
279 0, 0, /* cas_wl cas_l */
280 MV_DDR_TEMP_NORMAL, /* temperature */
281 MV_DDR_TIM_2T} }, /* timing */
282 BUS_MASK_32BIT, /* Busses mask */
283 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
284 { {0} }, /* raw spd data */
285 {0} /* timing parameters */
288 static struct mv_ddr_topology_map board_topology_map_2g = {
290 0x1, /* active interfaces */
291 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
292 { { { {0x1, 0, 0, 0},
297 SPEED_BIN_DDR_1600K, /* speed_bin */
298 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
299 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
300 MV_DDR_FREQ_800, /* frequency */
301 0, 0, /* cas_wl cas_l */
302 MV_DDR_TEMP_NORMAL, /* temperature */
303 MV_DDR_TIM_2T} }, /* timing */
304 BUS_MASK_32BIT, /* Busses mask */
305 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
306 { {0} }, /* raw spd data */
307 {0} /* timing parameters */
310 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
312 if (omnia_get_ram_size_gb() == 2)
313 return &board_topology_map_2g;
315 return &board_topology_map_1g;
318 #ifndef CONFIG_SPL_BUILD
319 static int set_regdomain(void)
321 struct omnia_eeprom oep;
322 char rd[3] = {' ', ' ', 0};
324 if (omnia_read_eeprom(&oep))
325 memcpy(rd, &oep.region, 2);
327 puts("EEPROM regdomain read failed.\n");
329 printf("Regdomain set to %s\n", rd);
330 return env_set("regdomain", rd);
334 * default factory reset bootcommand on Omnia first sets all the front LEDs
335 * to green and then tries to load the rescue image from SPI flash memory and
338 #define OMNIA_FACTORY_RESET_BOOTCMD \
340 "i2c mw 0x2a.1 0x3 0x1c 1; " \
341 "i2c mw 0x2a.1 0x4 0x1c 1; " \
342 "mw.l 0x01000000 0x00ff000c; " \
343 "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
344 "setenv bootargs \"earlyprintk console=ttyS0,115200" \
345 " omniarescue=$omnia_reset\"; " \
347 "sf read 0x1000000 0x100000 0x700000; " \
348 "bootm 0x1000000; " \
351 static void handle_reset_button(void)
356 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
358 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
363 env_set_ulong("omnia_reset", reset_status);
366 printf("RESET button was pressed, overwriting bootcmd!\n");
367 env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
372 int board_early_init_f(void)
375 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
376 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
377 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
378 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
379 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
380 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
381 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
382 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
384 /* Set GPP Out value */
385 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
386 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
388 /* Set GPP Polarity */
389 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
390 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
392 /* Set GPP Out Enable */
393 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
394 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
401 /* address of boot parameters */
402 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
404 #ifndef CONFIG_SPL_BUILD
405 disable_mcu_watchdog();
411 int board_late_init(void)
413 #ifndef CONFIG_SPL_BUILD
415 handle_reset_button();
422 static struct udevice *get_atsha204a_dev(void)
424 static struct udevice *dev;
429 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
430 puts("Cannot find ATSHA204A on I2C bus!\n");
439 u32 version_num, serial_num;
442 struct udevice *dev = get_atsha204a_dev();
445 err = atsha204a_wakeup(dev);
449 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
450 OMNIA_ATSHA204_OTP_VERSION,
455 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
456 OMNIA_ATSHA204_OTP_SERIAL,
461 atsha204a_sleep(dev);
465 printf("Turris Omnia:\n");
466 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
468 printf(" Serial Number: unknown\n");
470 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
471 be32_to_cpu(serial_num));
476 static void increment_mac(u8 *mac)
480 for (i = 5; i >= 3; i--) {
487 int misc_init_r(void)
490 struct udevice *dev = get_atsha204a_dev();
491 u8 mac0[4], mac1[4], mac[6];
496 err = atsha204a_wakeup(dev);
500 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
501 OMNIA_ATSHA204_OTP_MAC0, mac0);
505 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
506 OMNIA_ATSHA204_OTP_MAC1, mac1);
510 atsha204a_sleep(dev);
519 if (is_valid_ethaddr(mac))
520 eth_env_set_enetaddr("eth1addr", mac);
524 if (is_valid_ethaddr(mac))
525 eth_env_set_enetaddr("eth2addr", mac);
529 if (is_valid_ethaddr(mac))
530 eth_env_set_enetaddr("ethaddr", mac);