4 * Copyright (c) 2009 emlix GmbH
5 * Authors: Oskar Schirmer <os@emlix.com>
6 * Johannes Weiner <jw@emlix.com>
7 * Daniel Gloeckner <dg@emlix.com>
9 #include <linux/bitops.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/gpio.h>
17 #include <variant/hardware.h>
19 #define IRQ_BASE XTENSA_NR_IRQS
21 #define S6_GPIO_DATA 0x000
22 #define S6_GPIO_IS 0x404
23 #define S6_GPIO_IBE 0x408
24 #define S6_GPIO_IEV 0x40C
25 #define S6_GPIO_IE 0x410
26 #define S6_GPIO_RIS 0x414
27 #define S6_GPIO_MIS 0x418
28 #define S6_GPIO_IC 0x41C
29 #define S6_GPIO_AFSEL 0x420
30 #define S6_GPIO_DIR 0x800
31 #define S6_GPIO_BANK(nr) ((nr) * 0x1000)
32 #define S6_GPIO_MASK(nr) (4 << (nr))
33 #define S6_GPIO_OFFSET(nr) \
34 (S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
36 static int direction_input(struct gpio_chip *chip, unsigned int off)
38 writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
42 static int get(struct gpio_chip *chip, unsigned int off)
44 return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
47 static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
49 unsigned rel = S6_GPIO_OFFSET(off);
50 writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
51 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
55 static void set(struct gpio_chip *chip, unsigned int off, int val)
57 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
60 static int to_irq(struct gpio_chip *chip, unsigned offset)
63 return offset + IRQ_BASE;
67 static struct gpio_chip gpiochip = {
69 .direction_input = direction_input,
71 .direction_output = direction_output,
76 .can_sleep = 0, /* no blocking io needed */
77 .exported = 0, /* no exporting to userspace */
80 int s6_gpio_init(u32 afsel)
82 writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
83 writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
84 writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
85 return gpiochip_add(&gpiochip);
88 static void ack(struct irq_data *d)
90 writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
93 static void mask(struct irq_data *d)
95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
96 r &= ~(1 << (d->irq - IRQ_BASE));
97 writeb(r, S6_REG_GPIO + S6_GPIO_IE);
100 static void unmask(struct irq_data *d)
102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
103 m |= 1 << (d->irq - IRQ_BASE);
104 writeb(m, S6_REG_GPIO + S6_GPIO_IE);
107 static int set_type(struct irq_data *d, unsigned int type)
109 const u8 m = 1 << (d->irq - IRQ_BASE);
110 irq_flow_handler_t handler;
113 if (type == IRQ_TYPE_PROBE) {
114 if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
115 || (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
116 || readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
117 + S6_GPIO_MASK(irq - IRQ_BASE)))
119 type = IRQ_TYPE_EDGE_BOTH;
122 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
123 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
125 handler = handle_level_irq;
128 handler = handle_edge_irq;
130 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
131 __irq_set_handler_locked(irq, handler);
133 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
134 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
138 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
140 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
141 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
145 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
149 static struct irq_chip gpioirqs = {
153 .irq_unmask = unmask,
154 .irq_set_type = set_type,
157 static u8 demux_masks[4];
159 static void demux_irqs(unsigned int irq, struct irq_desc *desc)
161 struct irq_chip *chip = irq_desc_get_chip(desc);
162 u8 *mask = irq_desc_get_handler_data(desc);
166 chip->irq_mask(&desc->irq_data);
167 chip->irq_ack(&desc->irq_data));
168 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
171 int n = ffs(pending);
174 generic_handle_irq(cirq);
176 chip->irq_unmask(&desc->irq_data));
179 extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
181 void __init variant_init_irq(void)
184 writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
185 for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
186 const signed char *mapping = platform_irq_mappings[irq];
191 for(mask = 0; *mapping != -1; mapping++)
193 case S6_INTC_GPIO(0):
196 case S6_INTC_GPIO(1):
199 case S6_INTC_GPIO(2):
202 case S6_INTC_GPIO(3):
211 printk(KERN_ERR "chained irq chips can't share"
212 " parent irq %i\n", irq);
215 demux_masks[n] = mask;
221 irq_set_chip(cirq, &gpioirqs);
222 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
224 irq_set_handler_data(irq, demux_masks + n);
225 irq_set_chained_handler(irq, demux_irqs);
226 if (++n == ARRAY_SIZE(demux_masks))