arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/nmi.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cpumask.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 int unknown_nmi_panic;
  33 int nmi_watchdog_enabled;
  34 int panic_on_unrecovered_nmi;
  35
  36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  37  * evtsel_nmi_owner tracks the ownership of the event selection
  38  * - different performance counters/ event selection may be reserved for
  39  *   different subsystems this reservation system just tries to coordinate
  40  *   things a little
  41  */
  42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
  43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
  44
  45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  46
  47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  49  */
  50 #define NMI_MAX_COUNTER_BITS 66
  51
  52 /* nmi_active:
  53  * >0: the lapic NMI watchdog is active, but can be disabled
  54  * <0: the lapic NMI watchdog has not been set up, and cannot
  55  *     be enabled
  56  *  0: the lapic NMI watchdog is disabled, but can be enabled
  57  */
  58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  59 int panic_on_timeout;
  60
  61 unsigned int nmi_watchdog = NMI_DEFAULT;
  62 static unsigned int nmi_hz = HZ;
  63
  64 struct nmi_watchdog_ctlblk {
  65         int enabled;
  66         u64 check_bit;
  67         unsigned int cccr_msr;
  68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  70 };
  71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  72
  73 /* local prototypes */
  74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  75
  76 /* converts an msr to an appropriate reservation bit */
  77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  78 {
  79         /* returns the bit offset of the performance counter register */
  80         switch (boot_cpu_data.x86_vendor) {
  81         case X86_VENDOR_AMD:
  82                 return (msr - MSR_K7_PERFCTR0);
  83         case X86_VENDOR_INTEL:
  84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  86                 else
  87                         return (msr - MSR_P4_BPU_PERFCTR0);
  88         }
  89         return 0;
  90 }
  91
  92 /* converts an msr to an appropriate reservation bit */
  93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  94 {
  95         /* returns the bit offset of the event selection register */
  96         switch (boot_cpu_data.x86_vendor) {
  97         case X86_VENDOR_AMD:
  98                 return (msr - MSR_K7_EVNTSEL0);
  99         case X86_VENDOR_INTEL:
 100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 102                 else
 103                         return (msr - MSR_P4_BSU_ESCR0);
 104         }
 105         return 0;
 106 }
 107
 108 /* checks for a bit availability (hack for oprofile) */
 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 110 {
 111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 112
 113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 114 }
 115
 116 /* checks the an msr for availability */
 117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 118 {
 119         unsigned int counter;
 120
 121         counter = nmi_perfctr_msr_to_bit(msr);
 122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 123
 124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 125 }
 126
 127 int reserve_perfctr_nmi(unsigned int msr)
 128 {
 129         unsigned int counter;
 130
 131         counter = nmi_perfctr_msr_to_bit(msr);
 132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 133
 134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
 135                 return 1;
 136         return 0;
 137 }
 138
 139 void release_perfctr_nmi(unsigned int msr)
 140 {
 141         unsigned int counter;
 142
 143         counter = nmi_perfctr_msr_to_bit(msr);
 144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 145
 146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
 147 }
 148
 149 int reserve_evntsel_nmi(unsigned int msr)
 150 {
 151         unsigned int counter;
 152
 153         counter = nmi_evntsel_msr_to_bit(msr);
 154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 155
 156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
 157                 return 1;
 158         return 0;
 159 }
 160
 161 void release_evntsel_nmi(unsigned int msr)
 162 {
 163         unsigned int counter;
 164
 165         counter = nmi_evntsel_msr_to_bit(msr);
 166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 167
 168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
 169 }
 170
 171 static __cpuinit inline int nmi_known_cpu(void)
 172 {
 173         switch (boot_cpu_data.x86_vendor) {
 174         case X86_VENDOR_AMD:
 175                 return boot_cpu_data.x86 == 15 || boot_cpu_data.x86 == 16;
 176         case X86_VENDOR_INTEL:
 177                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 178                         return 1;
 179                 else
 180                         return (boot_cpu_data.x86 == 15);
 181         }
 182         return 0;
 183 }
 184
 185 /* Run after command line and cpu_init init, but before all other checks */
 186 void nmi_watchdog_default(void)
 187 {
 188         if (nmi_watchdog != NMI_DEFAULT)
 189                 return;
 190         nmi_watchdog = NMI_NONE;
 191 }
 192
 193 static int endflag __initdata = 0;
 194
 195 #ifdef CONFIG_SMP
 196 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 197  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 198  * CPUs during the test make them busy.
 199  */
 200 static __init void nmi_cpu_busy(void *data)
 201 {
 202         local_irq_enable_in_hardirq();
 203         /* Intentionally don't use cpu_relax here. This is
 204            to make sure that the performance counter really ticks,
 205            even if there is a simulator or similar that catches the
 206            pause instruction. On a real HT machine this is fine because
 207            all other CPUs are busy with "useless" delay loops and don't
 208            care if they get somewhat less cycles. */
 209         while (endflag == 0)
 210                 mb();
 211 }
 212 #endif
 213
 214 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 215 {
 216         unsigned int retval = hz;
 217
 218         /*
 219          * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
 220          * are writable, with higher bits sign extending from bit 31.
 221          * So, we can only program the counter with 31 bit values and
 222          * 32nd bit should be 1, for 33.. to be 1.
 223          * Find the appropriate nmi_hz
 224          */
 225         if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
 226                 retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
 227         }
 228         return retval;
 229 }
 230
 231 int __init check_nmi_watchdog (void)
 232 {
 233         int *counts;
 234         int cpu;
 235
 236         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 237                 return 0;
 238
 239         if (!atomic_read(&nmi_active))
 240                 return 0;
 241
 242         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 243         if (!counts)
 244                 return -1;
 245
 246         printk(KERN_INFO "testing NMI watchdog ... ");
 247
 248 #ifdef CONFIG_SMP
 249         if (nmi_watchdog == NMI_LOCAL_APIC)
 250                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 251 #endif
 252
 253         for (cpu = 0; cpu < NR_CPUS; cpu++)
 254                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 255         local_irq_enable();
 256         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 257
 258         for_each_online_cpu(cpu) {
 259                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 260                         continue;
 261                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 262                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 263                                cpu,
 264                                counts[cpu],
 265                                cpu_pda(cpu)->__nmi_count);
 266                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 267                         atomic_dec(&nmi_active);
 268                 }
 269         }
 270         if (!atomic_read(&nmi_active)) {
 271                 kfree(counts);
 272                 atomic_set(&nmi_active, -1);
 273                 endflag = 1;
 274                 return -1;
 275         }
 276         endflag = 1;
 277         printk("OK.\n");
 278
 279         /* now that we know it works we can reduce NMI frequency to
 280            something more reasonable; makes a difference in some configs */
 281         if (nmi_watchdog == NMI_LOCAL_APIC) {
 282                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 283
 284                 nmi_hz = 1;
 285                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
 286                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 287         }
 288
 289         kfree(counts);
 290         return 0;
 291 }
 292
 293 int __init setup_nmi_watchdog(char *str)
 294 {
 295         int nmi;
 296
 297         if (!strncmp(str,"panic",5)) {
 298                 panic_on_timeout = 1;
 299                 str = strchr(str, ',');
 300                 if (!str)
 301                         return 1;
 302                 ++str;
 303         }
 304
 305         get_option(&str, &nmi);
 306
 307         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 308                 return 0;
 309
 310         nmi_watchdog = nmi;
 311         return 1;
 312 }
 313
 314 __setup("nmi_watchdog=", setup_nmi_watchdog);
 315
 316 static void disable_lapic_nmi_watchdog(void)
 317 {
 318         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 319
 320         if (atomic_read(&nmi_active) <= 0)
 321                 return;
 322
 323         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 324
 325         BUG_ON(atomic_read(&nmi_active) != 0);
 326 }
 327
 328 static void enable_lapic_nmi_watchdog(void)
 329 {
 330         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 331
 332         /* are we already enabled */
 333         if (atomic_read(&nmi_active) != 0)
 334                 return;
 335
 336         /* are we lapic aware */
 337         if (nmi_known_cpu() <= 0)
 338                 return;
 339
 340         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 341         touch_nmi_watchdog();
 342 }
 343
 344 void disable_timer_nmi_watchdog(void)
 345 {
 346         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 347
 348         if (atomic_read(&nmi_active) <= 0)
 349                 return;
 350
 351         disable_irq(0);
 352         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 353
 354         BUG_ON(atomic_read(&nmi_active) != 0);
 355 }
 356
 357 void enable_timer_nmi_watchdog(void)
 358 {
 359         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 360
 361         if (atomic_read(&nmi_active) == 0) {
 362                 touch_nmi_watchdog();
 363                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 364                 enable_irq(0);
 365         }
 366 }
 367
 368 static void __acpi_nmi_disable(void *__unused)
 369 {
 370         apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 371 }
 372
 373 /*
 374  * Disable timer based NMIs on all CPUs:
 375  */
 376 void acpi_nmi_disable(void)
 377 {
 378         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 379                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 380 }
 381
 382 static void __acpi_nmi_enable(void *__unused)
 383 {
 384         apic_write(APIC_LVT0, APIC_DM_NMI);
 385 }
 386
 387 /*
 388  * Enable timer based NMIs on all CPUs:
 389  */
 390 void acpi_nmi_enable(void)
 391 {
 392         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 393                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 394 }
 395 #ifdef CONFIG_PM
 396
 397 static int nmi_pm_active; /* nmi_active before suspend */
 398
 399 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 400 {
 401         /* only CPU0 goes here, other CPUs should be offline */
 402         nmi_pm_active = atomic_read(&nmi_active);
 403         stop_apic_nmi_watchdog(NULL);
 404         BUG_ON(atomic_read(&nmi_active) != 0);
 405         return 0;
 406 }
 407
 408 static int lapic_nmi_resume(struct sys_device *dev)
 409 {
 410         /* only CPU0 goes here, other CPUs should be offline */
 411         if (nmi_pm_active > 0) {
 412                 setup_apic_nmi_watchdog(NULL);
 413                 touch_nmi_watchdog();
 414         }
 415         return 0;
 416 }
 417
 418 static struct sysdev_class nmi_sysclass = {
 419         set_kset_name("lapic_nmi"),
 420         .resume         = lapic_nmi_resume,
 421         .suspend        = lapic_nmi_suspend,
 422 };
 423
 424 static struct sys_device device_lapic_nmi = {
 425         .id             = 0,
 426         .cls    = &nmi_sysclass,
 427 };
 428
 429 static int __init init_lapic_nmi_sysfs(void)
 430 {
 431         int error;
 432
 433         /* should really be a BUG_ON but b/c this is an
 434          * init call, it just doesn't work.  -dcz
 435          */
 436         if (nmi_watchdog != NMI_LOCAL_APIC)
 437                 return 0;
 438
 439         if ( atomic_read(&nmi_active) < 0 )
 440                 return 0;
 441
 442         error = sysdev_class_register(&nmi_sysclass);
 443         if (!error)
 444                 error = sysdev_register(&device_lapic_nmi);
 445         return error;
 446 }
 447 /* must come after the local APIC's device_initcall() */
 448 late_initcall(init_lapic_nmi_sysfs);
 449
 450 #endif  /* CONFIG_PM */
 451
 452 /*
 453  * Activate the NMI watchdog via the local APIC.
 454  * Original code written by Keith Owens.
 455  */
 456
 457 /* Note that these events don't tick when the CPU idles. This means
 458    the frequency varies with CPU load. */
 459
 460 #define K7_EVNTSEL_ENABLE       (1 << 22)
 461 #define K7_EVNTSEL_INT          (1 << 20)
 462 #define K7_EVNTSEL_OS           (1 << 17)
 463 #define K7_EVNTSEL_USR          (1 << 16)
 464 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 465 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 466
 467 static int setup_k7_watchdog(void)
 468 {
 469         unsigned int perfctr_msr, evntsel_msr;
 470         unsigned int evntsel;
 471         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 472
 473         perfctr_msr = MSR_K7_PERFCTR0;
 474         evntsel_msr = MSR_K7_EVNTSEL0;
 475         if (!reserve_perfctr_nmi(perfctr_msr))
 476                 goto fail;
 477
 478         if (!reserve_evntsel_nmi(evntsel_msr))
 479                 goto fail1;
 480
 481         /* Simulator may not support it */
 482         if (checking_wrmsrl(evntsel_msr, 0UL))
 483                 goto fail2;
 484         wrmsrl(perfctr_msr, 0UL);
 485
 486         evntsel = K7_EVNTSEL_INT
 487                 | K7_EVNTSEL_OS
 488                 | K7_EVNTSEL_USR
 489                 | K7_NMI_EVENT;
 490
 491         /* setup the timer */
 492         wrmsr(evntsel_msr, evntsel, 0);
 493         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 494         apic_write(APIC_LVTPC, APIC_DM_NMI);
 495         evntsel |= K7_EVNTSEL_ENABLE;
 496         wrmsr(evntsel_msr, evntsel, 0);
 497
 498         wd->perfctr_msr = perfctr_msr;
 499         wd->evntsel_msr = evntsel_msr;
 500         wd->cccr_msr = 0;  //unused
 501         wd->check_bit = 1ULL<<63;
 502         return 1;
 503 fail2:
 504         release_evntsel_nmi(evntsel_msr);
 505 fail1:
 506         release_perfctr_nmi(perfctr_msr);
 507 fail:
 508         return 0;
 509 }
 510
 511 static void stop_k7_watchdog(void)
 512 {
 513         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 514
 515         wrmsr(wd->evntsel_msr, 0, 0);
 516
 517         release_evntsel_nmi(wd->evntsel_msr);
 518         release_perfctr_nmi(wd->perfctr_msr);
 519 }
 520
 521 /* Note that these events don't tick when the CPU idles. This means
 522    the frequency varies with CPU load. */
 523
 524 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 525 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 526 #define P4_ESCR_OS              (1<<3)
 527 #define P4_ESCR_USR             (1<<2)
 528 #define P4_CCCR_OVF_PMI0        (1<<26)
 529 #define P4_CCCR_OVF_PMI1        (1<<27)
 530 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 531 #define P4_CCCR_COMPLEMENT      (1<<19)
 532 #define P4_CCCR_COMPARE         (1<<18)
 533 #define P4_CCCR_REQUIRED        (3<<16)
 534 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 535 #define P4_CCCR_ENABLE          (1<<12)
 536 #define P4_CCCR_OVF             (1<<31)
 537 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 538    CRU_ESCR0 (with any non-null event selector) through a complemented
 539    max threshold. [IA32-Vol3, Section 14.9.9] */
 540
 541 static int setup_p4_watchdog(void)
 542 {
 543         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 544         unsigned int evntsel, cccr_val;
 545         unsigned int misc_enable, dummy;
 546         unsigned int ht_num;
 547         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 548
 549         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 550         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 551                 return 0;
 552
 553 #ifdef CONFIG_SMP
 554         /* detect which hyperthread we are on */
 555         if (smp_num_siblings == 2) {
 556                 unsigned int ebx, apicid;
 557
 558                 ebx = cpuid_ebx(1);
 559                 apicid = (ebx >> 24) & 0xff;
 560                 ht_num = apicid & 1;
 561         } else
 562 #endif
 563                 ht_num = 0;
 564
 565         /* performance counters are shared resources
 566          * assign each hyperthread its own set
 567          * (re-use the ESCR0 register, seems safe
 568          * and keeps the cccr_val the same)
 569          */
 570         if (!ht_num) {
 571                 /* logical cpu 0 */
 572                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 573                 evntsel_msr = MSR_P4_CRU_ESCR0;
 574                 cccr_msr = MSR_P4_IQ_CCCR0;
 575                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 576         } else {
 577                 /* logical cpu 1 */
 578                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 579                 evntsel_msr = MSR_P4_CRU_ESCR0;
 580                 cccr_msr = MSR_P4_IQ_CCCR1;
 581                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 582         }
 583
 584         if (!reserve_perfctr_nmi(perfctr_msr))
 585                 goto fail;
 586
 587         if (!reserve_evntsel_nmi(evntsel_msr))
 588                 goto fail1;
 589
 590         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 591                 | P4_ESCR_OS
 592                 | P4_ESCR_USR;
 593
 594         cccr_val |= P4_CCCR_THRESHOLD(15)
 595                  | P4_CCCR_COMPLEMENT
 596                  | P4_CCCR_COMPARE
 597                  | P4_CCCR_REQUIRED;
 598
 599         wrmsr(evntsel_msr, evntsel, 0);
 600         wrmsr(cccr_msr, cccr_val, 0);
 601         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 602         apic_write(APIC_LVTPC, APIC_DM_NMI);
 603         cccr_val |= P4_CCCR_ENABLE;
 604         wrmsr(cccr_msr, cccr_val, 0);
 605
 606         wd->perfctr_msr = perfctr_msr;
 607         wd->evntsel_msr = evntsel_msr;
 608         wd->cccr_msr = cccr_msr;
 609         wd->check_bit = 1ULL<<39;
 610         return 1;
 611 fail1:
 612         release_perfctr_nmi(perfctr_msr);
 613 fail:
 614         return 0;
 615 }
 616
 617 static void stop_p4_watchdog(void)
 618 {
 619         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 620
 621         wrmsr(wd->cccr_msr, 0, 0);
 622         wrmsr(wd->evntsel_msr, 0, 0);
 623
 624         release_evntsel_nmi(wd->evntsel_msr);
 625         release_perfctr_nmi(wd->perfctr_msr);
 626 }
 627
 628 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 629 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 630
 631 static int setup_intel_arch_watchdog(void)
 632 {
 633         unsigned int ebx;
 634         union cpuid10_eax eax;
 635         unsigned int unused;
 636         unsigned int perfctr_msr, evntsel_msr;
 637         unsigned int evntsel;
 638         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 639
 640         /*
 641          * Check whether the Architectural PerfMon supports
 642          * Unhalted Core Cycles Event or not.
 643          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 644          */
 645         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 646         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 647             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 648                 goto fail;
 649
 650         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 651         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 652
 653         if (!reserve_perfctr_nmi(perfctr_msr))
 654                 goto fail;
 655
 656         if (!reserve_evntsel_nmi(evntsel_msr))
 657                 goto fail1;
 658
 659         wrmsrl(perfctr_msr, 0UL);
 660
 661         evntsel = ARCH_PERFMON_EVENTSEL_INT
 662                 | ARCH_PERFMON_EVENTSEL_OS
 663                 | ARCH_PERFMON_EVENTSEL_USR
 664                 | ARCH_PERFMON_NMI_EVENT_SEL
 665                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 666
 667         /* setup the timer */
 668         wrmsr(evntsel_msr, evntsel, 0);
 669
 670         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 671         wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 672
 673         apic_write(APIC_LVTPC, APIC_DM_NMI);
 674         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 675         wrmsr(evntsel_msr, evntsel, 0);
 676
 677         wd->perfctr_msr = perfctr_msr;
 678         wd->evntsel_msr = evntsel_msr;
 679         wd->cccr_msr = 0;  //unused
 680         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 681         return 1;
 682 fail1:
 683         release_perfctr_nmi(perfctr_msr);
 684 fail:
 685         return 0;
 686 }
 687
 688 static void stop_intel_arch_watchdog(void)
 689 {
 690         unsigned int ebx;
 691         union cpuid10_eax eax;
 692         unsigned int unused;
 693         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 694
 695         /*
 696          * Check whether the Architectural PerfMon supports
 697          * Unhalted Core Cycles Event or not.
 698          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 699          */
 700         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 701         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 702             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 703                 return;
 704
 705         wrmsr(wd->evntsel_msr, 0, 0);
 706
 707         release_evntsel_nmi(wd->evntsel_msr);
 708         release_perfctr_nmi(wd->perfctr_msr);
 709 }
 710
 711 void setup_apic_nmi_watchdog(void *unused)
 712 {
 713         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 714
 715         /* only support LOCAL and IO APICs for now */
 716         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 717             (nmi_watchdog != NMI_IO_APIC))
 718                 return;
 719
 720         if (wd->enabled == 1)
 721                 return;
 722
 723         /* cheap hack to support suspend/resume */
 724         /* if cpu0 is not active neither should the other cpus */
 725         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 726                 return;
 727
 728         if (nmi_watchdog == NMI_LOCAL_APIC) {
 729                 switch (boot_cpu_data.x86_vendor) {
 730                 case X86_VENDOR_AMD:
 731                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 732                                 return;
 733                         if (!setup_k7_watchdog())
 734                                 return;
 735                         break;
 736                 case X86_VENDOR_INTEL:
 737                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 738                                 if (!setup_intel_arch_watchdog())
 739                                         return;
 740                                 break;
 741                         }
 742                         if (!setup_p4_watchdog())
 743                                 return;
 744                         break;
 745                 default:
 746                         return;
 747                 }
 748         }
 749         wd->enabled = 1;
 750         atomic_inc(&nmi_active);
 751 }
 752
 753 void stop_apic_nmi_watchdog(void *unused)
 754 {
 755         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 756
 757         /* only support LOCAL and IO APICs for now */
 758         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 759             (nmi_watchdog != NMI_IO_APIC))
 760                 return;
 761
 762         if (wd->enabled == 0)
 763                 return;
 764
 765         if (nmi_watchdog == NMI_LOCAL_APIC) {
 766                 switch (boot_cpu_data.x86_vendor) {
 767                 case X86_VENDOR_AMD:
 768                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 769                                 return;
 770                         stop_k7_watchdog();
 771                         break;
 772                 case X86_VENDOR_INTEL:
 773                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 774                                 stop_intel_arch_watchdog();
 775                                 break;
 776                         }
 777                         stop_p4_watchdog();
 778                         break;
 779                 default:
 780                         return;
 781                 }
 782         }
 783         wd->enabled = 0;
 784         atomic_dec(&nmi_active);
 785 }
 786
 787 /*
 788  * the best way to detect whether a CPU has a 'hard lockup' problem
 789  * is to check it's local APIC timer IRQ counts. If they are not
 790  * changing then that CPU has some problem.
 791  *
 792  * as these watchdog NMI IRQs are generated on every CPU, we only
 793  * have to check the current processor.
 794  */
 795
 796 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 797 static DEFINE_PER_CPU(local_t, alert_counter);
 798 static DEFINE_PER_CPU(int, nmi_touch);
 799
 800 void touch_nmi_watchdog (void)
 801 {
 802         if (nmi_watchdog > 0) {
 803                 unsigned cpu;
 804
 805                 /*
 806                  * Tell other CPUs to reset their alert counters. We cannot
 807                  * do it ourselves because the alert count increase is not
 808                  * atomic.
 809                  */
 810                 for_each_present_cpu (cpu)
 811                         per_cpu(nmi_touch, cpu) = 1;
 812         }
 813
 814         touch_softlockup_watchdog();
 815 }
 816
 817 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 818 {
 819         int sum;
 820         int touched = 0;
 821         int cpu = smp_processor_id();
 822         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 823         u64 dummy;
 824         int rc=0;
 825
 826         /* check for other users first */
 827         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 828                         == NOTIFY_STOP) {
 829                 rc = 1;
 830                 touched = 1;
 831         }
 832
 833         sum = read_pda(apic_timer_irqs);
 834         if (__get_cpu_var(nmi_touch)) {
 835                 __get_cpu_var(nmi_touch) = 0;
 836                 touched = 1;
 837         }
 838
 839         if (cpu_isset(cpu, backtrace_mask)) {
 840                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 841
 842                 spin_lock(&lock);
 843                 printk("NMI backtrace for cpu %d\n", cpu);
 844                 dump_stack();
 845                 spin_unlock(&lock);
 846                 cpu_clear(cpu, backtrace_mask);
 847         }
 848
 849 #ifdef CONFIG_X86_MCE
 850         /* Could check oops_in_progress here too, but it's safer
 851            not too */
 852         if (atomic_read(&mce_entry) > 0)
 853                 touched = 1;
 854 #endif
 855         /* if the apic timer isn't firing, this cpu isn't doing much */
 856         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 857                 /*
 858                  * Ayiee, looks like this CPU is stuck ...
 859                  * wait a few IRQs (5 seconds) before doing the oops ...
 860                  */
 861                 local_inc(&__get_cpu_var(alert_counter));
 862                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
 863                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
 864                                 panic_on_timeout);
 865         } else {
 866                 __get_cpu_var(last_irq_sum) = sum;
 867                 local_set(&__get_cpu_var(alert_counter), 0);
 868         }
 869
 870         /* see if the nmi watchdog went off */
 871         if (wd->enabled) {
 872                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 873                         rdmsrl(wd->perfctr_msr, dummy);
 874                         if (dummy & wd->check_bit){
 875                                 /* this wasn't a watchdog timer interrupt */
 876                                 goto done;
 877                         }
 878
 879                         /* only Intel uses the cccr msr */
 880                         if (wd->cccr_msr != 0) {
 881                                 /*
 882                                  * P4 quirks:
 883                                  * - An overflown perfctr will assert its interrupt
 884                                  *   until the OVF flag in its CCCR is cleared.
 885                                  * - LVTPC is masked on interrupt and must be
 886                                  *   unmasked by the LVTPC handler.
 887                                  */
 888                                 rdmsrl(wd->cccr_msr, dummy);
 889                                 dummy &= ~P4_CCCR_OVF;
 890                                 wrmsrl(wd->cccr_msr, dummy);
 891                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 892                                 /* start the cycle over again */
 893                                 wrmsrl(wd->perfctr_msr,
 894                                        -((u64)cpu_khz * 1000 / nmi_hz));
 895                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 896                                 /*
 897                                  * ArchPerfom/Core Duo needs to re-unmask
 898                                  * the apic vector
 899                                  */
 900                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 901                                 /* ARCH_PERFMON has 32 bit counter writes */
 902                                 wrmsr(wd->perfctr_msr,
 903                                      (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 904                         } else {
 905                                 /* start the cycle over again */
 906                                 wrmsrl(wd->perfctr_msr,
 907                                        -((u64)cpu_khz * 1000 / nmi_hz));
 908                         }
 909                         rc = 1;
 910                 } else  if (nmi_watchdog == NMI_IO_APIC) {
 911                         /* don't know how to accurately check for this.
 912                          * just assume it was a watchdog timer interrupt
 913                          * This matches the old behaviour.
 914                          */
 915                         rc = 1;
 916                 } else
 917                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 918         }
 919 done:
 920         return rc;
 921 }
 922
 923 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 924 {
 925         nmi_enter();
 926         add_pda(__nmi_count,1);
 927         default_do_nmi(regs);
 928         nmi_exit();
 929 }
 930
 931 int do_nmi_callback(struct pt_regs * regs, int cpu)
 932 {
 933 #ifdef CONFIG_SYSCTL
 934         if (unknown_nmi_panic)
 935                 return unknown_nmi_panic_callback(regs, cpu);
 936 #endif
 937         return 0;
 938 }
 939
 940 #ifdef CONFIG_SYSCTL
 941
 942 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 943 {
 944         unsigned char reason = get_nmi_reason();
 945         char buf[64];
 946
 947         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 948         die_nmi(buf, regs, 1);  /* Always panic here */
 949         return 0;
 950 }
 951
 952 /*
 953  * proc handler for /proc/sys/kernel/nmi
 954  */
 955 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
 956                         void __user *buffer, size_t *length, loff_t *ppos)
 957 {
 958         int old_state;
 959
 960         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
 961         old_state = nmi_watchdog_enabled;
 962         proc_dointvec(table, write, file, buffer, length, ppos);
 963         if (!!old_state == !!nmi_watchdog_enabled)
 964                 return 0;
 965
 966         if (atomic_read(&nmi_active) < 0) {
 967                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
 968                 return -EIO;
 969         }
 970
 971         /* if nmi_watchdog is not set yet, then set it */
 972         nmi_watchdog_default();
 973
 974         if (nmi_watchdog == NMI_LOCAL_APIC) {
 975                 if (nmi_watchdog_enabled)
 976                         enable_lapic_nmi_watchdog();
 977                 else
 978                         disable_lapic_nmi_watchdog();
 979         } else {
 980                 printk( KERN_WARNING
 981                         "NMI watchdog doesn't know what hardware to touch\n");
 982                 return -EIO;
 983         }
 984         return 0;
 985 }
 986
 987 #endif
 988
 989 void __trigger_all_cpu_backtrace(void)
 990 {
 991         int i;
 992
 993         backtrace_mask = cpu_online_map;
 994         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
 995         for (i = 0; i < 10 * 1000; i++) {
 996                 if (cpus_empty(backtrace_mask))
 997                         break;
 998                 mdelay(1);
 999         }
1000 }
1001
1002 EXPORT_SYMBOL(nmi_active);
1003 EXPORT_SYMBOL(nmi_watchdog);
1004 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1005 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1006 EXPORT_SYMBOL(reserve_perfctr_nmi);
1007 EXPORT_SYMBOL(release_perfctr_nmi);
1008 EXPORT_SYMBOL(reserve_evntsel_nmi);
1009 EXPORT_SYMBOL(release_evntsel_nmi);
1010 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1011 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
1012 EXPORT_SYMBOL(touch_nmi_watchdog);