2 * linux/arch/x86_64/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
12 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
15 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/bootmem.h>
19 #include <linux/smp_lock.h>
20 #include <linux/interrupt.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/module.h>
24 #include <linux/sysdev.h>
25 #include <linux/nmi.h>
26 #include <linux/sysctl.h>
27 #include <linux/kprobes.h>
31 #include <asm/mpspec.h>
34 #include <asm/proto.h>
35 #include <asm/kdebug.h>
36 #include <asm/local.h>
40 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
41 * - it may be reserved by some other driver, or not
42 * - when not reserved by some other driver, it may be used for
43 * the NMI watchdog, or not
45 * This is maintained separately from nmi_active because the NMI
46 * watchdog may also be driven from the I/O APIC timer.
48 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
49 static unsigned int lapic_nmi_owner;
50 #define LAPIC_NMI_WATCHDOG (1<<0)
51 #define LAPIC_NMI_RESERVED (1<<1)
54 * +1: the lapic NMI watchdog is active, but can be disabled
55 * 0: the lapic NMI watchdog has not been set up, and cannot
57 * -1: the lapic NMI watchdog is disabled, but can be enabled
59 int nmi_active; /* oprofile uses this */
62 unsigned int nmi_watchdog = NMI_DEFAULT;
63 static unsigned int nmi_hz = HZ;
64 static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
65 static unsigned int nmi_p4_cccr_val;
67 /* Note that these events don't tick when the CPU idles. This means
68 the frequency varies with CPU load. */
70 #define K7_EVNTSEL_ENABLE (1 << 22)
71 #define K7_EVNTSEL_INT (1 << 20)
72 #define K7_EVNTSEL_OS (1 << 17)
73 #define K7_EVNTSEL_USR (1 << 16)
74 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
75 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
77 #define MSR_P4_MISC_ENABLE 0x1A0
78 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
79 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
80 #define MSR_P4_PERFCTR0 0x300
81 #define MSR_P4_CCCR0 0x360
82 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
83 #define P4_ESCR_OS (1<<3)
84 #define P4_ESCR_USR (1<<2)
85 #define P4_CCCR_OVF_PMI0 (1<<26)
86 #define P4_CCCR_OVF_PMI1 (1<<27)
87 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
88 #define P4_CCCR_COMPLEMENT (1<<19)
89 #define P4_CCCR_COMPARE (1<<18)
90 #define P4_CCCR_REQUIRED (3<<16)
91 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
92 #define P4_CCCR_ENABLE (1<<12)
93 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
94 CRU_ESCR0 (with any non-null event selector) through a complemented
95 max threshold. [IA32-Vol3, Section 14.9.9] */
96 #define MSR_P4_IQ_COUNTER0 0x30C
97 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
98 #define P4_NMI_IQ_CCCR0 \
99 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
100 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
102 static __cpuinit inline int nmi_known_cpu(void)
104 switch (boot_cpu_data.x86_vendor) {
106 return boot_cpu_data.x86 == 15;
107 case X86_VENDOR_INTEL:
108 return boot_cpu_data.x86 == 15;
113 /* Run after command line and cpu_init init, but before all other checks */
114 void __cpuinit nmi_watchdog_default(void)
116 if (nmi_watchdog != NMI_DEFAULT)
119 nmi_watchdog = NMI_LOCAL_APIC;
121 nmi_watchdog = NMI_IO_APIC;
125 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
126 * the CPU is idle. To make sure the NMI watchdog really ticks on all
127 * CPUs during the test make them busy.
129 static __init void nmi_cpu_busy(void *data)
131 volatile int *endflag = data;
133 /* Intentionally don't use cpu_relax here. This is
134 to make sure that the performance counter really ticks,
135 even if there is a simulator or similar that catches the
136 pause instruction. On a real HT machine this is fine because
137 all other CPUs are busy with "useless" delay loops and don't
138 care if they get somewhat less cycles. */
139 while (*endflag == 0)
144 int __init check_nmi_watchdog (void)
146 volatile int endflag = 0;
150 counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
154 printk(KERN_INFO "testing NMI watchdog ... ");
157 if (nmi_watchdog == NMI_LOCAL_APIC)
158 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
161 for (cpu = 0; cpu < NR_CPUS; cpu++)
162 counts[cpu] = cpu_pda(cpu)->__nmi_count;
164 mdelay((10*1000)/nmi_hz); // wait 10 ticks
166 for_each_online_cpu(cpu) {
167 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
169 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
172 cpu_pda(cpu)->__nmi_count);
174 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
183 /* now that we know it works we can reduce NMI frequency to
184 something more reasonable; makes a difference in some configs */
185 if (nmi_watchdog == NMI_LOCAL_APIC)
192 int __init setup_nmi_watchdog(char *str)
196 if (!strncmp(str,"panic",5)) {
197 panic_on_timeout = 1;
198 str = strchr(str, ',');
204 get_option(&str, &nmi);
206 if (nmi >= NMI_INVALID)
212 __setup("nmi_watchdog=", setup_nmi_watchdog);
214 static void disable_lapic_nmi_watchdog(void)
218 switch (boot_cpu_data.x86_vendor) {
220 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
222 case X86_VENDOR_INTEL:
223 if (boot_cpu_data.x86 == 15) {
224 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
225 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
230 /* tell do_nmi() and others that we're not active any more */
234 static void enable_lapic_nmi_watchdog(void)
236 if (nmi_active < 0) {
237 nmi_watchdog = NMI_LOCAL_APIC;
238 touch_nmi_watchdog();
239 setup_apic_nmi_watchdog();
243 int reserve_lapic_nmi(void)
245 unsigned int old_owner;
247 spin_lock(&lapic_nmi_owner_lock);
248 old_owner = lapic_nmi_owner;
249 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
250 spin_unlock(&lapic_nmi_owner_lock);
251 if (old_owner & LAPIC_NMI_RESERVED)
253 if (old_owner & LAPIC_NMI_WATCHDOG)
254 disable_lapic_nmi_watchdog();
258 void release_lapic_nmi(void)
260 unsigned int new_owner;
262 spin_lock(&lapic_nmi_owner_lock);
263 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
264 lapic_nmi_owner = new_owner;
265 spin_unlock(&lapic_nmi_owner_lock);
266 if (new_owner & LAPIC_NMI_WATCHDOG)
267 enable_lapic_nmi_watchdog();
270 void disable_timer_nmi_watchdog(void)
272 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
276 unset_nmi_callback();
278 nmi_watchdog = NMI_NONE;
281 void enable_timer_nmi_watchdog(void)
283 if (nmi_active < 0) {
284 nmi_watchdog = NMI_IO_APIC;
285 touch_nmi_watchdog();
293 static int nmi_pm_active; /* nmi_active before suspend */
295 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
297 nmi_pm_active = nmi_active;
298 disable_lapic_nmi_watchdog();
302 static int lapic_nmi_resume(struct sys_device *dev)
304 if (nmi_pm_active > 0)
305 enable_lapic_nmi_watchdog();
309 static struct sysdev_class nmi_sysclass = {
310 set_kset_name("lapic_nmi"),
311 .resume = lapic_nmi_resume,
312 .suspend = lapic_nmi_suspend,
315 static struct sys_device device_lapic_nmi = {
317 .cls = &nmi_sysclass,
320 static int __init init_lapic_nmi_sysfs(void)
324 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
327 error = sysdev_class_register(&nmi_sysclass);
329 error = sysdev_register(&device_lapic_nmi);
332 /* must come after the local APIC's device_initcall() */
333 late_initcall(init_lapic_nmi_sysfs);
335 #endif /* CONFIG_PM */
338 * Activate the NMI watchdog via the local APIC.
339 * Original code written by Keith Owens.
342 static void clear_msr_range(unsigned int base, unsigned int n)
346 for(i = 0; i < n; ++i)
350 static void setup_k7_watchdog(void)
353 unsigned int evntsel;
355 nmi_perfctr_msr = MSR_K7_PERFCTR0;
357 for(i = 0; i < 4; ++i) {
358 /* Simulator may not support it */
359 if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
363 wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
366 evntsel = K7_EVNTSEL_INT
371 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
372 wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
373 apic_write(APIC_LVTPC, APIC_DM_NMI);
374 evntsel |= K7_EVNTSEL_ENABLE;
375 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
379 static int setup_p4_watchdog(void)
381 unsigned int misc_enable, dummy;
383 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
384 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
387 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
388 nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
390 if (smp_num_siblings == 2)
391 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
394 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
395 clear_msr_range(0x3F1, 2);
396 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
397 docs doesn't fully define it, so leave it alone for now. */
398 if (boot_cpu_data.x86_model >= 0x3) {
399 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
400 clear_msr_range(0x3A0, 26);
401 clear_msr_range(0x3BC, 3);
403 clear_msr_range(0x3A0, 31);
405 clear_msr_range(0x3C0, 6);
406 clear_msr_range(0x3C8, 6);
407 clear_msr_range(0x3E0, 2);
408 clear_msr_range(MSR_P4_CCCR0, 18);
409 clear_msr_range(MSR_P4_PERFCTR0, 18);
411 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
412 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
413 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
414 wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
415 apic_write(APIC_LVTPC, APIC_DM_NMI);
416 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
420 void setup_apic_nmi_watchdog(void)
422 switch (boot_cpu_data.x86_vendor) {
424 if (boot_cpu_data.x86 != 15)
426 if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
430 case X86_VENDOR_INTEL:
431 if (boot_cpu_data.x86 != 15)
433 if (!setup_p4_watchdog())
440 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
445 * the best way to detect whether a CPU has a 'hard lockup' problem
446 * is to check it's local APIC timer IRQ counts. If they are not
447 * changing then that CPU has some problem.
449 * as these watchdog NMI IRQs are generated on every CPU, we only
450 * have to check the current processor.
453 static DEFINE_PER_CPU(unsigned, last_irq_sum);
454 static DEFINE_PER_CPU(local_t, alert_counter);
455 static DEFINE_PER_CPU(int, nmi_touch);
457 void touch_nmi_watchdog (void)
459 if (nmi_watchdog > 0) {
463 * Tell other CPUs to reset their alert counters. We cannot
464 * do it ourselves because the alert count increase is not
467 for_each_present_cpu (cpu)
468 per_cpu(nmi_touch, cpu) = 1;
471 touch_softlockup_watchdog();
474 void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
479 sum = read_pda(apic_timer_irqs);
480 if (__get_cpu_var(nmi_touch)) {
481 __get_cpu_var(nmi_touch) = 0;
484 #ifdef CONFIG_X86_MCE
485 /* Could check oops_in_progress here too, but it's safer
487 if (atomic_read(&mce_entry) > 0)
490 if (!touched && __get_cpu_var(last_irq_sum) == sum) {
492 * Ayiee, looks like this CPU is stuck ...
493 * wait a few IRQs (5 seconds) before doing the oops ...
495 local_inc(&__get_cpu_var(alert_counter));
496 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
497 if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
499 local_set(&__get_cpu_var(alert_counter), 0);
502 die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
505 __get_cpu_var(last_irq_sum) = sum;
506 local_set(&__get_cpu_var(alert_counter), 0);
508 if (nmi_perfctr_msr) {
509 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
512 * - An overflown perfctr will assert its interrupt
513 * until the OVF flag in its CCCR is cleared.
514 * - LVTPC is masked on interrupt and must be
515 * unmasked by the LVTPC handler.
517 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
518 apic_write(APIC_LVTPC, APIC_DM_NMI);
520 wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
524 static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
529 static nmi_callback_t nmi_callback = dummy_nmi_callback;
531 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
533 int cpu = safe_smp_processor_id();
536 add_pda(__nmi_count,1);
537 if (!rcu_dereference(nmi_callback)(regs, cpu))
538 default_do_nmi(regs);
542 void set_nmi_callback(nmi_callback_t callback)
545 rcu_assign_pointer(nmi_callback, callback);
548 void unset_nmi_callback(void)
550 nmi_callback = dummy_nmi_callback;
555 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
557 unsigned char reason = get_nmi_reason();
560 if (!(reason & 0xc0)) {
561 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
568 * proc handler for /proc/sys/kernel/unknown_nmi_panic
570 int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
571 void __user *buffer, size_t *length, loff_t *ppos)
575 old_state = unknown_nmi_panic;
576 proc_dointvec(table, write, file, buffer, length, ppos);
577 if (!!old_state == !!unknown_nmi_panic)
580 if (unknown_nmi_panic) {
581 if (reserve_lapic_nmi() < 0) {
582 unknown_nmi_panic = 0;
585 set_nmi_callback(unknown_nmi_panic_callback);
589 unset_nmi_callback();
596 EXPORT_SYMBOL(nmi_active);
597 EXPORT_SYMBOL(nmi_watchdog);
598 EXPORT_SYMBOL(reserve_lapic_nmi);
599 EXPORT_SYMBOL(release_lapic_nmi);
600 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
601 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
602 EXPORT_SYMBOL(touch_nmi_watchdog);