2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
52 #define __apicdebuginit __init
54 int sis_apic_bug; /* not actually supported, dummy for compile */
56 static int no_timer_check;
58 /* Where if anywhere is the i8259 connect in external int mode */
59 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61 static DEFINE_SPINLOCK(ioapic_lock);
62 DEFINE_SPINLOCK(vector_lock);
65 * # of IRQ routing registers
67 int nr_ioapic_registers[MAX_IO_APICS];
70 * Rough estimation of how many shared IRQs there are, can
73 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
77 * This is performance-critical, we want to do it O(1)
79 * the indexing order of this array favors 1:1 mappings
80 * between pins and IRQs.
83 static struct irq_pin_list {
84 short apic, pin, next;
85 } irq_2_pin[PIN_MAP_SIZE];
89 unsigned int unused[3];
93 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
95 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
96 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
99 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
101 struct io_apic __iomem *io_apic = io_apic_base(apic);
102 writel(reg, &io_apic->index);
103 return readl(&io_apic->data);
106 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 writel(value, &io_apic->data);
114 * Re-write a value: to be used for read-modify-write
115 * cycles where the read already set up the index register.
117 static inline void io_apic_modify(unsigned int apic, unsigned int value)
119 struct io_apic __iomem *io_apic = io_apic_base(apic);
120 writel(value, &io_apic->data);
124 * Synchronize the IO-APIC and the CPU by doing
125 * a dummy read from the IO-APIC
127 static inline void io_apic_sync(unsigned int apic)
129 struct io_apic __iomem *io_apic = io_apic_base(apic);
130 readl(&io_apic->data);
133 #define __DO_ACTION(R, ACTION, FINAL) \
137 struct irq_pin_list *entry = irq_2_pin + irq; \
139 BUG_ON(irq >= NR_IRQS); \
145 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
147 io_apic_modify(entry->apic, reg); \
150 entry = irq_2_pin + entry->next; \
156 struct { u32 w1, w2; };
157 struct IO_APIC_route_entry entry;
160 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
162 union entry_union eu;
164 spin_lock_irqsave(&ioapic_lock, flags);
165 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
166 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
167 spin_unlock_irqrestore(&ioapic_lock, flags);
172 * When we write a new IO APIC routing entry, we need to write the high
173 * word first! If the mask bit in the low word is clear, we will enable
174 * the interrupt, and we need to make sure the entry is fully populated
175 * before that happens.
178 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
180 union entry_union eu;
182 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
183 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
186 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
189 spin_lock_irqsave(&ioapic_lock, flags);
190 __ioapic_write_entry(apic, pin, e);
191 spin_unlock_irqrestore(&ioapic_lock, flags);
195 * When we mask an IO APIC routing entry, we need to write the low
196 * word first, in order to set the mask bit before we change the
199 static void ioapic_mask_entry(int apic, int pin)
202 union entry_union eu = { .entry.mask = 1 };
204 spin_lock_irqsave(&ioapic_lock, flags);
205 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
206 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
207 spin_unlock_irqrestore(&ioapic_lock, flags);
211 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
214 struct irq_pin_list *entry = irq_2_pin + irq;
216 BUG_ON(irq >= NR_IRQS);
223 io_apic_write(apic, 0x11 + pin*2, dest);
224 reg = io_apic_read(apic, 0x10 + pin*2);
227 io_apic_modify(apic, reg);
230 entry = irq_2_pin + entry->next;
234 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
241 cpus_and(tmp, mask, cpu_online_map);
245 cpus_and(mask, tmp, CPU_MASK_ALL);
247 vector = assign_irq_vector(irq, mask, &tmp);
251 dest = cpu_mask_to_apicid(tmp);
254 * Only the high 8 bits are valid.
256 dest = SET_APIC_LOGICAL_ID(dest);
258 spin_lock_irqsave(&ioapic_lock, flags);
259 __target_IO_APIC_irq(irq, dest, vector);
260 set_native_irq_info(irq, mask);
261 spin_unlock_irqrestore(&ioapic_lock, flags);
266 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
267 * shared ISA-space IRQs, so we have to support them. We are super
268 * fast in the common case, and fast for shared ISA-space IRQs.
270 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
272 static int first_free_entry = NR_IRQS;
273 struct irq_pin_list *entry = irq_2_pin + irq;
275 BUG_ON(irq >= NR_IRQS);
277 entry = irq_2_pin + entry->next;
279 if (entry->pin != -1) {
280 entry->next = first_free_entry;
281 entry = irq_2_pin + entry->next;
282 if (++first_free_entry >= PIN_MAP_SIZE)
283 panic("io_apic.c: ran out of irq_2_pin entries!");
290 #define DO_ACTION(name,R,ACTION, FINAL) \
292 static void name##_IO_APIC_irq (unsigned int irq) \
293 __DO_ACTION(R, ACTION, FINAL)
295 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
297 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
300 static void mask_IO_APIC_irq (unsigned int irq)
304 spin_lock_irqsave(&ioapic_lock, flags);
305 __mask_IO_APIC_irq(irq);
306 spin_unlock_irqrestore(&ioapic_lock, flags);
309 static void unmask_IO_APIC_irq (unsigned int irq)
313 spin_lock_irqsave(&ioapic_lock, flags);
314 __unmask_IO_APIC_irq(irq);
315 spin_unlock_irqrestore(&ioapic_lock, flags);
318 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
320 struct IO_APIC_route_entry entry;
322 /* Check delivery_mode to be sure we're not clearing an SMI pin */
323 entry = ioapic_read_entry(apic, pin);
324 if (entry.delivery_mode == dest_SMI)
327 * Disable it in the IO-APIC irq-routing table:
329 ioapic_mask_entry(apic, pin);
332 static void clear_IO_APIC (void)
336 for (apic = 0; apic < nr_ioapics; apic++)
337 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
338 clear_IO_APIC_pin(apic, pin);
341 int skip_ioapic_setup;
344 /* dummy parsing: see setup.c */
346 static int __init disable_ioapic_setup(char *str)
348 skip_ioapic_setup = 1;
351 early_param("noapic", disable_ioapic_setup);
354 * Find the IRQ entry number of a certain pin.
356 static int find_irq_entry(int apic, int pin, int type)
360 for (i = 0; i < mp_irq_entries; i++)
361 if (mp_irqs[i].mpc_irqtype == type &&
362 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
363 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
364 mp_irqs[i].mpc_dstirq == pin)
371 * Find the pin to which IRQ[irq] (ISA) is connected
373 static int __init find_isa_irq_pin(int irq, int type)
377 for (i = 0; i < mp_irq_entries; i++) {
378 int lbus = mp_irqs[i].mpc_srcbus;
380 if (test_bit(lbus, mp_bus_not_pci) &&
381 (mp_irqs[i].mpc_irqtype == type) &&
382 (mp_irqs[i].mpc_srcbusirq == irq))
384 return mp_irqs[i].mpc_dstirq;
389 static int __init find_isa_irq_apic(int irq, int type)
393 for (i = 0; i < mp_irq_entries; i++) {
394 int lbus = mp_irqs[i].mpc_srcbus;
396 if (test_bit(lbus, mp_bus_not_pci) &&
397 (mp_irqs[i].mpc_irqtype == type) &&
398 (mp_irqs[i].mpc_srcbusirq == irq))
401 if (i < mp_irq_entries) {
403 for(apic = 0; apic < nr_ioapics; apic++) {
404 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
413 * Find a specific PCI IRQ entry.
414 * Not an __init, possibly needed by modules
416 static int pin_2_irq(int idx, int apic, int pin);
418 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
420 int apic, i, best_guess = -1;
422 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
424 if (mp_bus_id_to_pci_bus[bus] == -1) {
425 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
428 for (i = 0; i < mp_irq_entries; i++) {
429 int lbus = mp_irqs[i].mpc_srcbus;
431 for (apic = 0; apic < nr_ioapics; apic++)
432 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
433 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
436 if (!test_bit(lbus, mp_bus_not_pci) &&
437 !mp_irqs[i].mpc_irqtype &&
439 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
440 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
442 if (!(apic || IO_APIC_IRQ(irq)))
445 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
448 * Use the first all-but-pin matching entry as a
449 * best-guess fuzzy result for broken mptables.
455 BUG_ON(best_guess >= NR_IRQS);
459 /* ISA interrupts are always polarity zero edge triggered,
460 * when listed as conforming in the MP table. */
462 #define default_ISA_trigger(idx) (0)
463 #define default_ISA_polarity(idx) (0)
465 /* PCI interrupts are always polarity one level triggered,
466 * when listed as conforming in the MP table. */
468 #define default_PCI_trigger(idx) (1)
469 #define default_PCI_polarity(idx) (1)
471 static int __init MPBIOS_polarity(int idx)
473 int bus = mp_irqs[idx].mpc_srcbus;
477 * Determine IRQ line polarity (high active or low active):
479 switch (mp_irqs[idx].mpc_irqflag & 3)
481 case 0: /* conforms, ie. bus-type dependent polarity */
482 if (test_bit(bus, mp_bus_not_pci))
483 polarity = default_ISA_polarity(idx);
485 polarity = default_PCI_polarity(idx);
487 case 1: /* high active */
492 case 2: /* reserved */
494 printk(KERN_WARNING "broken BIOS!!\n");
498 case 3: /* low active */
503 default: /* invalid */
505 printk(KERN_WARNING "broken BIOS!!\n");
513 static int MPBIOS_trigger(int idx)
515 int bus = mp_irqs[idx].mpc_srcbus;
519 * Determine IRQ trigger mode (edge or level sensitive):
521 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
523 case 0: /* conforms, ie. bus-type dependent */
524 if (test_bit(bus, mp_bus_not_pci))
525 trigger = default_ISA_trigger(idx);
527 trigger = default_PCI_trigger(idx);
534 case 2: /* reserved */
536 printk(KERN_WARNING "broken BIOS!!\n");
545 default: /* invalid */
547 printk(KERN_WARNING "broken BIOS!!\n");
555 static inline int irq_polarity(int idx)
557 return MPBIOS_polarity(idx);
560 static inline int irq_trigger(int idx)
562 return MPBIOS_trigger(idx);
565 static int pin_2_irq(int idx, int apic, int pin)
568 int bus = mp_irqs[idx].mpc_srcbus;
571 * Debugging check, we are in big trouble if this message pops up!
573 if (mp_irqs[idx].mpc_dstirq != pin)
574 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
576 if (test_bit(bus, mp_bus_not_pci)) {
577 irq = mp_irqs[idx].mpc_srcbusirq;
580 * PCI IRQs are mapped in order
584 irq += nr_ioapic_registers[i++];
587 BUG_ON(irq >= NR_IRQS);
591 static inline int IO_APIC_irq_trigger(int irq)
595 for (apic = 0; apic < nr_ioapics; apic++) {
596 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
597 idx = find_irq_entry(apic,pin,mp_INT);
598 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
599 return irq_trigger(idx);
603 * nonexistent IRQs are edge default
608 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
609 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
610 [0] = FIRST_EXTERNAL_VECTOR + 0,
611 [1] = FIRST_EXTERNAL_VECTOR + 1,
612 [2] = FIRST_EXTERNAL_VECTOR + 2,
613 [3] = FIRST_EXTERNAL_VECTOR + 3,
614 [4] = FIRST_EXTERNAL_VECTOR + 4,
615 [5] = FIRST_EXTERNAL_VECTOR + 5,
616 [6] = FIRST_EXTERNAL_VECTOR + 6,
617 [7] = FIRST_EXTERNAL_VECTOR + 7,
618 [8] = FIRST_EXTERNAL_VECTOR + 8,
619 [9] = FIRST_EXTERNAL_VECTOR + 9,
620 [10] = FIRST_EXTERNAL_VECTOR + 10,
621 [11] = FIRST_EXTERNAL_VECTOR + 11,
622 [12] = FIRST_EXTERNAL_VECTOR + 12,
623 [13] = FIRST_EXTERNAL_VECTOR + 13,
624 [14] = FIRST_EXTERNAL_VECTOR + 14,
625 [15] = FIRST_EXTERNAL_VECTOR + 15,
628 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
647 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
650 * NOTE! The local APIC isn't very good at handling
651 * multiple interrupts at the same interrupt level.
652 * As the interrupt level is determined by taking the
653 * vector number and shifting that right by 4, we
654 * want to spread these out a bit so that they don't
655 * all fall in the same interrupt level.
657 * Also, we've got to be careful not to trash gate
658 * 0x80, because int 0x80 is hm, kind of importantish. ;)
660 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
664 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
666 /* Only try and allocate irqs on cpus that are present */
667 cpus_and(mask, mask, cpu_online_map);
669 if (irq_vector[irq] > 0)
670 old_vector = irq_vector[irq];
671 if (old_vector > 0) {
672 cpus_and(*result, irq_domain[irq], mask);
673 if (!cpus_empty(*result))
677 for_each_cpu_mask(cpu, mask) {
678 cpumask_t domain, new_mask;
682 domain = vector_allocation_domain(cpu);
683 cpus_and(new_mask, domain, cpu_online_map);
685 vector = current_vector;
686 offset = current_offset;
689 if (vector >= FIRST_SYSTEM_VECTOR) {
690 /* If we run out of vectors on large boxen, must share them. */
691 offset = (offset + 1) % 8;
692 vector = FIRST_DEVICE_VECTOR + offset;
694 if (unlikely(current_vector == vector))
696 if (vector == IA32_SYSCALL_VECTOR)
698 for_each_cpu_mask(new_cpu, new_mask)
699 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
702 current_vector = vector;
703 current_offset = offset;
704 if (old_vector >= 0) {
707 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
708 for_each_cpu_mask(old_cpu, old_mask)
709 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
711 for_each_cpu_mask(new_cpu, new_mask)
712 per_cpu(vector_irq, new_cpu)[vector] = irq;
713 irq_vector[irq] = vector;
714 irq_domain[irq] = domain;
715 cpus_and(*result, domain, mask);
721 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
726 spin_lock_irqsave(&vector_lock, flags);
727 vector = __assign_irq_vector(irq, mask, result);
728 spin_unlock_irqrestore(&vector_lock, flags);
732 static void __clear_irq_vector(int irq)
737 BUG_ON(!irq_vector[irq]);
739 vector = irq_vector[irq];
740 cpus_and(mask, irq_domain[irq], cpu_online_map);
741 for_each_cpu_mask(cpu, mask)
742 per_cpu(vector_irq, cpu)[vector] = -1;
745 irq_domain[irq] = CPU_MASK_NONE;
748 void __setup_vector_irq(int cpu)
750 /* Initialize vector_irq on a new cpu */
751 /* This function must be called with vector_lock held */
754 /* Mark the inuse vectors */
755 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
756 if (!cpu_isset(cpu, irq_domain[irq]))
758 vector = irq_vector[irq];
759 per_cpu(vector_irq, cpu)[vector] = irq;
761 /* Mark the free vectors */
762 for (vector = 0; vector < NR_VECTORS; ++vector) {
763 irq = per_cpu(vector_irq, cpu)[vector];
766 if (!cpu_isset(cpu, irq_domain[irq]))
767 per_cpu(vector_irq, cpu)[vector] = -1;
772 extern void (*interrupt[NR_IRQS])(void);
774 static struct irq_chip ioapic_chip;
776 #define IOAPIC_AUTO -1
777 #define IOAPIC_EDGE 0
778 #define IOAPIC_LEVEL 1
780 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
782 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
783 trigger == IOAPIC_LEVEL)
784 set_irq_chip_and_handler_name(irq, &ioapic_chip,
785 handle_fasteoi_irq, "fasteoi");
787 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
788 set_irq_chip_and_handler_name(irq, &ioapic_chip,
789 handle_edge_irq, "edge");
793 static void __init setup_IO_APIC_irqs(void)
795 struct IO_APIC_route_entry entry;
796 int apic, pin, idx, irq, first_notcon = 1, vector;
799 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
801 for (apic = 0; apic < nr_ioapics; apic++) {
802 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
805 * add it to the IO-APIC irq-routing table:
807 memset(&entry,0,sizeof(entry));
809 entry.delivery_mode = INT_DELIVERY_MODE;
810 entry.dest_mode = INT_DEST_MODE;
811 entry.mask = 0; /* enable IRQ */
812 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
814 idx = find_irq_entry(apic,pin,mp_INT);
817 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
820 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
824 entry.trigger = irq_trigger(idx);
825 entry.polarity = irq_polarity(idx);
827 if (irq_trigger(idx)) {
830 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
833 irq = pin_2_irq(idx, apic, pin);
834 add_pin_to_irq(irq, apic, pin);
836 if (!apic && !IO_APIC_IRQ(irq))
839 if (IO_APIC_IRQ(irq)) {
841 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
845 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
846 entry.vector = vector;
848 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
849 if (!apic && (irq < 16))
850 disable_8259A_irq(irq);
852 ioapic_write_entry(apic, pin, entry);
854 spin_lock_irqsave(&ioapic_lock, flags);
855 set_native_irq_info(irq, TARGET_CPUS);
856 spin_unlock_irqrestore(&ioapic_lock, flags);
861 apic_printk(APIC_VERBOSE," not connected.\n");
865 * Set up the 8259A-master output pin as broadcast to all
868 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
870 struct IO_APIC_route_entry entry;
873 memset(&entry,0,sizeof(entry));
875 disable_8259A_irq(0);
878 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
881 * We use logical delivery to get the timer IRQ
884 entry.dest_mode = INT_DEST_MODE;
885 entry.mask = 0; /* unmask IRQ now */
886 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
887 entry.delivery_mode = INT_DELIVERY_MODE;
890 entry.vector = vector;
893 * The timer IRQ doesn't have to know that behind the
894 * scene we have a 8259A-master in AEOI mode ...
896 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
899 * Add it to the IO-APIC irq-routing table:
901 spin_lock_irqsave(&ioapic_lock, flags);
902 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
903 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
904 spin_unlock_irqrestore(&ioapic_lock, flags);
909 void __init UNEXPECTED_IO_APIC(void)
913 void __apicdebuginit print_IO_APIC(void)
916 union IO_APIC_reg_00 reg_00;
917 union IO_APIC_reg_01 reg_01;
918 union IO_APIC_reg_02 reg_02;
921 if (apic_verbosity == APIC_QUIET)
924 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
925 for (i = 0; i < nr_ioapics; i++)
926 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
927 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
930 * We are a bit conservative about what we expect. We have to
931 * know about every hardware change ASAP.
933 printk(KERN_INFO "testing the IO APIC.......................\n");
935 for (apic = 0; apic < nr_ioapics; apic++) {
937 spin_lock_irqsave(&ioapic_lock, flags);
938 reg_00.raw = io_apic_read(apic, 0);
939 reg_01.raw = io_apic_read(apic, 1);
940 if (reg_01.bits.version >= 0x10)
941 reg_02.raw = io_apic_read(apic, 2);
942 spin_unlock_irqrestore(&ioapic_lock, flags);
945 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
946 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
947 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
948 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
949 UNEXPECTED_IO_APIC();
951 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
952 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
953 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
954 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
955 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
956 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
957 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
958 (reg_01.bits.entries != 0x2E) &&
959 (reg_01.bits.entries != 0x3F) &&
960 (reg_01.bits.entries != 0x03)
962 UNEXPECTED_IO_APIC();
964 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
965 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
966 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
967 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
968 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
969 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
970 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
971 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
973 UNEXPECTED_IO_APIC();
974 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
975 UNEXPECTED_IO_APIC();
977 if (reg_01.bits.version >= 0x10) {
978 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
979 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
980 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
981 UNEXPECTED_IO_APIC();
984 printk(KERN_DEBUG ".... IRQ redirection table:\n");
986 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
987 " Stat Dest Deli Vect: \n");
989 for (i = 0; i <= reg_01.bits.entries; i++) {
990 struct IO_APIC_route_entry entry;
992 entry = ioapic_read_entry(apic, i);
994 printk(KERN_DEBUG " %02x %03X %02X ",
996 entry.dest.logical.logical_dest,
997 entry.dest.physical.physical_dest
1000 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1005 entry.delivery_status,
1007 entry.delivery_mode,
1012 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1013 for (i = 0; i < NR_IRQS; i++) {
1014 struct irq_pin_list *entry = irq_2_pin + i;
1017 printk(KERN_DEBUG "IRQ%d ", i);
1019 printk("-> %d:%d", entry->apic, entry->pin);
1022 entry = irq_2_pin + entry->next;
1027 printk(KERN_INFO ".................................... done.\n");
1034 static __apicdebuginit void print_APIC_bitfield (int base)
1039 if (apic_verbosity == APIC_QUIET)
1042 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1043 for (i = 0; i < 8; i++) {
1044 v = apic_read(base + i*0x10);
1045 for (j = 0; j < 32; j++) {
1055 void __apicdebuginit print_local_APIC(void * dummy)
1057 unsigned int v, ver, maxlvt;
1059 if (apic_verbosity == APIC_QUIET)
1062 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1063 smp_processor_id(), hard_smp_processor_id());
1064 v = apic_read(APIC_ID);
1065 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1066 v = apic_read(APIC_LVR);
1067 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1068 ver = GET_APIC_VERSION(v);
1069 maxlvt = get_maxlvt();
1071 v = apic_read(APIC_TASKPRI);
1072 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1074 v = apic_read(APIC_ARBPRI);
1075 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1076 v & APIC_ARBPRI_MASK);
1077 v = apic_read(APIC_PROCPRI);
1078 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1080 v = apic_read(APIC_EOI);
1081 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1082 v = apic_read(APIC_RRR);
1083 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1084 v = apic_read(APIC_LDR);
1085 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1086 v = apic_read(APIC_DFR);
1087 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1088 v = apic_read(APIC_SPIV);
1089 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1091 printk(KERN_DEBUG "... APIC ISR field:\n");
1092 print_APIC_bitfield(APIC_ISR);
1093 printk(KERN_DEBUG "... APIC TMR field:\n");
1094 print_APIC_bitfield(APIC_TMR);
1095 printk(KERN_DEBUG "... APIC IRR field:\n");
1096 print_APIC_bitfield(APIC_IRR);
1098 v = apic_read(APIC_ESR);
1099 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1101 v = apic_read(APIC_ICR);
1102 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1103 v = apic_read(APIC_ICR2);
1104 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1106 v = apic_read(APIC_LVTT);
1107 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1109 if (maxlvt > 3) { /* PC is LVT#4. */
1110 v = apic_read(APIC_LVTPC);
1111 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1113 v = apic_read(APIC_LVT0);
1114 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1115 v = apic_read(APIC_LVT1);
1116 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1118 if (maxlvt > 2) { /* ERR is LVT#3. */
1119 v = apic_read(APIC_LVTERR);
1120 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1123 v = apic_read(APIC_TMICT);
1124 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1125 v = apic_read(APIC_TMCCT);
1126 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1127 v = apic_read(APIC_TDCR);
1128 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1132 void print_all_local_APICs (void)
1134 on_each_cpu(print_local_APIC, NULL, 1, 1);
1137 void __apicdebuginit print_PIC(void)
1140 unsigned long flags;
1142 if (apic_verbosity == APIC_QUIET)
1145 printk(KERN_DEBUG "\nprinting PIC contents\n");
1147 spin_lock_irqsave(&i8259A_lock, flags);
1149 v = inb(0xa1) << 8 | inb(0x21);
1150 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1152 v = inb(0xa0) << 8 | inb(0x20);
1153 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1157 v = inb(0xa0) << 8 | inb(0x20);
1161 spin_unlock_irqrestore(&i8259A_lock, flags);
1163 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1165 v = inb(0x4d1) << 8 | inb(0x4d0);
1166 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1171 static void __init enable_IO_APIC(void)
1173 union IO_APIC_reg_01 reg_01;
1174 int i8259_apic, i8259_pin;
1176 unsigned long flags;
1178 for (i = 0; i < PIN_MAP_SIZE; i++) {
1179 irq_2_pin[i].pin = -1;
1180 irq_2_pin[i].next = 0;
1184 * The number of IO-APIC IRQ registers (== #pins):
1186 for (apic = 0; apic < nr_ioapics; apic++) {
1187 spin_lock_irqsave(&ioapic_lock, flags);
1188 reg_01.raw = io_apic_read(apic, 1);
1189 spin_unlock_irqrestore(&ioapic_lock, flags);
1190 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1192 for(apic = 0; apic < nr_ioapics; apic++) {
1194 /* See if any of the pins is in ExtINT mode */
1195 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1196 struct IO_APIC_route_entry entry;
1197 entry = ioapic_read_entry(apic, pin);
1199 /* If the interrupt line is enabled and in ExtInt mode
1200 * I have found the pin where the i8259 is connected.
1202 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1203 ioapic_i8259.apic = apic;
1204 ioapic_i8259.pin = pin;
1210 /* Look to see what if the MP table has reported the ExtINT */
1211 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1212 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1213 /* Trust the MP table if nothing is setup in the hardware */
1214 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1215 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1216 ioapic_i8259.pin = i8259_pin;
1217 ioapic_i8259.apic = i8259_apic;
1219 /* Complain if the MP table and the hardware disagree */
1220 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1221 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1223 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1227 * Do not trust the IO-APIC being empty at bootup
1233 * Not an __init, needed by the reboot code
1235 void disable_IO_APIC(void)
1238 * Clear the IO-APIC before rebooting:
1243 * If the i8259 is routed through an IOAPIC
1244 * Put that IOAPIC in virtual wire mode
1245 * so legacy interrupts can be delivered.
1247 if (ioapic_i8259.pin != -1) {
1248 struct IO_APIC_route_entry entry;
1250 memset(&entry, 0, sizeof(entry));
1251 entry.mask = 0; /* Enabled */
1252 entry.trigger = 0; /* Edge */
1254 entry.polarity = 0; /* High */
1255 entry.delivery_status = 0;
1256 entry.dest_mode = 0; /* Physical */
1257 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1259 entry.dest.physical.physical_dest =
1260 GET_APIC_ID(apic_read(APIC_ID));
1263 * Add it to the IO-APIC irq-routing table:
1265 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1268 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1272 * There is a nasty bug in some older SMP boards, their mptable lies
1273 * about the timer IRQ. We do the following to work around the situation:
1275 * - timer IRQ defaults to IO-APIC IRQ
1276 * - if this function detects that timer IRQs are defunct, then we fall
1277 * back to ISA timer IRQs
1279 static int __init timer_irq_works(void)
1281 unsigned long t1 = jiffies;
1284 /* Let ten ticks pass... */
1285 mdelay((10 * 1000) / HZ);
1288 * Expect a few ticks at least, to be sure some possible
1289 * glue logic does not lock up after one or two first
1290 * ticks in a non-ExtINT mode. Also the local APIC
1291 * might have cached one ExtINT interrupt. Finally, at
1292 * least one tick may be lost due to delays.
1296 if (jiffies - t1 > 4)
1302 * In the SMP+IOAPIC case it might happen that there are an unspecified
1303 * number of pending IRQ events unhandled. These cases are very rare,
1304 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1305 * better to do it this way as thus we do not have to be aware of
1306 * 'pending' interrupts in the IRQ path, except at this point.
1309 * Edge triggered needs to resend any interrupt
1310 * that was delayed but this is now handled in the device
1315 * Starting up a edge-triggered IO-APIC interrupt is
1316 * nasty - we need to make sure that we get the edge.
1317 * If it is already asserted for some reason, we need
1318 * return 1 to indicate that is was pending.
1320 * This is not complete - we should be able to fake
1321 * an edge even if it isn't on the 8259A...
1324 static unsigned int startup_ioapic_irq(unsigned int irq)
1326 int was_pending = 0;
1327 unsigned long flags;
1329 spin_lock_irqsave(&ioapic_lock, flags);
1331 disable_8259A_irq(irq);
1332 if (i8259A_irq_pending(irq))
1335 __unmask_IO_APIC_irq(irq);
1336 spin_unlock_irqrestore(&ioapic_lock, flags);
1341 static int ioapic_retrigger_irq(unsigned int irq)
1345 unsigned long flags;
1347 spin_lock_irqsave(&vector_lock, flags);
1348 vector = irq_vector[irq];
1350 cpu_set(first_cpu(irq_domain[irq]), mask);
1352 send_IPI_mask(mask, vector);
1353 spin_unlock_irqrestore(&vector_lock, flags);
1359 * Level and edge triggered IO-APIC interrupts need different handling,
1360 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1361 * handled with the level-triggered descriptor, but that one has slightly
1362 * more overhead. Level-triggered interrupts cannot be handled with the
1363 * edge-triggered handler, without risking IRQ storms and other ugly
1367 static void ack_apic_edge(unsigned int irq)
1369 move_native_irq(irq);
1373 static void ack_apic_level(unsigned int irq)
1375 int do_unmask_irq = 0;
1377 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1378 /* If we are moving the irq we need to mask it */
1379 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1381 mask_IO_APIC_irq(irq);
1386 * We must acknowledge the irq before we move it or the acknowledge will
1387 * not propogate properly.
1391 /* Now we can move and renable the irq */
1392 move_masked_irq(irq);
1393 if (unlikely(do_unmask_irq))
1394 unmask_IO_APIC_irq(irq);
1397 static struct irq_chip ioapic_chip __read_mostly = {
1399 .startup = startup_ioapic_irq,
1400 .mask = mask_IO_APIC_irq,
1401 .unmask = unmask_IO_APIC_irq,
1402 .ack = ack_apic_edge,
1403 .eoi = ack_apic_level,
1405 .set_affinity = set_ioapic_affinity_irq,
1407 .retrigger = ioapic_retrigger_irq,
1410 static inline void init_IO_APIC_traps(void)
1415 * NOTE! The local APIC isn't very good at handling
1416 * multiple interrupts at the same interrupt level.
1417 * As the interrupt level is determined by taking the
1418 * vector number and shifting that right by 4, we
1419 * want to spread these out a bit so that they don't
1420 * all fall in the same interrupt level.
1422 * Also, we've got to be careful not to trash gate
1423 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1425 for (irq = 0; irq < NR_IRQS ; irq++) {
1427 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1429 * Hmm.. We don't have an entry for this,
1430 * so default to an old-fashioned 8259
1431 * interrupt if we can..
1434 make_8259A_irq(irq);
1436 /* Strange. Oh, well.. */
1437 irq_desc[irq].chip = &no_irq_chip;
1442 static void enable_lapic_irq (unsigned int irq)
1446 v = apic_read(APIC_LVT0);
1447 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1450 static void disable_lapic_irq (unsigned int irq)
1454 v = apic_read(APIC_LVT0);
1455 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1458 static void ack_lapic_irq (unsigned int irq)
1463 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1465 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1466 .typename = "local-APIC-edge",
1467 .startup = NULL, /* startup_irq() not used for IRQ0 */
1468 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1469 .enable = enable_lapic_irq,
1470 .disable = disable_lapic_irq,
1471 .ack = ack_lapic_irq,
1472 .end = end_lapic_irq,
1475 static void setup_nmi (void)
1478 * Dirty trick to enable the NMI watchdog ...
1479 * We put the 8259A master into AEOI mode and
1480 * unmask on all local APICs LVT0 as NMI.
1482 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1483 * is from Maciej W. Rozycki - so we do not have to EOI from
1484 * the NMI handler or the timer interrupt.
1486 printk(KERN_INFO "activating NMI Watchdog ...");
1488 enable_NMI_through_LVT0(NULL);
1494 * This looks a bit hackish but it's about the only one way of sending
1495 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1496 * not support the ExtINT mode, unfortunately. We need to send these
1497 * cycles as some i82489DX-based boards have glue logic that keeps the
1498 * 8259A interrupt line asserted until INTA. --macro
1500 static inline void unlock_ExtINT_logic(void)
1503 struct IO_APIC_route_entry entry0, entry1;
1504 unsigned char save_control, save_freq_select;
1505 unsigned long flags;
1507 pin = find_isa_irq_pin(8, mp_INT);
1508 apic = find_isa_irq_apic(8, mp_INT);
1512 spin_lock_irqsave(&ioapic_lock, flags);
1513 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1514 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1515 spin_unlock_irqrestore(&ioapic_lock, flags);
1516 clear_IO_APIC_pin(apic, pin);
1518 memset(&entry1, 0, sizeof(entry1));
1520 entry1.dest_mode = 0; /* physical delivery */
1521 entry1.mask = 0; /* unmask IRQ now */
1522 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1523 entry1.delivery_mode = dest_ExtINT;
1524 entry1.polarity = entry0.polarity;
1528 spin_lock_irqsave(&ioapic_lock, flags);
1529 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1530 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1531 spin_unlock_irqrestore(&ioapic_lock, flags);
1533 save_control = CMOS_READ(RTC_CONTROL);
1534 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1535 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1537 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1542 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1546 CMOS_WRITE(save_control, RTC_CONTROL);
1547 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1548 clear_IO_APIC_pin(apic, pin);
1550 spin_lock_irqsave(&ioapic_lock, flags);
1551 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1552 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1553 spin_unlock_irqrestore(&ioapic_lock, flags);
1557 * This code may look a bit paranoid, but it's supposed to cooperate with
1558 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1559 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1560 * fanatically on his truly buggy board.
1563 static int try_apic_pin(int apic, int pin, char *msg)
1565 apic_printk(APIC_VERBOSE, KERN_INFO
1566 "..TIMER: trying IO-APIC=%d PIN=%d %s",
1570 * Ok, does IRQ0 through the IOAPIC work?
1572 if (!no_timer_check && timer_irq_works()) {
1573 nmi_watchdog_default();
1574 if (nmi_watchdog == NMI_IO_APIC) {
1575 disable_8259A_irq(0);
1577 enable_8259A_irq(0);
1581 clear_IO_APIC_pin(apic, pin);
1582 apic_printk(APIC_QUIET, KERN_ERR " .. failed\n");
1586 /* The function from hell */
1587 static void check_timer(void)
1589 int apic1, pin1, apic2, pin2;
1594 * get/set the timer IRQ vector:
1596 disable_8259A_irq(0);
1597 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1600 * Subtle, code in do_timer_interrupt() expects an AEOI
1601 * mode for the 8259A whenever interrupts are routed
1602 * through I/O APICs. Also IRQ0 has to be enabled in
1603 * the 8259A which implies the virtual wire has to be
1604 * disabled in the local APIC.
1606 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1609 pin1 = find_isa_irq_pin(0, mp_INT);
1610 apic1 = find_isa_irq_apic(0, mp_INT);
1611 pin2 = ioapic_i8259.pin;
1612 apic2 = ioapic_i8259.apic;
1614 /* Do this first, otherwise we get double interrupts on ATI boards */
1615 if ((pin1 != -1) && try_apic_pin(apic1, pin1,"with 8259 IRQ0 disabled"))
1618 /* Now try again with IRQ0 8259A enabled.
1619 Assumes timer is on IO-APIC 0 ?!? */
1620 enable_8259A_irq(0);
1621 unmask_IO_APIC_irq(0);
1622 if (try_apic_pin(apic1, pin1, "with 8259 IRQ0 enabled"))
1624 disable_8259A_irq(0);
1626 /* Always try pin0 and pin2 on APIC 0 to handle buggy timer overrides
1628 if (!(apic1 == 0 && pin1 == 0) &&
1629 try_apic_pin(0, 0, "fallback with 8259 IRQ0 disabled"))
1631 if (!(apic1 == 0 && pin1 == 2) &&
1632 try_apic_pin(0, 2, "fallback with 8259 IRQ0 disabled"))
1635 /* Then try pure 8259A routing on the 8259 as reported by BIOS*/
1636 enable_8259A_irq(0);
1638 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1639 if (try_apic_pin(apic2,pin2,"8259A broadcast ExtINT from BIOS"))
1643 /* Tried all possibilities to go through the IO-APIC. Now come the
1644 really cheesy fallbacks. */
1646 if (nmi_watchdog == NMI_IO_APIC) {
1647 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1651 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1653 disable_8259A_irq(0);
1654 irq_desc[0].chip = &lapic_irq_type;
1655 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1656 enable_8259A_irq(0);
1658 if (timer_irq_works()) {
1659 apic_printk(APIC_VERBOSE," works.\n");
1662 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1663 apic_printk(APIC_VERBOSE," failed.\n");
1665 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1669 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1671 unlock_ExtINT_logic();
1673 if (timer_irq_works()) {
1674 apic_printk(APIC_VERBOSE," works.\n");
1677 apic_printk(APIC_VERBOSE," failed :(.\n");
1678 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1681 static int __init notimercheck(char *s)
1686 __setup("no_timer_check", notimercheck);
1690 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1691 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1692 * Linux doesn't really care, as it's not actually used
1693 * for any interrupt handling anyway.
1695 #define PIC_IRQS (1<<2)
1697 void __init setup_IO_APIC(void)
1702 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1704 io_apic_irqs = ~PIC_IRQS;
1706 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1709 setup_IO_APIC_irqs();
1710 init_IO_APIC_traps();
1716 struct sysfs_ioapic_data {
1717 struct sys_device dev;
1718 struct IO_APIC_route_entry entry[0];
1720 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1722 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1724 struct IO_APIC_route_entry *entry;
1725 struct sysfs_ioapic_data *data;
1728 data = container_of(dev, struct sysfs_ioapic_data, dev);
1729 entry = data->entry;
1730 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1731 *entry = ioapic_read_entry(dev->id, i);
1736 static int ioapic_resume(struct sys_device *dev)
1738 struct IO_APIC_route_entry *entry;
1739 struct sysfs_ioapic_data *data;
1740 unsigned long flags;
1741 union IO_APIC_reg_00 reg_00;
1744 data = container_of(dev, struct sysfs_ioapic_data, dev);
1745 entry = data->entry;
1747 spin_lock_irqsave(&ioapic_lock, flags);
1748 reg_00.raw = io_apic_read(dev->id, 0);
1749 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1750 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1751 io_apic_write(dev->id, 0, reg_00.raw);
1753 spin_unlock_irqrestore(&ioapic_lock, flags);
1754 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1755 ioapic_write_entry(dev->id, i, entry[i]);
1760 static struct sysdev_class ioapic_sysdev_class = {
1761 set_kset_name("ioapic"),
1762 .suspend = ioapic_suspend,
1763 .resume = ioapic_resume,
1766 static int __init ioapic_init_sysfs(void)
1768 struct sys_device * dev;
1769 int i, size, error = 0;
1771 error = sysdev_class_register(&ioapic_sysdev_class);
1775 for (i = 0; i < nr_ioapics; i++ ) {
1776 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1777 * sizeof(struct IO_APIC_route_entry);
1778 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1779 if (!mp_ioapic_data[i]) {
1780 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1783 memset(mp_ioapic_data[i], 0, size);
1784 dev = &mp_ioapic_data[i]->dev;
1786 dev->cls = &ioapic_sysdev_class;
1787 error = sysdev_register(dev);
1789 kfree(mp_ioapic_data[i]);
1790 mp_ioapic_data[i] = NULL;
1791 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1799 device_initcall(ioapic_init_sysfs);
1802 * Dynamic irq allocate and deallocation
1804 int create_irq(void)
1806 /* Allocate an unused irq */
1810 unsigned long flags;
1814 spin_lock_irqsave(&vector_lock, flags);
1815 for (new = (NR_IRQS - 1); new >= 0; new--) {
1816 if (platform_legacy_irq(new))
1818 if (irq_vector[new] != 0)
1820 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1821 if (likely(vector > 0))
1825 spin_unlock_irqrestore(&vector_lock, flags);
1828 dynamic_irq_init(irq);
1833 void destroy_irq(unsigned int irq)
1835 unsigned long flags;
1837 dynamic_irq_cleanup(irq);
1839 spin_lock_irqsave(&vector_lock, flags);
1840 __clear_irq_vector(irq);
1841 spin_unlock_irqrestore(&vector_lock, flags);
1845 * MSI mesage composition
1847 #ifdef CONFIG_PCI_MSI
1848 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1854 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1856 dest = cpu_mask_to_apicid(tmp);
1858 msg->address_hi = MSI_ADDR_BASE_HI;
1861 ((INT_DEST_MODE == 0) ?
1862 MSI_ADDR_DEST_MODE_PHYSICAL:
1863 MSI_ADDR_DEST_MODE_LOGICAL) |
1864 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1865 MSI_ADDR_REDIRECTION_CPU:
1866 MSI_ADDR_REDIRECTION_LOWPRI) |
1867 MSI_ADDR_DEST_ID(dest);
1870 MSI_DATA_TRIGGER_EDGE |
1871 MSI_DATA_LEVEL_ASSERT |
1872 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1873 MSI_DATA_DELIVERY_FIXED:
1874 MSI_DATA_DELIVERY_LOWPRI) |
1875 MSI_DATA_VECTOR(vector);
1881 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1888 cpus_and(tmp, mask, cpu_online_map);
1889 if (cpus_empty(tmp))
1892 cpus_and(mask, tmp, CPU_MASK_ALL);
1894 vector = assign_irq_vector(irq, mask, &tmp);
1898 dest = cpu_mask_to_apicid(tmp);
1900 read_msi_msg(irq, &msg);
1902 msg.data &= ~MSI_DATA_VECTOR_MASK;
1903 msg.data |= MSI_DATA_VECTOR(vector);
1904 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1905 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1907 write_msi_msg(irq, &msg);
1908 set_native_irq_info(irq, mask);
1910 #endif /* CONFIG_SMP */
1913 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1914 * which implement the MSI or MSI-X Capability Structure.
1916 static struct irq_chip msi_chip = {
1918 .unmask = unmask_msi_irq,
1919 .mask = mask_msi_irq,
1920 .ack = ack_apic_edge,
1922 .set_affinity = set_msi_irq_affinity,
1924 .retrigger = ioapic_retrigger_irq,
1927 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1931 ret = msi_compose_msg(dev, irq, &msg);
1935 write_msi_msg(irq, &msg);
1937 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1942 void arch_teardown_msi_irq(unsigned int irq)
1947 #endif /* CONFIG_PCI_MSI */
1950 * Hypertransport interrupt support
1952 #ifdef CONFIG_HT_IRQ
1956 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1958 struct ht_irq_msg msg;
1959 fetch_ht_irq_msg(irq, &msg);
1961 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1962 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1964 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1965 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1967 write_ht_irq_msg(irq, &msg);
1970 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1976 cpus_and(tmp, mask, cpu_online_map);
1977 if (cpus_empty(tmp))
1980 cpus_and(mask, tmp, CPU_MASK_ALL);
1982 vector = assign_irq_vector(irq, mask, &tmp);
1986 dest = cpu_mask_to_apicid(tmp);
1988 target_ht_irq(irq, dest, vector);
1989 set_native_irq_info(irq, mask);
1993 static struct irq_chip ht_irq_chip = {
1995 .mask = mask_ht_irq,
1996 .unmask = unmask_ht_irq,
1997 .ack = ack_apic_edge,
1999 .set_affinity = set_ht_irq_affinity,
2001 .retrigger = ioapic_retrigger_irq,
2004 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2009 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2011 struct ht_irq_msg msg;
2014 dest = cpu_mask_to_apicid(tmp);
2016 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2020 HT_IRQ_LOW_DEST_ID(dest) |
2021 HT_IRQ_LOW_VECTOR(vector) |
2022 ((INT_DEST_MODE == 0) ?
2023 HT_IRQ_LOW_DM_PHYSICAL :
2024 HT_IRQ_LOW_DM_LOGICAL) |
2025 HT_IRQ_LOW_RQEOI_EDGE |
2026 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2027 HT_IRQ_LOW_MT_FIXED :
2028 HT_IRQ_LOW_MT_ARBITRATED) |
2029 HT_IRQ_LOW_IRQ_MASKED;
2031 write_ht_irq_msg(irq, &msg);
2033 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2034 handle_edge_irq, "edge");
2038 #endif /* CONFIG_HT_IRQ */
2040 /* --------------------------------------------------------------------------
2041 ACPI-based IOAPIC Configuration
2042 -------------------------------------------------------------------------- */
2046 #define IO_APIC_MAX_ID 0xFE
2048 int __init io_apic_get_redir_entries (int ioapic)
2050 union IO_APIC_reg_01 reg_01;
2051 unsigned long flags;
2053 spin_lock_irqsave(&ioapic_lock, flags);
2054 reg_01.raw = io_apic_read(ioapic, 1);
2055 spin_unlock_irqrestore(&ioapic_lock, flags);
2057 return reg_01.bits.entries;
2061 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2063 struct IO_APIC_route_entry entry;
2064 unsigned long flags;
2068 if (!IO_APIC_IRQ(irq)) {
2069 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2075 * IRQs < 16 are already in the irq_2_pin[] map
2078 add_pin_to_irq(irq, ioapic, pin);
2081 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2086 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2087 * Note that we mask (disable) IRQs now -- these get enabled when the
2088 * corresponding device driver registers for this IRQ.
2091 memset(&entry,0,sizeof(entry));
2093 entry.delivery_mode = INT_DELIVERY_MODE;
2094 entry.dest_mode = INT_DEST_MODE;
2095 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2096 entry.trigger = triggering;
2097 entry.polarity = polarity;
2098 entry.mask = 1; /* Disabled (masked) */
2099 entry.vector = vector & 0xff;
2101 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2102 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2103 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2104 triggering, polarity);
2106 ioapic_register_intr(irq, entry.vector, triggering);
2108 if (!ioapic && (irq < 16))
2109 disable_8259A_irq(irq);
2111 ioapic_write_entry(ioapic, pin, entry);
2113 spin_lock_irqsave(&ioapic_lock, flags);
2114 set_native_irq_info(irq, TARGET_CPUS);
2115 spin_unlock_irqrestore(&ioapic_lock, flags);
2120 #endif /* CONFIG_ACPI */
2124 * This function currently is only a helper for the i386 smp boot process where
2125 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2126 * so mask in all cases should simply be TARGET_CPUS
2129 void __init setup_ioapic_dest(void)
2131 int pin, ioapic, irq, irq_entry;
2133 if (skip_ioapic_setup == 1)
2136 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2137 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2138 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2139 if (irq_entry == -1)
2141 irq = pin_2_irq(irq_entry, ioapic, pin);
2142 set_ioapic_affinity_irq(irq, TARGET_CPUS);