2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
52 #define __apicdebuginit __init
54 int sis_apic_bug; /* not actually supported, dummy for compile */
56 static int no_timer_check;
58 static int disable_timer_pin_1 __initdata;
60 int timer_over_8254 __initdata = 1;
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
65 static DEFINE_SPINLOCK(ioapic_lock);
66 DEFINE_SPINLOCK(vector_lock);
69 * # of IRQ routing registers
71 int nr_ioapic_registers[MAX_IO_APICS];
74 * Rough estimation of how many shared IRQs there are, can
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
81 * This is performance-critical, we want to do it O(1)
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
87 static struct irq_pin_list {
88 short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
93 unsigned int unused[3];
97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
99 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
100 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
105 struct io_apic __iomem *io_apic = io_apic_base(apic);
106 writel(reg, &io_apic->index);
107 return readl(&io_apic->data);
110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
112 struct io_apic __iomem *io_apic = io_apic_base(apic);
113 writel(reg, &io_apic->index);
114 writel(value, &io_apic->data);
118 * Re-write a value: to be used for read-modify-write
119 * cycles where the read already set up the index register.
121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
123 struct io_apic __iomem *io_apic = io_apic_base(apic);
124 writel(value, &io_apic->data);
128 * Synchronize the IO-APIC and the CPU by doing
129 * a dummy read from the IO-APIC
131 static inline void io_apic_sync(unsigned int apic)
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 readl(&io_apic->data);
137 #define __DO_ACTION(R, ACTION, FINAL) \
141 struct irq_pin_list *entry = irq_2_pin + irq; \
143 BUG_ON(irq >= NR_IRQS); \
149 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
151 io_apic_modify(entry->apic, reg); \
154 entry = irq_2_pin + entry->next; \
160 struct { u32 w1, w2; };
161 struct IO_APIC_route_entry entry;
164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
166 union entry_union eu;
168 spin_lock_irqsave(&ioapic_lock, flags);
169 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
170 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
171 spin_unlock_irqrestore(&ioapic_lock, flags);
176 * When we write a new IO APIC routing entry, we need to write the high
177 * word first! If the mask bit in the low word is clear, we will enable
178 * the interrupt, and we need to make sure the entry is fully populated
179 * before that happens.
182 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
184 union entry_union eu;
186 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
187 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
190 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
193 spin_lock_irqsave(&ioapic_lock, flags);
194 __ioapic_write_entry(apic, pin, e);
195 spin_unlock_irqrestore(&ioapic_lock, flags);
199 * When we mask an IO APIC routing entry, we need to write the low
200 * word first, in order to set the mask bit before we change the
203 static void ioapic_mask_entry(int apic, int pin)
206 union entry_union eu = { .entry.mask = 1 };
208 spin_lock_irqsave(&ioapic_lock, flags);
209 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
210 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
211 spin_unlock_irqrestore(&ioapic_lock, flags);
215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
218 struct irq_pin_list *entry = irq_2_pin + irq;
220 BUG_ON(irq >= NR_IRQS);
227 io_apic_write(apic, 0x11 + pin*2, dest);
228 reg = io_apic_read(apic, 0x10 + pin*2);
231 io_apic_modify(apic, reg);
234 entry = irq_2_pin + entry->next;
238 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
245 cpus_and(tmp, mask, cpu_online_map);
249 cpus_and(mask, tmp, CPU_MASK_ALL);
251 vector = assign_irq_vector(irq, mask, &tmp);
255 dest = cpu_mask_to_apicid(tmp);
258 * Only the high 8 bits are valid.
260 dest = SET_APIC_LOGICAL_ID(dest);
262 spin_lock_irqsave(&ioapic_lock, flags);
263 __target_IO_APIC_irq(irq, dest, vector);
264 irq_desc[irq].affinity = mask;
265 spin_unlock_irqrestore(&ioapic_lock, flags);
270 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
271 * shared ISA-space IRQs, so we have to support them. We are super
272 * fast in the common case, and fast for shared ISA-space IRQs.
274 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
276 static int first_free_entry = NR_IRQS;
277 struct irq_pin_list *entry = irq_2_pin + irq;
279 BUG_ON(irq >= NR_IRQS);
281 entry = irq_2_pin + entry->next;
283 if (entry->pin != -1) {
284 entry->next = first_free_entry;
285 entry = irq_2_pin + entry->next;
286 if (++first_free_entry >= PIN_MAP_SIZE)
287 panic("io_apic.c: ran out of irq_2_pin entries!");
294 #define DO_ACTION(name,R,ACTION, FINAL) \
296 static void name##_IO_APIC_irq (unsigned int irq) \
297 __DO_ACTION(R, ACTION, FINAL)
299 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
301 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
304 static void mask_IO_APIC_irq (unsigned int irq)
308 spin_lock_irqsave(&ioapic_lock, flags);
309 __mask_IO_APIC_irq(irq);
310 spin_unlock_irqrestore(&ioapic_lock, flags);
313 static void unmask_IO_APIC_irq (unsigned int irq)
317 spin_lock_irqsave(&ioapic_lock, flags);
318 __unmask_IO_APIC_irq(irq);
319 spin_unlock_irqrestore(&ioapic_lock, flags);
322 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
324 struct IO_APIC_route_entry entry;
326 /* Check delivery_mode to be sure we're not clearing an SMI pin */
327 entry = ioapic_read_entry(apic, pin);
328 if (entry.delivery_mode == dest_SMI)
331 * Disable it in the IO-APIC irq-routing table:
333 ioapic_mask_entry(apic, pin);
336 static void clear_IO_APIC (void)
340 for (apic = 0; apic < nr_ioapics; apic++)
341 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
342 clear_IO_APIC_pin(apic, pin);
345 int skip_ioapic_setup;
348 /* dummy parsing: see setup.c */
350 static int __init disable_ioapic_setup(char *str)
352 skip_ioapic_setup = 1;
355 early_param("noapic", disable_ioapic_setup);
357 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
358 static int __init disable_timer_pin_setup(char *arg)
360 disable_timer_pin_1 = 1;
363 __setup("disable_timer_pin_1", disable_timer_pin_setup);
365 static int __init setup_disable_8254_timer(char *s)
367 timer_over_8254 = -1;
370 static int __init setup_enable_8254_timer(char *s)
376 __setup("disable_8254_timer", setup_disable_8254_timer);
377 __setup("enable_8254_timer", setup_enable_8254_timer);
381 * Find the IRQ entry number of a certain pin.
383 static int find_irq_entry(int apic, int pin, int type)
387 for (i = 0; i < mp_irq_entries; i++)
388 if (mp_irqs[i].mpc_irqtype == type &&
389 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
390 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
391 mp_irqs[i].mpc_dstirq == pin)
398 * Find the pin to which IRQ[irq] (ISA) is connected
400 static int __init find_isa_irq_pin(int irq, int type)
404 for (i = 0; i < mp_irq_entries; i++) {
405 int lbus = mp_irqs[i].mpc_srcbus;
407 if (test_bit(lbus, mp_bus_not_pci) &&
408 (mp_irqs[i].mpc_irqtype == type) &&
409 (mp_irqs[i].mpc_srcbusirq == irq))
411 return mp_irqs[i].mpc_dstirq;
416 static int __init find_isa_irq_apic(int irq, int type)
420 for (i = 0; i < mp_irq_entries; i++) {
421 int lbus = mp_irqs[i].mpc_srcbus;
423 if (test_bit(lbus, mp_bus_not_pci) &&
424 (mp_irqs[i].mpc_irqtype == type) &&
425 (mp_irqs[i].mpc_srcbusirq == irq))
428 if (i < mp_irq_entries) {
430 for(apic = 0; apic < nr_ioapics; apic++) {
431 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
440 * Find a specific PCI IRQ entry.
441 * Not an __init, possibly needed by modules
443 static int pin_2_irq(int idx, int apic, int pin);
445 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
447 int apic, i, best_guess = -1;
449 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
451 if (mp_bus_id_to_pci_bus[bus] == -1) {
452 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
455 for (i = 0; i < mp_irq_entries; i++) {
456 int lbus = mp_irqs[i].mpc_srcbus;
458 for (apic = 0; apic < nr_ioapics; apic++)
459 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
460 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
463 if (!test_bit(lbus, mp_bus_not_pci) &&
464 !mp_irqs[i].mpc_irqtype &&
466 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
467 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
469 if (!(apic || IO_APIC_IRQ(irq)))
472 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
475 * Use the first all-but-pin matching entry as a
476 * best-guess fuzzy result for broken mptables.
482 BUG_ON(best_guess >= NR_IRQS);
486 /* ISA interrupts are always polarity zero edge triggered,
487 * when listed as conforming in the MP table. */
489 #define default_ISA_trigger(idx) (0)
490 #define default_ISA_polarity(idx) (0)
492 /* PCI interrupts are always polarity one level triggered,
493 * when listed as conforming in the MP table. */
495 #define default_PCI_trigger(idx) (1)
496 #define default_PCI_polarity(idx) (1)
498 static int __init MPBIOS_polarity(int idx)
500 int bus = mp_irqs[idx].mpc_srcbus;
504 * Determine IRQ line polarity (high active or low active):
506 switch (mp_irqs[idx].mpc_irqflag & 3)
508 case 0: /* conforms, ie. bus-type dependent polarity */
509 if (test_bit(bus, mp_bus_not_pci))
510 polarity = default_ISA_polarity(idx);
512 polarity = default_PCI_polarity(idx);
514 case 1: /* high active */
519 case 2: /* reserved */
521 printk(KERN_WARNING "broken BIOS!!\n");
525 case 3: /* low active */
530 default: /* invalid */
532 printk(KERN_WARNING "broken BIOS!!\n");
540 static int MPBIOS_trigger(int idx)
542 int bus = mp_irqs[idx].mpc_srcbus;
546 * Determine IRQ trigger mode (edge or level sensitive):
548 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
550 case 0: /* conforms, ie. bus-type dependent */
551 if (test_bit(bus, mp_bus_not_pci))
552 trigger = default_ISA_trigger(idx);
554 trigger = default_PCI_trigger(idx);
561 case 2: /* reserved */
563 printk(KERN_WARNING "broken BIOS!!\n");
572 default: /* invalid */
574 printk(KERN_WARNING "broken BIOS!!\n");
582 static inline int irq_polarity(int idx)
584 return MPBIOS_polarity(idx);
587 static inline int irq_trigger(int idx)
589 return MPBIOS_trigger(idx);
592 static int pin_2_irq(int idx, int apic, int pin)
595 int bus = mp_irqs[idx].mpc_srcbus;
598 * Debugging check, we are in big trouble if this message pops up!
600 if (mp_irqs[idx].mpc_dstirq != pin)
601 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
603 if (test_bit(bus, mp_bus_not_pci)) {
604 irq = mp_irqs[idx].mpc_srcbusirq;
607 * PCI IRQs are mapped in order
611 irq += nr_ioapic_registers[i++];
614 BUG_ON(irq >= NR_IRQS);
618 static inline int IO_APIC_irq_trigger(int irq)
622 for (apic = 0; apic < nr_ioapics; apic++) {
623 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
624 idx = find_irq_entry(apic,pin,mp_INT);
625 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
626 return irq_trigger(idx);
630 * nonexistent IRQs are edge default
635 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
636 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
637 [0] = FIRST_EXTERNAL_VECTOR + 0,
638 [1] = FIRST_EXTERNAL_VECTOR + 1,
639 [2] = FIRST_EXTERNAL_VECTOR + 2,
640 [3] = FIRST_EXTERNAL_VECTOR + 3,
641 [4] = FIRST_EXTERNAL_VECTOR + 4,
642 [5] = FIRST_EXTERNAL_VECTOR + 5,
643 [6] = FIRST_EXTERNAL_VECTOR + 6,
644 [7] = FIRST_EXTERNAL_VECTOR + 7,
645 [8] = FIRST_EXTERNAL_VECTOR + 8,
646 [9] = FIRST_EXTERNAL_VECTOR + 9,
647 [10] = FIRST_EXTERNAL_VECTOR + 10,
648 [11] = FIRST_EXTERNAL_VECTOR + 11,
649 [12] = FIRST_EXTERNAL_VECTOR + 12,
650 [13] = FIRST_EXTERNAL_VECTOR + 13,
651 [14] = FIRST_EXTERNAL_VECTOR + 14,
652 [15] = FIRST_EXTERNAL_VECTOR + 15,
655 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
674 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
677 * NOTE! The local APIC isn't very good at handling
678 * multiple interrupts at the same interrupt level.
679 * As the interrupt level is determined by taking the
680 * vector number and shifting that right by 4, we
681 * want to spread these out a bit so that they don't
682 * all fall in the same interrupt level.
684 * Also, we've got to be careful not to trash gate
685 * 0x80, because int 0x80 is hm, kind of importantish. ;)
687 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
688 cpumask_t old_mask = CPU_MASK_NONE;
692 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
694 /* Only try and allocate irqs on cpus that are present */
695 cpus_and(mask, mask, cpu_online_map);
697 if (irq_vector[irq] > 0)
698 old_vector = irq_vector[irq];
699 if (old_vector > 0) {
700 cpus_and(*result, irq_domain[irq], mask);
701 if (!cpus_empty(*result))
703 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
706 for_each_cpu_mask(cpu, mask) {
707 cpumask_t domain, new_mask;
708 int new_cpu, old_cpu;
711 domain = vector_allocation_domain(cpu);
712 cpus_and(new_mask, domain, cpu_online_map);
714 vector = current_vector;
715 offset = current_offset;
718 if (vector >= FIRST_SYSTEM_VECTOR) {
719 /* If we run out of vectors on large boxen, must share them. */
720 offset = (offset + 1) % 8;
721 vector = FIRST_DEVICE_VECTOR + offset;
723 if (unlikely(current_vector == vector))
725 if (vector == IA32_SYSCALL_VECTOR)
727 for_each_cpu_mask(new_cpu, new_mask)
728 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
731 current_vector = vector;
732 current_offset = offset;
733 for_each_cpu_mask(old_cpu, old_mask)
734 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
735 for_each_cpu_mask(new_cpu, new_mask)
736 per_cpu(vector_irq, new_cpu)[vector] = irq;
737 irq_vector[irq] = vector;
738 irq_domain[irq] = domain;
739 cpus_and(*result, domain, mask);
745 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
750 spin_lock_irqsave(&vector_lock, flags);
751 vector = __assign_irq_vector(irq, mask, result);
752 spin_unlock_irqrestore(&vector_lock, flags);
756 static void __clear_irq_vector(int irq)
761 BUG_ON(!irq_vector[irq]);
763 vector = irq_vector[irq];
764 cpus_and(mask, irq_domain[irq], cpu_online_map);
765 for_each_cpu_mask(cpu, mask)
766 per_cpu(vector_irq, cpu)[vector] = -1;
769 irq_domain[irq] = CPU_MASK_NONE;
772 void __setup_vector_irq(int cpu)
774 /* Initialize vector_irq on a new cpu */
775 /* This function must be called with vector_lock held */
778 /* Mark the inuse vectors */
779 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
780 if (!cpu_isset(cpu, irq_domain[irq]))
782 vector = irq_vector[irq];
783 per_cpu(vector_irq, cpu)[vector] = irq;
785 /* Mark the free vectors */
786 for (vector = 0; vector < NR_VECTORS; ++vector) {
787 irq = per_cpu(vector_irq, cpu)[vector];
790 if (!cpu_isset(cpu, irq_domain[irq]))
791 per_cpu(vector_irq, cpu)[vector] = -1;
796 extern void (*interrupt[NR_IRQS])(void);
798 static struct irq_chip ioapic_chip;
800 #define IOAPIC_AUTO -1
801 #define IOAPIC_EDGE 0
802 #define IOAPIC_LEVEL 1
804 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
806 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
807 trigger == IOAPIC_LEVEL)
808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_fasteoi_irq, "fasteoi");
811 set_irq_chip_and_handler_name(irq, &ioapic_chip,
812 handle_edge_irq, "edge");
814 static void __init setup_IO_APIC_irq(int apic, int pin, int idx, int irq)
816 struct IO_APIC_route_entry entry;
822 * add it to the IO-APIC irq-routing table:
824 memset(&entry,0,sizeof(entry));
826 entry.delivery_mode = INT_DELIVERY_MODE;
827 entry.dest_mode = INT_DEST_MODE;
828 entry.mask = 0; /* enable IRQ */
829 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
831 entry.trigger = irq_trigger(idx);
832 entry.polarity = irq_polarity(idx);
834 if (irq_trigger(idx)) {
837 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
840 if (!apic && !IO_APIC_IRQ(irq))
843 if (IO_APIC_IRQ(irq)) {
845 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
849 entry.dest = cpu_mask_to_apicid(mask);
850 entry.vector = vector;
852 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
853 if (!apic && (irq < 16))
854 disable_8259A_irq(irq);
857 ioapic_write_entry(apic, pin, entry);
859 spin_lock_irqsave(&ioapic_lock, flags);
860 irq_desc[irq].affinity = TARGET_CPUS;
861 spin_unlock_irqrestore(&ioapic_lock, flags);
865 static void __init setup_IO_APIC_irqs(void)
867 int apic, pin, idx, irq, first_notcon = 1;
869 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
874 idx = find_irq_entry(apic,pin,mp_INT);
877 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
880 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
884 irq = pin_2_irq(idx, apic, pin);
885 add_pin_to_irq(irq, apic, pin);
887 setup_IO_APIC_irq(apic, pin, idx, irq);
893 apic_printk(APIC_VERBOSE," not connected.\n");
897 * Set up the 8259A-master output pin as broadcast to all
900 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
902 struct IO_APIC_route_entry entry;
905 memset(&entry,0,sizeof(entry));
907 disable_8259A_irq(0);
910 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
913 * We use logical delivery to get the timer IRQ
916 entry.dest_mode = INT_DEST_MODE;
917 entry.mask = 0; /* unmask IRQ now */
918 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
919 entry.delivery_mode = INT_DELIVERY_MODE;
922 entry.vector = vector;
925 * The timer IRQ doesn't have to know that behind the
926 * scene we have a 8259A-master in AEOI mode ...
928 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
931 * Add it to the IO-APIC irq-routing table:
933 spin_lock_irqsave(&ioapic_lock, flags);
934 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
935 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
936 spin_unlock_irqrestore(&ioapic_lock, flags);
941 void __init UNEXPECTED_IO_APIC(void)
945 void __apicdebuginit print_IO_APIC(void)
948 union IO_APIC_reg_00 reg_00;
949 union IO_APIC_reg_01 reg_01;
950 union IO_APIC_reg_02 reg_02;
953 if (apic_verbosity == APIC_QUIET)
956 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
957 for (i = 0; i < nr_ioapics; i++)
958 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
959 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
962 * We are a bit conservative about what we expect. We have to
963 * know about every hardware change ASAP.
965 printk(KERN_INFO "testing the IO APIC.......................\n");
967 for (apic = 0; apic < nr_ioapics; apic++) {
969 spin_lock_irqsave(&ioapic_lock, flags);
970 reg_00.raw = io_apic_read(apic, 0);
971 reg_01.raw = io_apic_read(apic, 1);
972 if (reg_01.bits.version >= 0x10)
973 reg_02.raw = io_apic_read(apic, 2);
974 spin_unlock_irqrestore(&ioapic_lock, flags);
977 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
978 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
979 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
980 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
981 UNEXPECTED_IO_APIC();
983 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
984 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
985 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
986 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
987 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
988 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
989 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
990 (reg_01.bits.entries != 0x2E) &&
991 (reg_01.bits.entries != 0x3F) &&
992 (reg_01.bits.entries != 0x03)
994 UNEXPECTED_IO_APIC();
996 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
997 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
998 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
999 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1000 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1001 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1002 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1003 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1005 UNEXPECTED_IO_APIC();
1006 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1007 UNEXPECTED_IO_APIC();
1009 if (reg_01.bits.version >= 0x10) {
1010 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1011 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1012 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1013 UNEXPECTED_IO_APIC();
1016 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1018 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1019 " Stat Dmod Deli Vect: \n");
1021 for (i = 0; i <= reg_01.bits.entries; i++) {
1022 struct IO_APIC_route_entry entry;
1024 entry = ioapic_read_entry(apic, i);
1026 printk(KERN_DEBUG " %02x %03X ",
1031 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1036 entry.delivery_status,
1038 entry.delivery_mode,
1043 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1044 for (i = 0; i < NR_IRQS; i++) {
1045 struct irq_pin_list *entry = irq_2_pin + i;
1048 printk(KERN_DEBUG "IRQ%d ", i);
1050 printk("-> %d:%d", entry->apic, entry->pin);
1053 entry = irq_2_pin + entry->next;
1058 printk(KERN_INFO ".................................... done.\n");
1065 static __apicdebuginit void print_APIC_bitfield (int base)
1070 if (apic_verbosity == APIC_QUIET)
1073 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1074 for (i = 0; i < 8; i++) {
1075 v = apic_read(base + i*0x10);
1076 for (j = 0; j < 32; j++) {
1086 void __apicdebuginit print_local_APIC(void * dummy)
1088 unsigned int v, ver, maxlvt;
1090 if (apic_verbosity == APIC_QUIET)
1093 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1094 smp_processor_id(), hard_smp_processor_id());
1095 v = apic_read(APIC_ID);
1096 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1097 v = apic_read(APIC_LVR);
1098 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1099 ver = GET_APIC_VERSION(v);
1100 maxlvt = get_maxlvt();
1102 v = apic_read(APIC_TASKPRI);
1103 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1105 v = apic_read(APIC_ARBPRI);
1106 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1107 v & APIC_ARBPRI_MASK);
1108 v = apic_read(APIC_PROCPRI);
1109 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1111 v = apic_read(APIC_EOI);
1112 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1113 v = apic_read(APIC_RRR);
1114 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1115 v = apic_read(APIC_LDR);
1116 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1117 v = apic_read(APIC_DFR);
1118 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1119 v = apic_read(APIC_SPIV);
1120 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1122 printk(KERN_DEBUG "... APIC ISR field:\n");
1123 print_APIC_bitfield(APIC_ISR);
1124 printk(KERN_DEBUG "... APIC TMR field:\n");
1125 print_APIC_bitfield(APIC_TMR);
1126 printk(KERN_DEBUG "... APIC IRR field:\n");
1127 print_APIC_bitfield(APIC_IRR);
1129 v = apic_read(APIC_ESR);
1130 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1132 v = apic_read(APIC_ICR);
1133 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1134 v = apic_read(APIC_ICR2);
1135 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1137 v = apic_read(APIC_LVTT);
1138 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1140 if (maxlvt > 3) { /* PC is LVT#4. */
1141 v = apic_read(APIC_LVTPC);
1142 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1144 v = apic_read(APIC_LVT0);
1145 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1146 v = apic_read(APIC_LVT1);
1147 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1149 if (maxlvt > 2) { /* ERR is LVT#3. */
1150 v = apic_read(APIC_LVTERR);
1151 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1154 v = apic_read(APIC_TMICT);
1155 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1156 v = apic_read(APIC_TMCCT);
1157 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1158 v = apic_read(APIC_TDCR);
1159 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1163 void print_all_local_APICs (void)
1165 on_each_cpu(print_local_APIC, NULL, 1, 1);
1168 void __apicdebuginit print_PIC(void)
1171 unsigned long flags;
1173 if (apic_verbosity == APIC_QUIET)
1176 printk(KERN_DEBUG "\nprinting PIC contents\n");
1178 spin_lock_irqsave(&i8259A_lock, flags);
1180 v = inb(0xa1) << 8 | inb(0x21);
1181 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1183 v = inb(0xa0) << 8 | inb(0x20);
1184 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1188 v = inb(0xa0) << 8 | inb(0x20);
1192 spin_unlock_irqrestore(&i8259A_lock, flags);
1194 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1196 v = inb(0x4d1) << 8 | inb(0x4d0);
1197 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1202 static void __init enable_IO_APIC(void)
1204 union IO_APIC_reg_01 reg_01;
1205 int i8259_apic, i8259_pin;
1207 unsigned long flags;
1209 for (i = 0; i < PIN_MAP_SIZE; i++) {
1210 irq_2_pin[i].pin = -1;
1211 irq_2_pin[i].next = 0;
1215 * The number of IO-APIC IRQ registers (== #pins):
1217 for (apic = 0; apic < nr_ioapics; apic++) {
1218 spin_lock_irqsave(&ioapic_lock, flags);
1219 reg_01.raw = io_apic_read(apic, 1);
1220 spin_unlock_irqrestore(&ioapic_lock, flags);
1221 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1223 for(apic = 0; apic < nr_ioapics; apic++) {
1225 /* See if any of the pins is in ExtINT mode */
1226 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1227 struct IO_APIC_route_entry entry;
1228 entry = ioapic_read_entry(apic, pin);
1230 /* If the interrupt line is enabled and in ExtInt mode
1231 * I have found the pin where the i8259 is connected.
1233 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1234 ioapic_i8259.apic = apic;
1235 ioapic_i8259.pin = pin;
1241 /* Look to see what if the MP table has reported the ExtINT */
1242 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1243 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1244 /* Trust the MP table if nothing is setup in the hardware */
1245 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1246 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1247 ioapic_i8259.pin = i8259_pin;
1248 ioapic_i8259.apic = i8259_apic;
1250 /* Complain if the MP table and the hardware disagree */
1251 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1252 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1254 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1258 * Do not trust the IO-APIC being empty at bootup
1264 * Not an __init, needed by the reboot code
1266 void disable_IO_APIC(void)
1269 * Clear the IO-APIC before rebooting:
1274 * If the i8259 is routed through an IOAPIC
1275 * Put that IOAPIC in virtual wire mode
1276 * so legacy interrupts can be delivered.
1278 if (ioapic_i8259.pin != -1) {
1279 struct IO_APIC_route_entry entry;
1281 memset(&entry, 0, sizeof(entry));
1282 entry.mask = 0; /* Enabled */
1283 entry.trigger = 0; /* Edge */
1285 entry.polarity = 0; /* High */
1286 entry.delivery_status = 0;
1287 entry.dest_mode = 0; /* Physical */
1288 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1290 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1293 * Add it to the IO-APIC irq-routing table:
1295 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1298 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1302 * There is a nasty bug in some older SMP boards, their mptable lies
1303 * about the timer IRQ. We do the following to work around the situation:
1305 * - timer IRQ defaults to IO-APIC IRQ
1306 * - if this function detects that timer IRQs are defunct, then we fall
1307 * back to ISA timer IRQs
1309 static int __init timer_irq_works(void)
1311 unsigned long t1 = jiffies;
1314 /* Let ten ticks pass... */
1315 mdelay((10 * 1000) / HZ);
1318 * Expect a few ticks at least, to be sure some possible
1319 * glue logic does not lock up after one or two first
1320 * ticks in a non-ExtINT mode. Also the local APIC
1321 * might have cached one ExtINT interrupt. Finally, at
1322 * least one tick may be lost due to delays.
1326 if (jiffies - t1 > 4)
1332 * In the SMP+IOAPIC case it might happen that there are an unspecified
1333 * number of pending IRQ events unhandled. These cases are very rare,
1334 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1335 * better to do it this way as thus we do not have to be aware of
1336 * 'pending' interrupts in the IRQ path, except at this point.
1339 * Edge triggered needs to resend any interrupt
1340 * that was delayed but this is now handled in the device
1345 * Starting up a edge-triggered IO-APIC interrupt is
1346 * nasty - we need to make sure that we get the edge.
1347 * If it is already asserted for some reason, we need
1348 * return 1 to indicate that is was pending.
1350 * This is not complete - we should be able to fake
1351 * an edge even if it isn't on the 8259A...
1354 static unsigned int startup_ioapic_irq(unsigned int irq)
1356 int was_pending = 0;
1357 unsigned long flags;
1359 spin_lock_irqsave(&ioapic_lock, flags);
1361 disable_8259A_irq(irq);
1362 if (i8259A_irq_pending(irq))
1365 __unmask_IO_APIC_irq(irq);
1366 spin_unlock_irqrestore(&ioapic_lock, flags);
1371 static int ioapic_retrigger_irq(unsigned int irq)
1375 unsigned long flags;
1377 spin_lock_irqsave(&vector_lock, flags);
1378 vector = irq_vector[irq];
1380 cpu_set(first_cpu(irq_domain[irq]), mask);
1382 send_IPI_mask(mask, vector);
1383 spin_unlock_irqrestore(&vector_lock, flags);
1389 * Level and edge triggered IO-APIC interrupts need different handling,
1390 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1391 * handled with the level-triggered descriptor, but that one has slightly
1392 * more overhead. Level-triggered interrupts cannot be handled with the
1393 * edge-triggered handler, without risking IRQ storms and other ugly
1397 static void ack_apic_edge(unsigned int irq)
1399 move_native_irq(irq);
1403 static void ack_apic_level(unsigned int irq)
1405 int do_unmask_irq = 0;
1407 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1408 /* If we are moving the irq we need to mask it */
1409 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1411 mask_IO_APIC_irq(irq);
1416 * We must acknowledge the irq before we move it or the acknowledge will
1417 * not propogate properly.
1421 /* Now we can move and renable the irq */
1422 move_masked_irq(irq);
1423 if (unlikely(do_unmask_irq))
1424 unmask_IO_APIC_irq(irq);
1427 static struct irq_chip ioapic_chip __read_mostly = {
1429 .startup = startup_ioapic_irq,
1430 .mask = mask_IO_APIC_irq,
1431 .unmask = unmask_IO_APIC_irq,
1432 .ack = ack_apic_edge,
1433 .eoi = ack_apic_level,
1435 .set_affinity = set_ioapic_affinity_irq,
1437 .retrigger = ioapic_retrigger_irq,
1440 static inline void init_IO_APIC_traps(void)
1445 * NOTE! The local APIC isn't very good at handling
1446 * multiple interrupts at the same interrupt level.
1447 * As the interrupt level is determined by taking the
1448 * vector number and shifting that right by 4, we
1449 * want to spread these out a bit so that they don't
1450 * all fall in the same interrupt level.
1452 * Also, we've got to be careful not to trash gate
1453 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1455 for (irq = 0; irq < NR_IRQS ; irq++) {
1457 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1459 * Hmm.. We don't have an entry for this,
1460 * so default to an old-fashioned 8259
1461 * interrupt if we can..
1464 make_8259A_irq(irq);
1466 /* Strange. Oh, well.. */
1467 irq_desc[irq].chip = &no_irq_chip;
1472 static void enable_lapic_irq (unsigned int irq)
1476 v = apic_read(APIC_LVT0);
1477 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1480 static void disable_lapic_irq (unsigned int irq)
1484 v = apic_read(APIC_LVT0);
1485 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1488 static void ack_lapic_irq (unsigned int irq)
1493 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1495 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1496 .typename = "local-APIC-edge",
1497 .startup = NULL, /* startup_irq() not used for IRQ0 */
1498 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1499 .enable = enable_lapic_irq,
1500 .disable = disable_lapic_irq,
1501 .ack = ack_lapic_irq,
1502 .end = end_lapic_irq,
1505 static void setup_nmi (void)
1508 * Dirty trick to enable the NMI watchdog ...
1509 * We put the 8259A master into AEOI mode and
1510 * unmask on all local APICs LVT0 as NMI.
1512 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1513 * is from Maciej W. Rozycki - so we do not have to EOI from
1514 * the NMI handler or the timer interrupt.
1516 printk(KERN_INFO "activating NMI Watchdog ...");
1518 enable_NMI_through_LVT0(NULL);
1524 * This looks a bit hackish but it's about the only one way of sending
1525 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1526 * not support the ExtINT mode, unfortunately. We need to send these
1527 * cycles as some i82489DX-based boards have glue logic that keeps the
1528 * 8259A interrupt line asserted until INTA. --macro
1530 static inline void unlock_ExtINT_logic(void)
1533 struct IO_APIC_route_entry entry0, entry1;
1534 unsigned char save_control, save_freq_select;
1535 unsigned long flags;
1537 pin = find_isa_irq_pin(8, mp_INT);
1538 apic = find_isa_irq_apic(8, mp_INT);
1542 spin_lock_irqsave(&ioapic_lock, flags);
1543 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1544 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1545 spin_unlock_irqrestore(&ioapic_lock, flags);
1546 clear_IO_APIC_pin(apic, pin);
1548 memset(&entry1, 0, sizeof(entry1));
1550 entry1.dest_mode = 0; /* physical delivery */
1551 entry1.mask = 0; /* unmask IRQ now */
1552 entry1.dest = hard_smp_processor_id();
1553 entry1.delivery_mode = dest_ExtINT;
1554 entry1.polarity = entry0.polarity;
1558 spin_lock_irqsave(&ioapic_lock, flags);
1559 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1560 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1561 spin_unlock_irqrestore(&ioapic_lock, flags);
1563 save_control = CMOS_READ(RTC_CONTROL);
1564 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1565 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1567 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1572 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1576 CMOS_WRITE(save_control, RTC_CONTROL);
1577 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1578 clear_IO_APIC_pin(apic, pin);
1580 spin_lock_irqsave(&ioapic_lock, flags);
1581 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1582 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1583 spin_unlock_irqrestore(&ioapic_lock, flags);
1587 * This code may look a bit paranoid, but it's supposed to cooperate with
1588 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1589 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1590 * fanatically on his truly buggy board.
1592 * FIXME: really need to revamp this for modern platforms only.
1594 static inline void check_timer(void)
1596 int apic1, pin1, apic2, pin2;
1601 * get/set the timer IRQ vector:
1603 disable_8259A_irq(0);
1604 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1607 * Subtle, code in do_timer_interrupt() expects an AEOI
1608 * mode for the 8259A whenever interrupts are routed
1609 * through I/O APICs. Also IRQ0 has to be enabled in
1610 * the 8259A which implies the virtual wire has to be
1611 * disabled in the local APIC.
1613 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1615 if (timer_over_8254 > 0)
1616 enable_8259A_irq(0);
1618 pin1 = find_isa_irq_pin(0, mp_INT);
1619 apic1 = find_isa_irq_apic(0, mp_INT);
1620 pin2 = ioapic_i8259.pin;
1621 apic2 = ioapic_i8259.apic;
1623 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1624 vector, apic1, pin1, apic2, pin2);
1628 * Ok, does IRQ0 through the IOAPIC work?
1630 unmask_IO_APIC_irq(0);
1631 if (!no_timer_check && timer_irq_works()) {
1632 nmi_watchdog_default();
1633 if (nmi_watchdog == NMI_IO_APIC) {
1634 disable_8259A_irq(0);
1636 enable_8259A_irq(0);
1638 if (disable_timer_pin_1 > 0)
1639 clear_IO_APIC_pin(0, pin1);
1642 clear_IO_APIC_pin(apic1, pin1);
1643 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1644 "connected to IO-APIC\n");
1647 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1648 "through the 8259A ... ");
1650 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1653 * legacy devices should be connected to IO APIC #0
1655 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1656 if (timer_irq_works()) {
1657 apic_printk(APIC_VERBOSE," works.\n");
1658 nmi_watchdog_default();
1659 if (nmi_watchdog == NMI_IO_APIC) {
1665 * Cleanup, just in case ...
1667 clear_IO_APIC_pin(apic2, pin2);
1669 apic_printk(APIC_VERBOSE," failed.\n");
1671 if (nmi_watchdog == NMI_IO_APIC) {
1672 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1676 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1678 disable_8259A_irq(0);
1679 irq_desc[0].chip = &lapic_irq_type;
1680 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1681 enable_8259A_irq(0);
1683 if (timer_irq_works()) {
1684 apic_printk(APIC_VERBOSE," works.\n");
1687 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1688 apic_printk(APIC_VERBOSE," failed.\n");
1690 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1694 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1696 unlock_ExtINT_logic();
1698 if (timer_irq_works()) {
1699 apic_printk(APIC_VERBOSE," works.\n");
1702 apic_printk(APIC_VERBOSE," failed :(.\n");
1703 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1706 static int __init notimercheck(char *s)
1711 __setup("no_timer_check", notimercheck);
1715 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1716 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1717 * Linux doesn't really care, as it's not actually used
1718 * for any interrupt handling anyway.
1720 #define PIC_IRQS (1<<2)
1722 void __init setup_IO_APIC(void)
1727 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1729 io_apic_irqs = ~PIC_IRQS;
1731 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1734 setup_IO_APIC_irqs();
1735 init_IO_APIC_traps();
1741 struct sysfs_ioapic_data {
1742 struct sys_device dev;
1743 struct IO_APIC_route_entry entry[0];
1745 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1747 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1749 struct IO_APIC_route_entry *entry;
1750 struct sysfs_ioapic_data *data;
1753 data = container_of(dev, struct sysfs_ioapic_data, dev);
1754 entry = data->entry;
1755 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1756 *entry = ioapic_read_entry(dev->id, i);
1761 static int ioapic_resume(struct sys_device *dev)
1763 struct IO_APIC_route_entry *entry;
1764 struct sysfs_ioapic_data *data;
1765 unsigned long flags;
1766 union IO_APIC_reg_00 reg_00;
1769 data = container_of(dev, struct sysfs_ioapic_data, dev);
1770 entry = data->entry;
1772 spin_lock_irqsave(&ioapic_lock, flags);
1773 reg_00.raw = io_apic_read(dev->id, 0);
1774 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1775 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1776 io_apic_write(dev->id, 0, reg_00.raw);
1778 spin_unlock_irqrestore(&ioapic_lock, flags);
1779 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1780 ioapic_write_entry(dev->id, i, entry[i]);
1785 static struct sysdev_class ioapic_sysdev_class = {
1786 set_kset_name("ioapic"),
1787 .suspend = ioapic_suspend,
1788 .resume = ioapic_resume,
1791 static int __init ioapic_init_sysfs(void)
1793 struct sys_device * dev;
1794 int i, size, error = 0;
1796 error = sysdev_class_register(&ioapic_sysdev_class);
1800 for (i = 0; i < nr_ioapics; i++ ) {
1801 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1802 * sizeof(struct IO_APIC_route_entry);
1803 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1804 if (!mp_ioapic_data[i]) {
1805 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1808 memset(mp_ioapic_data[i], 0, size);
1809 dev = &mp_ioapic_data[i]->dev;
1811 dev->cls = &ioapic_sysdev_class;
1812 error = sysdev_register(dev);
1814 kfree(mp_ioapic_data[i]);
1815 mp_ioapic_data[i] = NULL;
1816 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1824 device_initcall(ioapic_init_sysfs);
1827 * Dynamic irq allocate and deallocation
1829 int create_irq(void)
1831 /* Allocate an unused irq */
1835 unsigned long flags;
1839 spin_lock_irqsave(&vector_lock, flags);
1840 for (new = (NR_IRQS - 1); new >= 0; new--) {
1841 if (platform_legacy_irq(new))
1843 if (irq_vector[new] != 0)
1845 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1846 if (likely(vector > 0))
1850 spin_unlock_irqrestore(&vector_lock, flags);
1853 dynamic_irq_init(irq);
1858 void destroy_irq(unsigned int irq)
1860 unsigned long flags;
1862 dynamic_irq_cleanup(irq);
1864 spin_lock_irqsave(&vector_lock, flags);
1865 __clear_irq_vector(irq);
1866 spin_unlock_irqrestore(&vector_lock, flags);
1870 * MSI mesage composition
1872 #ifdef CONFIG_PCI_MSI
1873 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1879 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1881 dest = cpu_mask_to_apicid(tmp);
1883 msg->address_hi = MSI_ADDR_BASE_HI;
1886 ((INT_DEST_MODE == 0) ?
1887 MSI_ADDR_DEST_MODE_PHYSICAL:
1888 MSI_ADDR_DEST_MODE_LOGICAL) |
1889 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1890 MSI_ADDR_REDIRECTION_CPU:
1891 MSI_ADDR_REDIRECTION_LOWPRI) |
1892 MSI_ADDR_DEST_ID(dest);
1895 MSI_DATA_TRIGGER_EDGE |
1896 MSI_DATA_LEVEL_ASSERT |
1897 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1898 MSI_DATA_DELIVERY_FIXED:
1899 MSI_DATA_DELIVERY_LOWPRI) |
1900 MSI_DATA_VECTOR(vector);
1906 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1913 cpus_and(tmp, mask, cpu_online_map);
1914 if (cpus_empty(tmp))
1917 cpus_and(mask, tmp, CPU_MASK_ALL);
1919 vector = assign_irq_vector(irq, mask, &tmp);
1923 dest = cpu_mask_to_apicid(tmp);
1925 read_msi_msg(irq, &msg);
1927 msg.data &= ~MSI_DATA_VECTOR_MASK;
1928 msg.data |= MSI_DATA_VECTOR(vector);
1929 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1930 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1932 write_msi_msg(irq, &msg);
1933 irq_desc[irq].affinity = mask;
1935 #endif /* CONFIG_SMP */
1938 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1939 * which implement the MSI or MSI-X Capability Structure.
1941 static struct irq_chip msi_chip = {
1943 .unmask = unmask_msi_irq,
1944 .mask = mask_msi_irq,
1945 .ack = ack_apic_edge,
1947 .set_affinity = set_msi_irq_affinity,
1949 .retrigger = ioapic_retrigger_irq,
1952 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1960 set_irq_msi(irq, desc);
1961 ret = msi_compose_msg(dev, irq, &msg);
1967 write_msi_msg(irq, &msg);
1969 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1974 void arch_teardown_msi_irq(unsigned int irq)
1979 #endif /* CONFIG_PCI_MSI */
1982 * Hypertransport interrupt support
1984 #ifdef CONFIG_HT_IRQ
1988 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1990 struct ht_irq_msg msg;
1991 fetch_ht_irq_msg(irq, &msg);
1993 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1994 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1996 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1997 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1999 write_ht_irq_msg(irq, &msg);
2002 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2008 cpus_and(tmp, mask, cpu_online_map);
2009 if (cpus_empty(tmp))
2012 cpus_and(mask, tmp, CPU_MASK_ALL);
2014 vector = assign_irq_vector(irq, mask, &tmp);
2018 dest = cpu_mask_to_apicid(tmp);
2020 target_ht_irq(irq, dest, vector);
2021 irq_desc[irq].affinity = mask;
2025 static struct irq_chip ht_irq_chip = {
2027 .mask = mask_ht_irq,
2028 .unmask = unmask_ht_irq,
2029 .ack = ack_apic_edge,
2031 .set_affinity = set_ht_irq_affinity,
2033 .retrigger = ioapic_retrigger_irq,
2036 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2041 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2043 struct ht_irq_msg msg;
2046 dest = cpu_mask_to_apicid(tmp);
2048 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2052 HT_IRQ_LOW_DEST_ID(dest) |
2053 HT_IRQ_LOW_VECTOR(vector) |
2054 ((INT_DEST_MODE == 0) ?
2055 HT_IRQ_LOW_DM_PHYSICAL :
2056 HT_IRQ_LOW_DM_LOGICAL) |
2057 HT_IRQ_LOW_RQEOI_EDGE |
2058 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2059 HT_IRQ_LOW_MT_FIXED :
2060 HT_IRQ_LOW_MT_ARBITRATED) |
2061 HT_IRQ_LOW_IRQ_MASKED;
2063 write_ht_irq_msg(irq, &msg);
2065 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2066 handle_edge_irq, "edge");
2070 #endif /* CONFIG_HT_IRQ */
2072 /* --------------------------------------------------------------------------
2073 ACPI-based IOAPIC Configuration
2074 -------------------------------------------------------------------------- */
2078 #define IO_APIC_MAX_ID 0xFE
2080 int __init io_apic_get_redir_entries (int ioapic)
2082 union IO_APIC_reg_01 reg_01;
2083 unsigned long flags;
2085 spin_lock_irqsave(&ioapic_lock, flags);
2086 reg_01.raw = io_apic_read(ioapic, 1);
2087 spin_unlock_irqrestore(&ioapic_lock, flags);
2089 return reg_01.bits.entries;
2093 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2095 struct IO_APIC_route_entry entry;
2096 unsigned long flags;
2100 if (!IO_APIC_IRQ(irq)) {
2101 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2107 * IRQs < 16 are already in the irq_2_pin[] map
2110 add_pin_to_irq(irq, ioapic, pin);
2113 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2118 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2119 * Note that we mask (disable) IRQs now -- these get enabled when the
2120 * corresponding device driver registers for this IRQ.
2123 memset(&entry,0,sizeof(entry));
2125 entry.delivery_mode = INT_DELIVERY_MODE;
2126 entry.dest_mode = INT_DEST_MODE;
2127 entry.dest = cpu_mask_to_apicid(mask);
2128 entry.trigger = triggering;
2129 entry.polarity = polarity;
2130 entry.mask = 1; /* Disabled (masked) */
2131 entry.vector = vector & 0xff;
2133 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2134 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2135 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2136 triggering, polarity);
2138 ioapic_register_intr(irq, entry.vector, triggering);
2140 if (!ioapic && (irq < 16))
2141 disable_8259A_irq(irq);
2143 ioapic_write_entry(ioapic, pin, entry);
2145 spin_lock_irqsave(&ioapic_lock, flags);
2146 irq_desc[irq].affinity = TARGET_CPUS;
2147 spin_unlock_irqrestore(&ioapic_lock, flags);
2152 #endif /* CONFIG_ACPI */
2156 * This function currently is only a helper for the i386 smp boot process where
2157 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2158 * so mask in all cases should simply be TARGET_CPUS
2161 void __init setup_ioapic_dest(void)
2163 int pin, ioapic, irq, irq_entry;
2165 if (skip_ioapic_setup == 1)
2168 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2169 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2170 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2171 if (irq_entry == -1)
2173 irq = pin_2_irq(irq_entry, ioapic, pin);
2175 /* setup_IO_APIC_irqs could fail to get vector for some device
2176 * when you have too many devices, because at that time only boot
2179 if(!irq_vector[irq])
2180 setup_IO_APIC_irq(ioapic, pin, irq_entry, irq);
2182 set_ioapic_affinity_irq(irq, TARGET_CPUS);