2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
11 #include <linux/linkage.h>
12 #include <linux/threads.h>
13 #include <linux/init.h>
15 #include <asm/segment.h>
18 #include <asm/cache.h>
20 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
21 * because we need identity-mapped pages on setup so define __START_KERNEL to
22 * 0x100000 for this stage
27 .section .bootstrap.text
30 /* %bx: 1 if coming from smp trampoline on secondary cpu */
34 * At this point the CPU runs in 32bit protected mode (CS.D = 1) with
35 * paging disabled and the point of this file is to switch to 64bit
36 * long mode with a kernel mapping for kerneland to jump into the
37 * kernel virtual addresses.
38 * There is no stack until we set one up.
41 /* Initialize the %ds segment register */
42 movl $__KERNEL_DS,%eax
45 /* Load new GDT with the 64bit segments using 32bit descriptor */
46 lgdt pGDT32 - __START_KERNEL_map
48 /* If the CPU doesn't support CPUID this will double fault.
49 * Unfortunately it is hard to check for CPUID without a stack.
52 /* Check if extended functions are implemented */
53 movl $0x80000000, %eax
55 cmpl $0x80000000, %eax
57 /* Check if long mode is implemented */
64 * Prepare for entering 64bits mode
72 /* Setup early boot stage 4 level pagetables */
73 movl $(boot_level4_pgt - __START_KERNEL_map), %eax
76 /* Setup EFER (Extended Feature Enable Register) */
80 /* Enable Long Mode */
83 /* Make changes effective */
87 btsl $31, %eax /* Enable paging and in turn activate Long Mode */
88 btsl $0, %eax /* Enable protected mode */
89 /* Make changes effective */
92 * At this point we're in long mode but in 32bit compatibility mode
93 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
94 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
95 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
97 ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map)
103 /* We come here either from startup_32
104 * or directly from a 64bit bootloader.
105 * Since we may have come directly from a bootloader we
106 * reload the page tables here.
109 /* Enable PAE mode and PGE */
115 /* Setup early boot stage 4 level pagetables. */
116 movq $(boot_level4_pgt - __START_KERNEL_map), %rax
119 /* Check if nx is implemented */
120 movl $0x80000001, %eax
124 /* Setup EFER (Extended Feature Enable Register) */
128 /* Enable System Call */
129 btsl $_EFER_SCE, %eax
131 /* No Execute supported? */
136 /* Make changes effective */
140 #define CR0_PM 1 /* protected mode */
141 #define CR0_MP (1<<1)
142 #define CR0_ET (1<<4)
143 #define CR0_NE (1<<5)
144 #define CR0_WP (1<<16)
145 #define CR0_AM (1<<18)
146 #define CR0_PAGING (1<<31)
147 movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
148 /* Make changes effective */
151 /* Setup a boot time stack */
152 movq init_rsp(%rip),%rsp
154 /* zero EFLAGS after setting rsp */
159 * We must switch to a new descriptor in kernel space for the GDT
160 * because soon the kernel won't have access anymore to the userspace
161 * addresses where we're currently running on. We have to do that here
162 * because in 32bit we couldn't load a 64bit linear address.
167 * Setup up a dummy PDA. this is just for some early bootup code
168 * that does in_interrupt()
170 movl $MSR_GS_BASE,%ecx
171 movq $empty_zero_page,%rax
176 /* set up data segments. actually 0 would do too */
177 movl $__KERNEL_DS,%eax
182 /* esi is pointer to real mode structure with interesting info.
186 /* Finally jump to run C code and to be on real kernel address
187 * Since we are running on identity-mapped space we have to jump
188 * to the full 64bit address, this is only possible as indirect
189 * jump. In addition we need to ensure %cs is set so we make this
192 movq initial_code(%rip),%rax
193 pushq $0 # fake return address to stop unwinder
194 pushq $__KERNEL_CS # set correct cs
195 pushq %rax # target address in negative space
198 /* SMP bootup changes these two */
202 .quad x86_64_start_kernel
205 .quad init_thread_union+THREAD_SIZE-8
207 ENTRY(early_idt_handler)
208 cmpl $2,early_recursion_flag(%rip)
210 incl early_recursion_flag(%rip)
212 movq 8(%rsp),%rsi # get rip
215 leaq early_idt_msg(%rip),%rdi
217 cmpl $2,early_recursion_flag(%rip)
220 #ifdef CONFIG_KALLSYMS
221 leaq early_idt_ripmsg(%rip),%rdi
222 movq 8(%rsp),%rsi # get rip again
227 early_recursion_flag:
231 .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
237 /* This isn't an x86-64 CPU so hang */
244 .word gdt_end-cpu_gdt_table-1
245 .long cpu_gdt_table-__START_KERNEL_map
249 .long startup_64-__START_KERNEL_map
256 #define NEXT_PAGE(name) \
258 .org $page * 0x1000; \
259 phys_/**/name = $page * 0x1000 + __PHYSICAL_START; \
262 NEXT_PAGE(init_level4_pgt)
263 /* This gets initialized in x86_64_start_kernel */
266 NEXT_PAGE(level3_ident_pgt)
267 .quad phys_level2_ident_pgt | 0x007
270 NEXT_PAGE(level3_kernel_pgt)
272 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
273 .quad phys_level2_kernel_pgt | 0x007
276 NEXT_PAGE(level2_ident_pgt)
277 /* 40MB for bootup. */
280 .quad i << 21 | 0x083
283 /* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
284 .globl temp_boot_pmds
288 NEXT_PAGE(level2_kernel_pgt)
289 /* 40MB kernel mapping. The kernel code cannot be bigger than that.
290 When you change this change KERNEL_TEXT_SIZE in page.h too. */
291 /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
294 .quad i << 21 | 0x183
297 /* Module mapping starts here */
300 NEXT_PAGE(level3_physmem_pgt)
301 .quad phys_level2_kernel_pgt | 0x007 /* so that __va works even before pagetable_init */
308 #ifdef CONFIG_ACPI_SLEEP
310 ENTRY(wakeup_level4_pgt)
311 .quad phys_level3_ident_pgt | 0x007
313 .quad phys_level3_physmem_pgt | 0x007
315 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
316 .quad phys_level3_kernel_pgt | 0x007
319 #ifndef CONFIG_HOTPLUG_CPU
323 * This default setting generates an ident mapping at address 0x100000
324 * and a mapping for the kernel that precisely maps virtual address
325 * 0xffffffff80000000 to physical address 0x000000. (always using
326 * 2Mbyte large pages provided by PAE mode)
329 ENTRY(boot_level4_pgt)
330 .quad phys_level3_ident_pgt | 0x007
332 .quad phys_level3_physmem_pgt | 0x007
334 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
335 .quad phys_level3_kernel_pgt | 0x007
342 .word gdt_end-cpu_gdt_table-1
352 /* We need valid kernel segments for data and code in long mode too
353 * IRET will check the segment types kkeil 2000/10/28
354 * Also sysret mandates a special GDT layout
357 .section .data.page_aligned, "aw"
360 /* The TLS descriptors are currently at a different place compared to i386.
361 Hopefully nobody expects them at a fixed place (Wine?) */
364 .quad 0x0000000000000000 /* NULL descriptor */
365 .quad 0x0 /* unused */
366 .quad 0x00af9a000000ffff /* __KERNEL_CS */
367 .quad 0x00cf92000000ffff /* __KERNEL_DS */
368 .quad 0x00cffa000000ffff /* __USER32_CS */
369 .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
370 .quad 0x00affa000000ffff /* __USER_CS */
371 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */
374 .quad 0,0,0 /* three TLS descriptors */
375 .quad 0x0000f40000000000 /* node/CPU stored in limit */
377 /* asm/segment.h:GDT_ENTRIES must match this */
378 /* This should be a multiple of the cache line size */
379 /* GDTs of other CPUs are now dynamically allocated */
381 /* zero the remaining page */
382 .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
384 .section .bss, "aw", @nobits
385 .align L1_CACHE_BYTES
389 .section .bss.page_aligned, "aw", @nobits
391 ENTRY(empty_zero_page)