2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
13 #include <linux/linkage.h>
14 #include <linux/threads.h>
15 #include <linux/init.h>
17 #include <asm/segment.h>
20 #include <asm/cache.h>
22 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
23 * because we need identity-mapped pages on setup so define __START_KERNEL to
24 * 0x100000 for this stage
29 .section .bootstrap.text
32 /* %bx: 1 if coming from smp trampoline on secondary cpu */
36 * At this point the CPU runs in 32bit protected mode (CS.D = 1) with
37 * paging disabled and the point of this file is to switch to 64bit
38 * long mode with a kernel mapping for kerneland to jump into the
39 * kernel virtual addresses.
40 * There is no stack until we set one up.
43 /* Initialize the %ds segment register */
44 movl $__KERNEL_DS,%eax
47 /* Load new GDT with the 64bit segments using 32bit descriptor */
48 lgdt pGDT32 - __START_KERNEL_map
50 /* If the CPU doesn't support CPUID this will double fault.
51 * Unfortunately it is hard to check for CPUID without a stack.
54 /* Check if extended functions are implemented */
55 movl $0x80000000, %eax
57 cmpl $0x80000000, %eax
59 /* Check if long mode is implemented */
66 * Prepare for entering 64bits mode
74 /* Setup early boot stage 4 level pagetables */
75 movl $(boot_level4_pgt - __START_KERNEL_map), %eax
78 /* Setup EFER (Extended Feature Enable Register) */
82 /* Enable Long Mode */
85 /* Make changes effective */
89 btsl $31, %eax /* Enable paging and in turn activate Long Mode */
90 btsl $0, %eax /* Enable protected mode */
91 /* Make changes effective */
94 * At this point we're in long mode but in 32bit compatibility mode
95 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
96 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
97 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
99 ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map)
105 /* We come here either from startup_32
106 * or directly from a 64bit bootloader.
107 * Since we may have come directly from a bootloader we
108 * reload the page tables here.
111 /* Enable PAE mode and PGE */
117 /* Setup early boot stage 4 level pagetables. */
118 movq $(boot_level4_pgt - __START_KERNEL_map), %rax
121 /* Check if nx is implemented */
122 movl $0x80000001, %eax
126 /* Setup EFER (Extended Feature Enable Register) */
130 /* Enable System Call */
131 btsl $_EFER_SCE, %eax
133 /* No Execute supported? */
138 /* Make changes effective */
142 #define CR0_PM 1 /* protected mode */
143 #define CR0_MP (1<<1)
144 #define CR0_ET (1<<4)
145 #define CR0_NE (1<<5)
146 #define CR0_WP (1<<16)
147 #define CR0_AM (1<<18)
148 #define CR0_PAGING (1<<31)
149 movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
150 /* Make changes effective */
153 /* Setup a boot time stack */
154 movq init_rsp(%rip),%rsp
156 /* zero EFLAGS after setting rsp */
161 * We must switch to a new descriptor in kernel space for the GDT
162 * because soon the kernel won't have access anymore to the userspace
163 * addresses where we're currently running on. We have to do that here
164 * because in 32bit we couldn't load a 64bit linear address.
169 * Setup up a dummy PDA. this is just for some early bootup code
170 * that does in_interrupt()
172 movl $MSR_GS_BASE,%ecx
173 movq $empty_zero_page,%rax
178 /* set up data segments. actually 0 would do too */
179 movl $__KERNEL_DS,%eax
184 /* esi is pointer to real mode structure with interesting info.
188 /* Finally jump to run C code and to be on real kernel address
189 * Since we are running on identity-mapped space we have to jump
190 * to the full 64bit address , this is only possible as indirect
193 movq initial_code(%rip),%rax
194 pushq $0 # fake return address
197 /* SMP bootup changes these two */
201 .quad x86_64_start_kernel
204 .quad init_thread_union+THREAD_SIZE-8
206 ENTRY(early_idt_handler)
207 cmpl $2,early_recursion_flag(%rip)
209 incl early_recursion_flag(%rip)
211 movq 8(%rsp),%rsi # get rip
214 leaq early_idt_msg(%rip),%rdi
216 cmpl $2,early_recursion_flag(%rip)
219 #ifdef CONFIG_KALLSYMS
220 leaq early_idt_ripmsg(%rip),%rdi
221 movq 8(%rsp),%rsi # get rip again
226 early_recursion_flag:
230 .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
236 /* This isn't an x86-64 CPU so hang */
243 .word gdt_end-cpu_gdt_table-1
244 .long cpu_gdt_table-__START_KERNEL_map
248 .long startup_64-__START_KERNEL_map
255 #define NEXT_PAGE(name) \
257 .org $page * 0x1000; \
258 phys_/**/name = $page * 0x1000 + __PHYSICAL_START; \
261 NEXT_PAGE(init_level4_pgt)
262 /* This gets initialized in x86_64_start_kernel */
265 NEXT_PAGE(level3_ident_pgt)
266 .quad phys_level2_ident_pgt | 0x007
269 NEXT_PAGE(level3_kernel_pgt)
271 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
272 .quad phys_level2_kernel_pgt | 0x007
275 NEXT_PAGE(level2_ident_pgt)
276 /* 40MB for bootup. */
279 .quad i << 21 | 0x083
282 /* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
283 .globl temp_boot_pmds
287 NEXT_PAGE(level2_kernel_pgt)
288 /* 40MB kernel mapping. The kernel code cannot be bigger than that.
289 When you change this change KERNEL_TEXT_SIZE in page.h too. */
290 /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
293 .quad i << 21 | 0x183
296 /* Module mapping starts here */
299 NEXT_PAGE(level3_physmem_pgt)
300 .quad phys_level2_kernel_pgt | 0x007 /* so that __va works even before pagetable_init */
307 #ifdef CONFIG_ACPI_SLEEP
309 ENTRY(wakeup_level4_pgt)
310 .quad phys_level3_ident_pgt | 0x007
312 .quad phys_level3_physmem_pgt | 0x007
314 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
315 .quad phys_level3_kernel_pgt | 0x007
318 #ifndef CONFIG_HOTPLUG_CPU
322 * This default setting generates an ident mapping at address 0x100000
323 * and a mapping for the kernel that precisely maps virtual address
324 * 0xffffffff80000000 to physical address 0x000000. (always using
325 * 2Mbyte large pages provided by PAE mode)
328 ENTRY(boot_level4_pgt)
329 .quad phys_level3_ident_pgt | 0x007
331 .quad phys_level3_physmem_pgt | 0x007
333 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
334 .quad phys_level3_kernel_pgt | 0x007
341 .word gdt_end-cpu_gdt_table-1
351 /* We need valid kernel segments for data and code in long mode too
352 * IRET will check the segment types kkeil 2000/10/28
353 * Also sysret mandates a special GDT layout
356 .section .data.page_aligned, "aw"
359 /* The TLS descriptors are currently at a different place compared to i386.
360 Hopefully nobody expects them at a fixed place (Wine?) */
363 .quad 0x0000000000000000 /* NULL descriptor */
364 .quad 0x0 /* unused */
365 .quad 0x00af9a000000ffff /* __KERNEL_CS */
366 .quad 0x00cf92000000ffff /* __KERNEL_DS */
367 .quad 0x00cffa000000ffff /* __USER32_CS */
368 .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
369 .quad 0x00affa000000ffff /* __USER_CS */
370 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */
373 .quad 0,0,0 /* three TLS descriptors */
376 /* asm/segment.h:GDT_ENTRIES must match this */
377 /* This should be a multiple of the cache line size */
378 /* GDTs of other CPUs are now dynamically allocated */
380 /* zero the remaining page */
381 .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
383 .section .bss, "aw", @nobits
384 .align L1_CACHE_BYTES
388 .section .bss.page_aligned, "aw", @nobits
390 ENTRY(empty_zero_page)