2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
44 int apic_runs_main_timer;
45 int apic_calibrate_pmtmr __initdata;
47 int disable_apic_timer __initdata;
49 static struct resource *ioapic_resources;
50 static struct resource lapic_resource = {
52 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
56 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
57 * IPIs in place of local APIC timers
59 static cpumask_t timer_interrupt_broadcast_ipi_mask;
61 /* Using APIC to generate smp_local_timer_interrupt? */
62 int using_apic_timer __read_mostly = 0;
64 static void apic_pm_activate(void);
66 void enable_NMI_through_LVT0 (void * dummy)
70 v = APIC_DM_NMI; /* unmask and set to NMI */
71 apic_write(APIC_LVT0, v);
76 unsigned int v, maxlvt;
78 v = apic_read(APIC_LVR);
79 maxlvt = GET_APIC_MAXLVT(v);
84 * 'what should we do if we get a hw irq event on an illegal vector'.
85 * each architecture has to answer this themselves.
87 void ack_bad_irq(unsigned int irq)
89 printk("unexpected IRQ trap at vector %02x\n", irq);
91 * Currently unexpected vectors happen only on SMP and APIC.
92 * We _must_ ack these because every local APIC has only N
93 * irq slots per priority level, and a 'hanging, unacked' IRQ
94 * holds up an irq slot - in excessive cases (when multiple
95 * unexpected vectors occur) that might lock up the APIC
97 * But don't ack when the APIC is disabled. -AK
103 void clear_local_APIC(void)
108 maxlvt = get_maxlvt();
111 * Masking an LVT entry can trigger a local APIC error
112 * if the vector is zero. Mask LVTERR first to prevent this.
115 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
116 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
119 * Careful: we have to set masks only first to deassert
120 * any level-triggered sources.
122 v = apic_read(APIC_LVTT);
123 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
124 v = apic_read(APIC_LVT0);
125 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
126 v = apic_read(APIC_LVT1);
127 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
129 v = apic_read(APIC_LVTPC);
130 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
134 * Clean APIC state for other OSs:
136 apic_write(APIC_LVTT, APIC_LVT_MASKED);
137 apic_write(APIC_LVT0, APIC_LVT_MASKED);
138 apic_write(APIC_LVT1, APIC_LVT_MASKED);
140 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
142 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
143 v = GET_APIC_VERSION(apic_read(APIC_LVR));
144 apic_write(APIC_ESR, 0);
148 void disconnect_bsp_APIC(int virt_wire_setup)
150 /* Go back to Virtual Wire compatibility mode */
153 /* For the spurious interrupt use vector F, and enable it */
154 value = apic_read(APIC_SPIV);
155 value &= ~APIC_VECTOR_MASK;
156 value |= APIC_SPIV_APIC_ENABLED;
158 apic_write(APIC_SPIV, value);
160 if (!virt_wire_setup) {
161 /* For LVT0 make it edge triggered, active high, external and enabled */
162 value = apic_read(APIC_LVT0);
163 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
164 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
165 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
166 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
167 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
168 apic_write(APIC_LVT0, value);
171 apic_write(APIC_LVT0, APIC_LVT_MASKED);
174 /* For LVT1 make it edge triggered, active high, nmi and enabled */
175 value = apic_read(APIC_LVT1);
176 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
177 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
178 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
179 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
180 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
181 apic_write(APIC_LVT1, value);
184 void disable_local_APIC(void)
191 * Disable APIC (implies clearing of registers
194 value = apic_read(APIC_SPIV);
195 value &= ~APIC_SPIV_APIC_ENABLED;
196 apic_write(APIC_SPIV, value);
200 * This is to verify that we're looking at a real local APIC.
201 * Check these against your board if the CPUs aren't getting
202 * started for no apparent reason.
204 int __init verify_local_APIC(void)
206 unsigned int reg0, reg1;
209 * The version register is read-only in a real APIC.
211 reg0 = apic_read(APIC_LVR);
212 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
213 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
214 reg1 = apic_read(APIC_LVR);
215 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
218 * The two version reads above should print the same
219 * numbers. If the second one is different, then we
220 * poke at a non-APIC.
226 * Check if the version looks reasonably.
228 reg1 = GET_APIC_VERSION(reg0);
229 if (reg1 == 0x00 || reg1 == 0xff)
232 if (reg1 < 0x02 || reg1 == 0xff)
236 * The ID register is read/write in a real APIC.
238 reg0 = apic_read(APIC_ID);
239 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
240 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
241 reg1 = apic_read(APIC_ID);
242 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
243 apic_write(APIC_ID, reg0);
244 if (reg1 != (reg0 ^ APIC_ID_MASK))
248 * The next two are just to see if we have sane values.
249 * They're only really relevant if we're in Virtual Wire
250 * compatibility mode, but most boxes are anymore.
252 reg0 = apic_read(APIC_LVT0);
253 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
254 reg1 = apic_read(APIC_LVT1);
255 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
260 void __init sync_Arb_IDs(void)
262 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
263 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
264 if (ver >= 0x14) /* P4 or higher */
270 apic_wait_icr_idle();
272 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
273 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
278 * An initial setup of the virtual wire mode.
280 void __init init_bsp_APIC(void)
285 * Don't do the setup now if we have a SMP BIOS as the
286 * through-I/O-APIC virtual wire mode might be active.
288 if (smp_found_config || !cpu_has_apic)
291 value = apic_read(APIC_LVR);
294 * Do not trust the local APIC being empty at bootup.
301 value = apic_read(APIC_SPIV);
302 value &= ~APIC_VECTOR_MASK;
303 value |= APIC_SPIV_APIC_ENABLED;
304 value |= APIC_SPIV_FOCUS_DISABLED;
305 value |= SPURIOUS_APIC_VECTOR;
306 apic_write(APIC_SPIV, value);
309 * Set up the virtual wire mode.
311 apic_write(APIC_LVT0, APIC_DM_EXTINT);
313 apic_write(APIC_LVT1, value);
316 void __cpuinit setup_local_APIC (void)
318 unsigned int value, maxlvt;
321 value = apic_read(APIC_LVR);
323 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
326 * Double-check whether this APIC is really registered.
327 * This is meaningless in clustered apic mode, so we skip it.
329 if (!apic_id_registered())
333 * Intel recommends to set DFR, LDR and TPR before enabling
334 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
335 * document number 292116). So here it goes...
340 * Set Task Priority to 'accept all'. We never change this
343 value = apic_read(APIC_TASKPRI);
344 value &= ~APIC_TPRI_MASK;
345 apic_write(APIC_TASKPRI, value);
348 * After a crash, we no longer service the interrupts and a pending
349 * interrupt from previous kernel might still have ISR bit set.
351 * Most probably by now CPU has serviced that pending interrupt and
352 * it might not have done the ack_APIC_irq() because it thought,
353 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
354 * does not clear the ISR bit and cpu thinks it has already serivced
355 * the interrupt. Hence a vector might get locked. It was noticed
356 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
358 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
359 value = apic_read(APIC_ISR + i*0x10);
360 for (j = 31; j >= 0; j--) {
367 * Now that we are all set up, enable the APIC
369 value = apic_read(APIC_SPIV);
370 value &= ~APIC_VECTOR_MASK;
374 value |= APIC_SPIV_APIC_ENABLED;
376 /* We always use processor focus */
379 * Set spurious IRQ vector
381 value |= SPURIOUS_APIC_VECTOR;
382 apic_write(APIC_SPIV, value);
387 * set up through-local-APIC on the BP's LINT0. This is not
388 * strictly necessary in pure symmetric-IO mode, but sometimes
389 * we delegate interrupts to the 8259A.
392 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
394 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
395 if (!smp_processor_id() && !value) {
396 value = APIC_DM_EXTINT;
397 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
399 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
400 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
402 apic_write(APIC_LVT0, value);
405 * only the BP should see the LINT1 NMI signal, obviously.
407 if (!smp_processor_id())
410 value = APIC_DM_NMI | APIC_LVT_MASKED;
411 apic_write(APIC_LVT1, value);
415 maxlvt = get_maxlvt();
416 oldvalue = apic_read(APIC_ESR);
417 value = ERROR_APIC_VECTOR; // enables sending errors
418 apic_write(APIC_LVTERR, value);
420 * spec says clear errors after enabling vector.
423 apic_write(APIC_ESR, 0);
424 value = apic_read(APIC_ESR);
425 if (value != oldvalue)
426 apic_printk(APIC_VERBOSE,
427 "ESR value after enabling vector: %08x, after %08x\n",
431 nmi_watchdog_default();
432 setup_apic_nmi_watchdog(NULL);
439 /* 'active' is true if the local APIC was enabled by us and
440 not the BIOS; this signifies that we are also responsible
441 for disabling it before entering apm/acpi suspend */
443 /* r/w apic fields */
444 unsigned int apic_id;
445 unsigned int apic_taskpri;
446 unsigned int apic_ldr;
447 unsigned int apic_dfr;
448 unsigned int apic_spiv;
449 unsigned int apic_lvtt;
450 unsigned int apic_lvtpc;
451 unsigned int apic_lvt0;
452 unsigned int apic_lvt1;
453 unsigned int apic_lvterr;
454 unsigned int apic_tmict;
455 unsigned int apic_tdcr;
456 unsigned int apic_thmr;
459 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
464 if (!apic_pm_state.active)
467 maxlvt = get_maxlvt();
469 apic_pm_state.apic_id = apic_read(APIC_ID);
470 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
471 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
472 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
473 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
474 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
476 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
477 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
478 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
479 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
480 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
481 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
482 #ifdef CONFIG_X86_MCE_INTEL
484 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
486 local_irq_save(flags);
487 disable_local_APIC();
488 local_irq_restore(flags);
492 static int lapic_resume(struct sys_device *dev)
498 if (!apic_pm_state.active)
501 maxlvt = get_maxlvt();
503 local_irq_save(flags);
504 rdmsr(MSR_IA32_APICBASE, l, h);
505 l &= ~MSR_IA32_APICBASE_BASE;
506 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
507 wrmsr(MSR_IA32_APICBASE, l, h);
508 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
509 apic_write(APIC_ID, apic_pm_state.apic_id);
510 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
511 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
512 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
513 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
514 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
515 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
516 #ifdef CONFIG_X86_MCE_INTEL
518 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
521 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
522 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
523 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
524 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
525 apic_write(APIC_ESR, 0);
527 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
528 apic_write(APIC_ESR, 0);
530 local_irq_restore(flags);
534 static struct sysdev_class lapic_sysclass = {
535 set_kset_name("lapic"),
536 .resume = lapic_resume,
537 .suspend = lapic_suspend,
540 static struct sys_device device_lapic = {
542 .cls = &lapic_sysclass,
545 static void __cpuinit apic_pm_activate(void)
547 apic_pm_state.active = 1;
550 static int __init init_lapic_sysfs(void)
555 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
556 error = sysdev_class_register(&lapic_sysclass);
558 error = sysdev_register(&device_lapic);
561 device_initcall(init_lapic_sysfs);
563 #else /* CONFIG_PM */
565 static void apic_pm_activate(void) { }
567 #endif /* CONFIG_PM */
569 static int __init apic_set_verbosity(char *str)
572 skip_ioapic_setup = 0;
576 if (strcmp("debug", str) == 0)
577 apic_verbosity = APIC_DEBUG;
578 else if (strcmp("verbose", str) == 0)
579 apic_verbosity = APIC_VERBOSE;
581 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
582 " use apic=verbose or apic=debug\n", str);
588 early_param("apic", apic_set_verbosity);
591 * Detect and enable local APICs on non-SMP boards.
592 * Original code written by Keir Fraser.
593 * On AMD64 we trust the BIOS - if it says no APIC it is likely
594 * not correctly set up (usually the APIC timer won't work etc.)
597 static int __init detect_init_APIC (void)
600 printk(KERN_INFO "No local APIC present\n");
604 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
609 #ifdef CONFIG_X86_IO_APIC
610 static struct resource * __init ioapic_setup_resources(void)
612 #define IOAPIC_RESOURCE_NAME_SIZE 11
614 struct resource *res;
621 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
624 mem = alloc_bootmem(n);
629 mem += sizeof(struct resource) * nr_ioapics;
631 for (i = 0; i < nr_ioapics; i++) {
633 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
634 sprintf(mem, "IOAPIC %u", i);
635 mem += IOAPIC_RESOURCE_NAME_SIZE;
639 ioapic_resources = res;
644 static int __init ioapic_insert_resources(void)
647 struct resource *r = ioapic_resources;
650 printk("IO APIC resources could be not be allocated.\n");
654 for (i = 0; i < nr_ioapics; i++) {
655 insert_resource(&iomem_resource, r);
662 /* Insert the IO APIC resources after PCI initialization has occured to handle
663 * IO APICS that are mapped in on a BAR in PCI space. */
664 late_initcall(ioapic_insert_resources);
667 void __init init_apic_mappings(void)
669 unsigned long apic_phys;
672 * If no local APIC can be found then set up a fake all
673 * zeroes page to simulate the local APIC and another
674 * one for the IO-APIC.
676 if (!smp_found_config && detect_init_APIC()) {
677 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
678 apic_phys = __pa(apic_phys);
680 apic_phys = mp_lapic_addr;
682 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
684 apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
686 /* Put local APIC into the resource map. */
687 lapic_resource.start = apic_phys;
688 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
689 insert_resource(&iomem_resource, &lapic_resource);
692 * Fetch the APIC ID of the BSP in case we have a
693 * default configuration (or the MP table is broken).
695 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
698 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
700 struct resource *ioapic_res;
702 ioapic_res = ioapic_setup_resources();
703 for (i = 0; i < nr_ioapics; i++) {
704 if (smp_found_config) {
705 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
707 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
708 ioapic_phys = __pa(ioapic_phys);
710 set_fixmap_nocache(idx, ioapic_phys);
711 apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
712 __fix_to_virt(idx), ioapic_phys);
715 if (ioapic_res != NULL) {
716 ioapic_res->start = ioapic_phys;
717 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
725 * This function sets up the local APIC timer, with a timeout of
726 * 'clocks' APIC bus clock. During calibration we actually call
727 * this function twice on the boot CPU, once with a bogus timeout
728 * value, second time for real. The other (noncalibrating) CPUs
729 * call this function only once, with the real, calibrated value.
731 * We do reads before writes even if unnecessary, to get around the
732 * P5 APIC double write bug.
735 #define APIC_DIVISOR 16
737 static void __setup_APIC_LVTT(unsigned int clocks)
739 unsigned int lvtt_value, tmp_value, ver;
740 int cpu = smp_processor_id();
742 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
743 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
745 if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask))
746 lvtt_value |= APIC_LVT_MASKED;
748 apic_write(APIC_LVTT, lvtt_value);
753 tmp_value = apic_read(APIC_TDCR);
754 apic_write(APIC_TDCR, (tmp_value
755 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
758 apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
761 static void setup_APIC_timer(unsigned int clocks)
765 local_irq_save(flags);
767 /* wait for irq slice */
768 if (vxtime.hpet_address && hpet_use_timer) {
769 int trigger = hpet_readl(HPET_T0_CMP);
770 while (hpet_readl(HPET_COUNTER) >= trigger)
772 while (hpet_readl(HPET_COUNTER) < trigger)
778 c2 |= inb_p(0x40) << 8;
783 c2 |= inb_p(0x40) << 8;
784 } while (c2 - c1 < 300);
786 __setup_APIC_LVTT(clocks);
787 /* Turn off PIT interrupt if we use APIC timer as main timer.
788 Only works with the PM timer right now
789 TBD fix it for HPET too. */
790 if (vxtime.mode == VXTIME_PMTMR &&
791 smp_processor_id() == boot_cpu_id &&
792 apic_runs_main_timer == 1 &&
793 !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) {
794 stop_timer_interrupt();
795 apic_runs_main_timer++;
797 local_irq_restore(flags);
801 * In this function we calibrate APIC bus clocks to the external
802 * timer. Unfortunately we cannot use jiffies and the timer irq
803 * to calibrate, since some later bootup code depends on getting
804 * the first irq? Ugh.
806 * We want to do the calibration only once since we
807 * want to have local timer irqs syncron. CPUs connected
808 * by the same APIC bus have the very same bus frequency.
809 * And we want to have irqs off anyways, no accidental
813 #define TICK_COUNT 100000000
815 static int __init calibrate_APIC_clock(void)
817 int apic, apic_start, tsc, tsc_start;
820 * Put whatever arbitrary (but long enough) timeout
821 * value into the APIC clock, we just want to get the
822 * counter running for calibration.
824 __setup_APIC_LVTT(1000000000);
826 apic_start = apic_read(APIC_TMCCT);
827 #ifdef CONFIG_X86_PM_TIMER
828 if (apic_calibrate_pmtmr && pmtmr_ioport) {
829 pmtimer_wait(5000); /* 5ms wait */
830 apic = apic_read(APIC_TMCCT);
831 result = (apic_start - apic) * 1000L / 5;
838 apic = apic_read(APIC_TMCCT);
840 } while ((tsc - tsc_start) < TICK_COUNT &&
841 (apic - apic_start) < TICK_COUNT);
843 result = (apic_start - apic) * 1000L * cpu_khz /
846 printk("result %d\n", result);
849 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
850 result / 1000 / 1000, result / 1000 % 1000);
852 return result * APIC_DIVISOR / HZ;
855 static unsigned int calibration_result;
857 void __init setup_boot_APIC_clock (void)
859 if (disable_apic_timer) {
860 printk(KERN_INFO "Disabling APIC timer\n");
864 printk(KERN_INFO "Using local APIC timer interrupts.\n");
865 using_apic_timer = 1;
869 calibration_result = calibrate_APIC_clock();
871 * Now set up the timer for real.
873 setup_APIC_timer(calibration_result);
878 void __cpuinit setup_secondary_APIC_clock(void)
880 local_irq_disable(); /* FIXME: Do we need this? --RR */
881 setup_APIC_timer(calibration_result);
885 void disable_APIC_timer(void)
887 if (using_apic_timer) {
890 v = apic_read(APIC_LVTT);
892 * When an illegal vector value (0-15) is written to an LVT
893 * entry and delivery mode is Fixed, the APIC may signal an
894 * illegal vector error, with out regard to whether the mask
895 * bit is set or whether an interrupt is actually seen on input.
897 * Boot sequence might call this function when the LVTT has
898 * '0' vector value. So make sure vector field is set to
901 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
902 apic_write(APIC_LVTT, v);
906 void enable_APIC_timer(void)
908 int cpu = smp_processor_id();
910 if (using_apic_timer &&
911 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
914 v = apic_read(APIC_LVTT);
915 apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
919 void switch_APIC_timer_to_ipi(void *cpumask)
921 cpumask_t mask = *(cpumask_t *)cpumask;
922 int cpu = smp_processor_id();
924 if (cpu_isset(cpu, mask) &&
925 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
926 disable_APIC_timer();
927 cpu_set(cpu, timer_interrupt_broadcast_ipi_mask);
930 EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
932 void smp_send_timer_broadcast_ipi(void)
936 cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask);
937 if (!cpus_empty(mask)) {
938 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
942 void switch_ipi_to_APIC_timer(void *cpumask)
944 cpumask_t mask = *(cpumask_t *)cpumask;
945 int cpu = smp_processor_id();
947 if (cpu_isset(cpu, mask) &&
948 cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
949 cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask);
953 EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
955 int setup_profiling_timer(unsigned int multiplier)
960 void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector,
961 unsigned char msg_type, unsigned char mask)
963 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
964 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
971 * Local timer interrupt handler. It does both profiling and
972 * process statistics/rescheduling.
974 * We do profiling in every local tick, statistics/rescheduling
975 * happen only every 'profiling multiplier' ticks. The default
976 * multiplier is 1 and it can be changed by writing the new multiplier
977 * value into /proc/profile.
980 void smp_local_timer_interrupt(void)
982 profile_tick(CPU_PROFILING);
984 update_process_times(user_mode(get_irq_regs()));
986 if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id)
987 main_timer_handler();
989 * We take the 'long' return path, and there every subsystem
990 * grabs the appropriate locks (kernel lock/ irq lock).
992 * We might want to decouple profiling from the 'long path',
993 * and do the profiling totally in assembly.
995 * Currently this isn't too much of an issue (performance wise),
996 * we can take more than 100K local irqs per second on a 100 MHz P5.
1001 * Local APIC timer interrupt. This is the most natural way for doing
1002 * local interrupts, but local timer interrupts can be emulated by
1003 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1005 * [ if a single-CPU system runs an SMP kernel then we call the local
1006 * interrupt as well. Thus we cannot inline the local irq ... ]
1008 void smp_apic_timer_interrupt(struct pt_regs *regs)
1010 struct pt_regs *old_regs = set_irq_regs(regs);
1013 * the NMI deadlock-detector uses this.
1015 add_pda(apic_timer_irqs, 1);
1018 * NOTE! We'd better ACK the irq immediately,
1019 * because timer handling can be slow.
1023 * update_process_times() expects us to have done irq_enter().
1024 * Besides, if we don't timer interrupts ignore the global
1025 * interrupt lock, which is the WrongThing (tm) to do.
1029 smp_local_timer_interrupt();
1031 set_irq_regs(old_regs);
1035 * apic_is_clustered_box() -- Check if we can expect good TSC
1037 * Thus far, the major user of this is IBM's Summit2 series:
1039 * Clustered boxes may have unsynced TSC problems if they are
1040 * multi-chassis. Use available data to take a good guess.
1041 * If in doubt, go HPET.
1043 __cpuinit int apic_is_clustered_box(void)
1045 int i, clusters, zeros;
1047 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1049 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1051 for (i = 0; i < NR_CPUS; i++) {
1052 id = bios_cpu_apicid[i];
1053 if (id != BAD_APICID)
1054 __set_bit(APIC_CLUSTERID(id), clustermap);
1057 /* Problem: Partially populated chassis may not have CPUs in some of
1058 * the APIC clusters they have been allocated. Only present CPUs have
1059 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1060 * clusters are allocated sequentially, count zeros only if they are
1065 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1066 if (test_bit(i, clustermap)) {
1067 clusters += 1 + zeros;
1074 * If clusters > 2, then should be multi-chassis.
1075 * May have to revisit this when multi-core + hyperthreaded CPUs come
1076 * out, but AFAIK this will work even for them.
1078 return (clusters > 2);
1082 * This interrupt should _never_ happen with our APIC/SMP architecture
1084 asmlinkage void smp_spurious_interrupt(void)
1090 * Check if this really is a spurious interrupt and ACK it
1091 * if it is a vectored one. Just in case...
1092 * Spurious interrupts should not be ACKed.
1094 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1095 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1099 static unsigned long last_warning;
1100 static unsigned long skipped;
1102 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1103 if (time_before(last_warning+30*HZ,jiffies)) {
1104 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1105 smp_processor_id(), skipped);
1106 last_warning = jiffies;
1116 * This interrupt should never happen with our APIC/SMP architecture
1119 asmlinkage void smp_error_interrupt(void)
1125 /* First tickle the hardware, only then report what went on. -- REW */
1126 v = apic_read(APIC_ESR);
1127 apic_write(APIC_ESR, 0);
1128 v1 = apic_read(APIC_ESR);
1130 atomic_inc(&irq_err_count);
1132 /* Here is what the APIC error bits mean:
1135 2: Send accept error
1136 3: Receive accept error
1138 5: Send illegal vector
1139 6: Received illegal vector
1140 7: Illegal register address
1142 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1143 smp_processor_id(), v , v1);
1150 * This initializes the IO-APIC and APIC hardware if this is
1153 int __init APIC_init_uniprocessor (void)
1156 printk(KERN_INFO "Apic disabled\n");
1159 if (!cpu_has_apic) {
1161 printk(KERN_INFO "Apic disabled by BIOS\n");
1165 verify_local_APIC();
1167 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1168 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
1172 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1176 setup_boot_APIC_clock();
1177 check_nmi_watchdog();
1181 static __init int setup_disableapic(char *str)
1184 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1187 early_param("disableapic", setup_disableapic);
1189 /* same as disableapic, for compatibility */
1190 static __init int setup_nolapic(char *str)
1192 return setup_disableapic(str);
1194 early_param("nolapic", setup_nolapic);
1196 static __init int setup_noapictimer(char *str)
1198 if (str[0] != ' ' && str[0] != 0)
1200 disable_apic_timer = 1;
1204 static __init int setup_apicmaintimer(char *str)
1206 apic_runs_main_timer = 1;
1210 __setup("apicmaintimer", setup_apicmaintimer);
1212 static __init int setup_noapicmaintimer(char *str)
1214 apic_runs_main_timer = -1;
1217 __setup("noapicmaintimer", setup_noapicmaintimer);
1219 static __init int setup_apicpmtimer(char *s)
1221 apic_calibrate_pmtmr = 1;
1223 return setup_apicmaintimer(NULL);
1225 __setup("apicpmtimer", setup_apicpmtimer);
1227 __setup("noapictimer", setup_noapictimer);