2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/sfi.h>
18 #include <linux/intel_pmic_gpio.h>
19 #include <linux/spi/spi.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca953x.h>
22 #include <linux/gpio_keys.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
28 #include <asm/setup.h>
29 #include <asm/mpspec_def.h>
30 #include <asm/hw_irq.h>
32 #include <asm/io_apic.h>
35 #include <asm/i8259.h>
36 #include <asm/intel_scu_ipc.h>
37 #include <asm/apb_timer.h>
41 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
42 * cmdline option x86_mrst_timer can be used to override the configuration
43 * to prefer one or the other.
44 * at runtime, there are basically three timer configurations:
45 * 1. per cpu apbt clock only
46 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
47 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
49 * by default (without cmdline option), platform code first detects cpu type
50 * to see if we are on lincroft or penwell, then set up both lapic or apbt
52 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
53 * config #3 is supported but not recommended on medfield.
55 * rating and feature summary:
56 * lapic (with C3STOP) --------- 100
57 * apbt (always-on) ------------ 110
58 * lapic (always-on,ARAT) ------ 150
61 __cpuinitdata enum mrst_timer_options mrst_timer_options;
63 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
64 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
65 enum mrst_cpu_type __mrst_cpu_chip;
66 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
70 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
71 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
74 static inline void assign_to_mp_irq(struct mpc_intsrc *m,
75 struct mpc_intsrc *mp_irq)
77 memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
80 static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
83 return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
86 static void save_mp_irq(struct mpc_intsrc *m)
90 for (i = 0; i < mp_irq_entries; i++) {
91 if (!mp_irq_cmp(&mp_irqs[i], m))
95 assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
96 if (++mp_irq_entries == MAX_IRQ_SOURCES)
97 panic("Max # of irq sources exceeded!!\n");
100 /* parse all the mtimer info to a static mtimer array */
101 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
103 struct sfi_table_simple *sb;
104 struct sfi_timer_table_entry *pentry;
105 struct mpc_intsrc mp_irq;
108 sb = (struct sfi_table_simple *)table;
109 if (!sfi_mtimer_num) {
110 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
111 struct sfi_timer_table_entry);
112 pentry = (struct sfi_timer_table_entry *) sb->pentry;
113 totallen = sfi_mtimer_num * sizeof(*pentry);
114 memcpy(sfi_mtimer_array, pentry, totallen);
117 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
118 pentry = sfi_mtimer_array;
119 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
120 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
121 " irq = %d\n", totallen, (u32)pentry->phys_addr,
122 pentry->freq_hz, pentry->irq);
125 mp_irq.type = MP_IOAPIC;
126 mp_irq.irqtype = mp_INT;
127 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
130 mp_irq.srcbusirq = pentry->irq; /* IRQ */
131 mp_irq.dstapic = MP_APIC_ALL;
132 mp_irq.dstirq = pentry->irq;
133 save_mp_irq(&mp_irq);
139 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
142 if (hint < sfi_mtimer_num) {
143 if (!sfi_mtimer_usage[hint]) {
144 pr_debug("hint taken for timer %d irq %d\n",\
145 hint, sfi_mtimer_array[hint].irq);
146 sfi_mtimer_usage[hint] = 1;
147 return &sfi_mtimer_array[hint];
150 /* take the first timer available */
151 for (i = 0; i < sfi_mtimer_num;) {
152 if (!sfi_mtimer_usage[i]) {
153 sfi_mtimer_usage[i] = 1;
154 return &sfi_mtimer_array[i];
161 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
164 for (i = 0; i < sfi_mtimer_num;) {
165 if (mtmr->irq == sfi_mtimer_array[i].irq) {
166 sfi_mtimer_usage[i] = 0;
173 /* parse all the mrtc info to a global mrtc array */
174 int __init sfi_parse_mrtc(struct sfi_table_header *table)
176 struct sfi_table_simple *sb;
177 struct sfi_rtc_table_entry *pentry;
178 struct mpc_intsrc mp_irq;
182 sb = (struct sfi_table_simple *)table;
184 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
185 struct sfi_rtc_table_entry);
186 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
187 totallen = sfi_mrtc_num * sizeof(*pentry);
188 memcpy(sfi_mrtc_array, pentry, totallen);
191 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
192 pentry = sfi_mrtc_array;
193 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
194 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
195 totallen, (u32)pentry->phys_addr, pentry->irq);
196 mp_irq.type = MP_IOAPIC;
197 mp_irq.irqtype = mp_INT;
200 mp_irq.srcbusirq = pentry->irq; /* IRQ */
201 mp_irq.dstapic = MP_APIC_ALL;
202 mp_irq.dstirq = pentry->irq;
203 save_mp_irq(&mp_irq);
208 static unsigned long __init mrst_calibrate_tsc(void)
210 unsigned long flags, fast_calibrate;
212 local_irq_save(flags);
213 fast_calibrate = apbt_quick_calibrate();
214 local_irq_restore(flags);
217 return fast_calibrate;
222 void __init mrst_time_init(void)
224 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
225 switch (mrst_timer_options) {
226 case MRST_TIMER_APBT_ONLY:
228 case MRST_TIMER_LAPIC_APBT:
229 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
230 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
233 if (!boot_cpu_has(X86_FEATURE_ARAT))
235 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
236 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
239 /* we need at least one APB timer */
240 pre_init_apic_IRQ0();
244 void __init mrst_rtc_init(void)
246 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
249 void __cpuinit mrst_arch_setup(void)
251 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
252 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
253 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
254 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
256 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
257 boot_cpu_data.x86, boot_cpu_data.x86_model);
258 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
260 pr_debug("Moorestown CPU %s identified\n",
261 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
262 "Lincroft" : "Penwell");
265 /* MID systems don't have i8042 controller */
266 static int mrst_i8042_detect(void)
272 * Moorestown specific x86_init function overrides and early setup
275 void __init x86_mrst_early_setup(void)
277 x86_init.resources.probe_roms = x86_init_noop;
278 x86_init.resources.reserve_resources = x86_init_noop;
280 x86_init.timers.timer_init = mrst_time_init;
281 x86_init.timers.setup_percpu_clockev = x86_init_noop;
283 x86_init.irqs.pre_vector_init = x86_init_noop;
285 x86_init.oem.arch_setup = mrst_arch_setup;
287 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
289 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
290 x86_platform.i8042_detect = mrst_i8042_detect;
291 x86_init.pci.init = pci_mrst_init;
292 x86_init.pci.fixup_irqs = x86_init_noop;
294 legacy_pic = &null_legacy_pic;
296 /* Avoid searching for BIOS MP tables */
297 x86_init.mpparse.find_smp_config = x86_init_noop;
298 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
303 * if user does not want to use per CPU apb timer, just give it a lower rating
304 * than local apic timer and skip the late per cpu timer init.
306 static inline int __init setup_x86_mrst_timer(char *arg)
311 if (strcmp("apbt_only", arg) == 0)
312 mrst_timer_options = MRST_TIMER_APBT_ONLY;
313 else if (strcmp("lapic_and_apbt", arg) == 0)
314 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
316 pr_warning("X86 MRST timer option %s not recognised"
317 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
323 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
326 * Parsing GPIO table first, since the DEVS table will need this table
327 * to map the pin name to the actual pin.
329 static struct sfi_gpio_table_entry *gpio_table;
330 static int gpio_num_entry;
332 static int __init sfi_parse_gpio(struct sfi_table_header *table)
334 struct sfi_table_simple *sb;
335 struct sfi_gpio_table_entry *pentry;
340 sb = (struct sfi_table_simple *)table;
341 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
342 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
344 gpio_table = (struct sfi_gpio_table_entry *)
345 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
348 memcpy(gpio_table, pentry, num * sizeof(*pentry));
349 gpio_num_entry = num;
351 pr_debug("GPIO pin info:\n");
352 for (i = 0; i < num; i++, pentry++)
353 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
355 pentry->controller_name,
361 static int get_gpio_by_name(const char *name)
363 struct sfi_gpio_table_entry *pentry = gpio_table;
368 for (i = 0; i < gpio_num_entry; i++, pentry++) {
369 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
370 return pentry->pin_no;
376 * Here defines the array of devices platform data that IAFW would export
377 * through SFI "DEVS" table, we use name and type to match the device and
381 char name[SFI_NAME_LEN + 1];
384 void *(*get_platform_data)(void *info);
387 /* the offset for the mapping of global gpio pin to irq */
388 #define MRST_IRQ_OFFSET 0x100
390 static void __init *pmic_gpio_platform_data(void *info)
392 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
393 int gpio_base = get_gpio_by_name("pmic_gpio_base");
397 pmic_gpio_pdata.gpio_base = gpio_base;
398 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
399 pmic_gpio_pdata.gpiointr = 0xffffeff8;
401 return &pmic_gpio_pdata;
404 static void __init *max3111_platform_data(void *info)
406 struct spi_board_info *spi_info = info;
407 int intr = get_gpio_by_name("max3111_int");
411 spi_info->irq = intr + MRST_IRQ_OFFSET;
415 /* we have multiple max7315 on the board ... */
416 #define MAX7315_NUM 2
417 static void __init *max7315_platform_data(void *info)
419 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
421 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
422 struct i2c_board_info *i2c_info = info;
424 char base_pin_name[SFI_NAME_LEN + 1];
425 char intr_pin_name[SFI_NAME_LEN + 1];
427 if (nr == MAX7315_NUM) {
428 pr_err("too many max7315s, we only support %d\n",
432 /* we have several max7315 on the board, we only need load several
433 * instances of the same pca953x driver to cover them
435 strcpy(i2c_info->type, "max7315");
437 sprintf(base_pin_name, "max7315_%d_base", nr);
438 sprintf(intr_pin_name, "max7315_%d_int", nr);
440 strcpy(base_pin_name, "max7315_base");
441 strcpy(intr_pin_name, "max7315_int");
444 gpio_base = get_gpio_by_name(base_pin_name);
445 intr = get_gpio_by_name(intr_pin_name);
449 max7315->gpio_base = gpio_base;
451 i2c_info->irq = intr + MRST_IRQ_OFFSET;
452 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
455 max7315->irq_base = -1;
460 static void __init *emc1403_platform_data(void *info)
462 static short intr2nd_pdata;
463 struct i2c_board_info *i2c_info = info;
464 int intr = get_gpio_by_name("thermal_int");
465 int intr2nd = get_gpio_by_name("thermal_alert");
467 if (intr == -1 || intr2nd == -1)
470 i2c_info->irq = intr + MRST_IRQ_OFFSET;
471 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
473 return &intr2nd_pdata;
476 static void __init *lis331dl_platform_data(void *info)
478 static short intr2nd_pdata;
479 struct i2c_board_info *i2c_info = info;
480 int intr = get_gpio_by_name("accel_int");
481 int intr2nd = get_gpio_by_name("accel_2");
483 if (intr == -1 || intr2nd == -1)
486 i2c_info->irq = intr + MRST_IRQ_OFFSET;
487 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
489 return &intr2nd_pdata;
492 static const struct devs_id __initconst device_ids[] = {
493 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
494 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
495 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
496 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
497 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
498 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
502 #define MAX_IPCDEVS 24
503 static struct platform_device *ipc_devs[MAX_IPCDEVS];
504 static int ipc_next_dev;
506 #define MAX_SCU_SPI 24
507 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
508 static int spi_next_dev;
510 #define MAX_SCU_I2C 24
511 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
512 static int i2c_bus[MAX_SCU_I2C];
513 static int i2c_next_dev;
515 static void __init intel_scu_device_register(struct platform_device *pdev)
517 if(ipc_next_dev == MAX_IPCDEVS)
518 pr_err("too many SCU IPC devices");
520 ipc_devs[ipc_next_dev++] = pdev;
523 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
525 struct spi_board_info *new_dev;
527 if (spi_next_dev == MAX_SCU_SPI) {
528 pr_err("too many SCU SPI devices");
532 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
534 pr_err("failed to alloc mem for delayed spi dev %s\n",
538 memcpy(new_dev, sdev, sizeof(*sdev));
540 spi_devs[spi_next_dev++] = new_dev;
543 static void __init intel_scu_i2c_device_register(int bus,
544 struct i2c_board_info *idev)
546 struct i2c_board_info *new_dev;
548 if (i2c_next_dev == MAX_SCU_I2C) {
549 pr_err("too many SCU I2C devices");
553 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
555 pr_err("failed to alloc mem for delayed i2c dev %s\n",
559 memcpy(new_dev, idev, sizeof(*idev));
561 i2c_bus[i2c_next_dev] = bus;
562 i2c_devs[i2c_next_dev++] = new_dev;
565 /* Called by IPC driver */
566 void intel_scu_devices_create(void)
570 for (i = 0; i < ipc_next_dev; i++)
571 platform_device_add(ipc_devs[i]);
573 for (i = 0; i < spi_next_dev; i++)
574 spi_register_board_info(spi_devs[i], 1);
576 for (i = 0; i < i2c_next_dev; i++) {
577 struct i2c_adapter *adapter;
578 struct i2c_client *client;
580 adapter = i2c_get_adapter(i2c_bus[i]);
582 client = i2c_new_device(adapter, i2c_devs[i]);
584 pr_err("can't create i2c device %s\n",
587 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
590 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
592 /* Called by IPC driver */
593 void intel_scu_devices_destroy(void)
597 for (i = 0; i < ipc_next_dev; i++)
598 platform_device_del(ipc_devs[i]);
600 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
602 static void __init install_irq_resource(struct platform_device *pdev, int irq)
604 /* Single threaded */
605 static struct resource __initdata res = {
607 .flags = IORESOURCE_IRQ,
610 platform_device_add_resources(pdev, &res, 1);
613 static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
615 const struct devs_id *dev = device_ids;
618 while (dev->name[0]) {
619 if (dev->type == SFI_DEV_TYPE_IPC &&
620 !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
621 pdata = dev->get_platform_data(pdev);
626 pdev->dev.platform_data = pdata;
627 intel_scu_device_register(pdev);
630 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
632 const struct devs_id *dev = device_ids;
635 while (dev->name[0]) {
636 if (dev->type == SFI_DEV_TYPE_SPI &&
637 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
638 pdata = dev->get_platform_data(spi_info);
643 spi_info->platform_data = pdata;
645 intel_scu_spi_device_register(spi_info);
647 spi_register_board_info(spi_info, 1);
650 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
652 const struct devs_id *dev = device_ids;
655 while (dev->name[0]) {
656 if (dev->type == SFI_DEV_TYPE_I2C &&
657 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
658 pdata = dev->get_platform_data(i2c_info);
663 i2c_info->platform_data = pdata;
666 intel_scu_i2c_device_register(bus, i2c_info);
668 i2c_register_board_info(bus, i2c_info, 1);
672 static int __init sfi_parse_devs(struct sfi_table_header *table)
674 struct sfi_table_simple *sb;
675 struct sfi_device_table_entry *pentry;
676 struct spi_board_info spi_info;
677 struct i2c_board_info i2c_info;
678 struct platform_device *pdev;
681 struct io_apic_irq_attr irq_attr;
683 sb = (struct sfi_table_simple *)table;
684 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
685 pentry = (struct sfi_device_table_entry *)sb->pentry;
687 for (i = 0; i < num; i++, pentry++) {
688 if (pentry->irq != (u8)0xff) { /* native RTE case */
689 /* these SPI2 devices are not exposed to system as PCI
690 * devices, but they have separate RTE entry in IOAPIC
691 * so we have to enable them one by one here
693 ioapic = mp_find_ioapic(pentry->irq);
694 irq_attr.ioapic = ioapic;
695 irq_attr.ioapic_pin = pentry->irq;
696 irq_attr.trigger = 1;
697 irq_attr.polarity = 1;
698 io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
700 switch (pentry->type) {
701 case SFI_DEV_TYPE_IPC:
702 /* ID as IRQ is a hack that will go away */
703 pdev = platform_device_alloc(pentry->name, pentry->irq);
705 pr_err("out of memory for SFI platform device '%s'.\n",
709 install_irq_resource(pdev, pentry->irq);
710 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
711 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
712 sfi_handle_ipc_dev(pdev);
714 case SFI_DEV_TYPE_SPI:
715 memset(&spi_info, 0, sizeof(spi_info));
716 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
717 spi_info.irq = pentry->irq;
718 spi_info.bus_num = pentry->host_num;
719 spi_info.chip_select = pentry->addr;
720 spi_info.max_speed_hz = pentry->max_freq;
721 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
722 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
726 spi_info.max_speed_hz,
727 spi_info.chip_select);
728 sfi_handle_spi_dev(&spi_info);
730 case SFI_DEV_TYPE_I2C:
731 memset(&i2c_info, 0, sizeof(i2c_info));
732 bus = pentry->host_num;
733 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
734 i2c_info.irq = pentry->irq;
735 i2c_info.addr = pentry->addr;
736 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
737 "irq = 0x%2x, addr = 0x%x\n", i, bus,
741 sfi_handle_i2c_dev(bus, &i2c_info);
743 case SFI_DEV_TYPE_UART:
744 case SFI_DEV_TYPE_HSI:
752 static int __init mrst_platform_init(void)
754 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
755 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
758 arch_initcall(mrst_platform_init);
761 * we will search these buttons in SFI GPIO table (by name)
762 * and register them dynamically. Please add all possible
763 * buttons here, we will shrink them if no GPIO found.
765 static struct gpio_keys_button gpio_button[] = {
766 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
767 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
768 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
769 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
770 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
771 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
772 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
773 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
774 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
775 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
778 static struct gpio_keys_platform_data mrst_gpio_keys = {
779 .buttons = gpio_button,
781 .nbuttons = -1, /* will fill it after search */
784 static struct platform_device pb_device = {
788 .platform_data = &mrst_gpio_keys,
793 * Shrink the non-existent buttons, register the gpio button
794 * device if there is some
796 static int __init pb_keys_init(void)
798 struct gpio_keys_button *gb = gpio_button;
799 int i, num, good = 0;
801 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
802 for (i = 0; i < num; i++) {
803 gb[i].gpio = get_gpio_by_name(gb[i].desc);
804 if (gb[i].gpio == -1)
813 mrst_gpio_keys.nbuttons = good;
814 return platform_device_register(&pb_device);
818 late_initcall(pb_keys_init);