2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/slab.h>
21 #include <asm/pci_x86.h>
24 #define PREFIX "PCI: "
26 /* Indicate if the mmcfg resources have been placed into the resource table. */
27 static int __initdata pci_mmcfg_resources_inserted;
29 LIST_HEAD(pci_mmcfg_list);
31 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
34 release_resource(&cfg->res);
39 static __init void free_all_mmcfg(void)
41 struct pci_mmcfg_region *cfg, *tmp;
43 pci_mmcfg_arch_free();
44 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
45 pci_mmconfig_remove(cfg);
48 static __init void list_add_sorted(struct pci_mmcfg_region *new)
50 struct pci_mmcfg_region *cfg;
52 /* keep list sorted by segment and starting bus number */
53 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
54 if (cfg->segment > new->segment ||
55 (cfg->segment == new->segment &&
56 cfg->start_bus >= new->start_bus)) {
57 list_add_tail(&new->list, &cfg->list);
61 list_add_tail(&new->list, &pci_mmcfg_list);
64 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
67 struct pci_mmcfg_region *new;
74 new = kzalloc(sizeof(*new), GFP_KERNEL);
79 new->segment = segment;
80 new->start_bus = start;
85 num_buses = end - start + 1;
87 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
88 res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
89 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
90 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
91 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
92 res->name = new->name;
94 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
95 "%pR (base %#lx)\n", segment, start, end, &new->res,
96 (unsigned long) addr);
101 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
103 struct pci_mmcfg_region *cfg;
105 list_for_each_entry(cfg, &pci_mmcfg_list, list)
106 if (cfg->segment == segment &&
107 cfg->start_bus <= bus && bus <= cfg->end_bus)
113 static const char __init *pci_mmcfg_e7520(void)
116 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
119 if (win == 0x0000 || win == 0xf000)
122 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
125 return "Intel Corporation E7520 Memory Controller Hub";
128 static const char __init *pci_mmcfg_intel_945(void)
130 u32 pciexbar, mask = 0, len = 0;
132 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
139 switch ((pciexbar >> 1) & 3) {
156 /* Errata #2, things break when not aligned on a 256Mb boundary */
157 /* Can only happen in 64M/128M mode */
159 if ((pciexbar & mask) & 0x0fffffffU)
162 /* Don't hit the APIC registers and their friends */
163 if ((pciexbar & mask) >= 0xf0000000U)
166 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
169 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
172 static const char __init *pci_mmcfg_amd_fam10h(void)
174 u32 low, high, address;
177 unsigned segnbits = 0, busnbits, end_bus;
179 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
182 address = MSR_FAM10H_MMIO_CONF_BASE;
183 if (rdmsr_safe(address, &low, &high))
190 /* mmconfig is not enable */
191 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
194 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
196 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
197 FAM10H_MMIO_CONF_BUSRANGE_MASK;
200 * only handle bus 0 ?
207 segnbits = busnbits - 8;
211 end_bus = (1 << busnbits) - 1;
212 for (i = 0; i < (1 << segnbits); i++)
213 if (pci_mmconfig_add(i, 0, end_bus,
214 base + (1<<28) * i) == NULL) {
219 return "AMD Family 10h NB";
222 static bool __initdata mcp55_checked;
223 static const char __init *pci_mmcfg_nvidia_mcp55(void)
226 int mcp55_mmconf_found = 0;
228 static const u32 extcfg_regnum = 0x90;
229 static const u32 extcfg_regsize = 4;
230 static const u32 extcfg_enable_mask = 1<<31;
231 static const u32 extcfg_start_mask = 0xff<<16;
232 static const int extcfg_start_shift = 16;
233 static const u32 extcfg_size_mask = 0x3<<28;
234 static const int extcfg_size_shift = 28;
235 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
236 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
237 static const int extcfg_base_lshift = 25;
240 * do check if amd fam10h already took over
242 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
245 mcp55_checked = true;
246 for (bus = 0; bus < 256; bus++) {
250 int start, size_index, end;
252 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
254 device = (l >> 16) & 0xffff;
256 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
259 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
260 extcfg_regsize, &extcfg);
262 if (!(extcfg & extcfg_enable_mask))
265 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
266 base = extcfg & extcfg_base_mask[size_index];
267 /* base could > 4G */
268 base <<= extcfg_base_lshift;
269 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
270 end = start + extcfg_sizebus[size_index] - 1;
271 if (pci_mmconfig_add(0, start, end, base) == NULL)
273 mcp55_mmconf_found++;
276 if (!mcp55_mmconf_found)
279 return "nVidia MCP55";
282 struct pci_mmcfg_hostbridge_probe {
287 const char *(*probe)(void);
290 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
291 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
292 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
293 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
294 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
295 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
296 0x1200, pci_mmcfg_amd_fam10h },
297 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
298 0x1200, pci_mmcfg_amd_fam10h },
299 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
300 0x0369, pci_mmcfg_nvidia_mcp55 },
303 static void __init pci_mmcfg_check_end_bus_number(void)
305 struct pci_mmcfg_region *cfg, *cfgx;
308 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
309 if (cfg->end_bus < cfg->start_bus)
312 /* Don't access the list head ! */
313 if (cfg->list.next == &pci_mmcfg_list)
316 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
317 if (cfg->end_bus >= cfgx->start_bus)
318 cfg->end_bus = cfgx->start_bus - 1;
322 static int __init pci_mmcfg_check_hostbridge(void)
335 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
336 bus = pci_mmcfg_probes[i].bus;
337 devfn = pci_mmcfg_probes[i].devfn;
338 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
340 device = (l >> 16) & 0xffff;
343 if (pci_mmcfg_probes[i].vendor == vendor &&
344 pci_mmcfg_probes[i].device == device)
345 name = pci_mmcfg_probes[i].probe();
348 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
352 /* some end_bus_number is crazy, fix it */
353 pci_mmcfg_check_end_bus_number();
355 return !list_empty(&pci_mmcfg_list);
358 static void __init pci_mmcfg_insert_resources(void)
360 struct pci_mmcfg_region *cfg;
362 list_for_each_entry(cfg, &pci_mmcfg_list, list)
363 insert_resource(&iomem_resource, &cfg->res);
365 /* Mark that the resources have been inserted. */
366 pci_mmcfg_resources_inserted = 1;
369 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
372 struct resource *mcfg_res = data;
373 struct acpi_resource_address64 address;
376 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
377 struct acpi_resource_fixed_memory32 *fixmem32 =
378 &res->data.fixed_memory32;
381 if ((mcfg_res->start >= fixmem32->address) &&
382 (mcfg_res->end < (fixmem32->address +
383 fixmem32->address_length))) {
385 return AE_CTRL_TERMINATE;
388 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
389 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
392 status = acpi_resource_to_address64(res, &address);
393 if (ACPI_FAILURE(status) ||
394 (address.address_length <= 0) ||
395 (address.resource_type != ACPI_MEMORY_RANGE))
398 if ((mcfg_res->start >= address.minimum) &&
399 (mcfg_res->end < (address.minimum + address.address_length))) {
401 return AE_CTRL_TERMINATE;
406 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
407 void *context, void **rv)
409 struct resource *mcfg_res = context;
411 acpi_walk_resources(handle, METHOD_NAME__CRS,
412 check_mcfg_resource, context);
415 return AE_CTRL_TERMINATE;
420 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
422 struct resource mcfg_res;
424 mcfg_res.start = start;
425 mcfg_res.end = end - 1;
428 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
431 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
434 return mcfg_res.flags;
437 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
439 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
440 struct pci_mmcfg_region *cfg, int with_e820)
442 u64 addr = cfg->res.start;
443 u64 size = resource_size(&cfg->res);
445 int valid = 0, num_buses;
447 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
449 if (size < (16UL<<20))
453 if (size >= (16UL<<20) || size == old_size) {
454 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
456 with_e820 ? "E820" : "ACPI motherboard resources");
459 if (old_size != size) {
461 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
462 num_buses = cfg->end_bus - cfg->start_bus + 1;
463 cfg->res.end = cfg->res.start +
464 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
465 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
466 "PCI MMCONFIG %04x [bus %02x-%02x]",
467 cfg->segment, cfg->start_bus, cfg->end_bus);
468 printk(KERN_INFO PREFIX
469 "MMCONFIG for %04x [bus%02x-%02x] "
470 "at %pR (base %#lx) (size reduced!)\n",
471 cfg->segment, cfg->start_bus, cfg->end_bus,
472 &cfg->res, (unsigned long) cfg->address);
479 static void __init pci_mmcfg_reject_broken(int early)
481 struct pci_mmcfg_region *cfg;
483 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
486 if (!early && !acpi_disabled) {
487 valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
492 printk(KERN_ERR FW_BUG PREFIX
493 "MMCONFIG at %pR not reserved in "
494 "ACPI motherboard resources\n",
498 /* Don't try to do this check unless configuration
499 type 1 is available. how about type 2 ?*/
501 valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
510 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
514 static int __initdata known_bridge;
516 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
517 struct acpi_mcfg_allocation *cfg)
521 if (cfg->address < 0xFFFFFFFF)
524 if (!strcmp(mcfg->header.oem_id, "SGI"))
527 if (mcfg->header.revision >= 1) {
528 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
533 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
534 "is above 4GB, ignored\n", cfg->pci_segment,
535 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
539 static int __init pci_parse_mcfg(struct acpi_table_header *header)
541 struct acpi_table_mcfg *mcfg;
542 struct acpi_mcfg_allocation *cfg_table, *cfg;
549 mcfg = (struct acpi_table_mcfg *)header;
551 /* how many config structures do we have */
554 i = header->length - sizeof(struct acpi_table_mcfg);
555 while (i >= sizeof(struct acpi_mcfg_allocation)) {
557 i -= sizeof(struct acpi_mcfg_allocation);
560 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
564 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
565 for (i = 0; i < entries; i++) {
567 if (acpi_mcfg_check_entry(mcfg, cfg)) {
572 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
573 cfg->end_bus_number, cfg->address) == NULL) {
574 printk(KERN_WARNING PREFIX
575 "no memory for MCFG entries\n");
584 static void __init __pci_mmcfg_init(int early)
586 /* MMCONFIG disabled */
587 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
590 /* MMCONFIG already enabled */
591 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
594 /* for late to exit */
599 if (pci_mmcfg_check_hostbridge())
604 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
606 pci_mmcfg_reject_broken(early);
608 if (list_empty(&pci_mmcfg_list))
611 if (pci_mmcfg_arch_init())
612 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
615 * Signal not to attempt to insert mmcfg resources because
616 * the architecture mmcfg setup could not initialize.
618 pci_mmcfg_resources_inserted = 1;
622 void __init pci_mmcfg_early_init(void)
627 void __init pci_mmcfg_late_init(void)
632 static int __init pci_mmcfg_late_insert_resources(void)
635 * If resources are already inserted or we are not using MMCONFIG,
636 * don't insert the resources.
638 if ((pci_mmcfg_resources_inserted == 1) ||
639 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
640 list_empty(&pci_mmcfg_list))
644 * Attempt to insert the mmcfg resources but not with the busy flag
645 * marked so it won't cause request errors when __request_region is
648 pci_mmcfg_insert_resources();
654 * Perform MMCONFIG resource insertion after PCI initialization to allow for
655 * misprogrammed MCFG tables that state larger sizes but actually conflict
656 * with other system resources.
658 late_initcall(pci_mmcfg_late_insert_resources);