1 #include <linux/init.h>
3 #include <linux/topology.h>
5 #include <linux/range.h>
7 #include <asm/amd_nb.h>
8 #include <asm/pci_x86.h>
10 #include <asm/pci-direct.h>
15 * This discovers the pcibus <-> node mapping on AMD K8.
16 * also get peer root bus resource for io,mmio
19 struct pci_hostbridge_probe {
26 static struct pci_hostbridge_probe pci_probes[] __initdata = {
27 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
28 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
29 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
36 * early_fill_mp_bus_to_node()
37 * called before pcibios_scan_root and pci_scan_bus
38 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
39 * Registers found in the K8 northbridge
41 static int __init early_fill_mp_bus_info(void)
51 struct pci_root_info *info;
56 struct range range[RANGE_NUM];
60 struct resource fam10h_mmconf_res, *fam10h_mmconf;
61 u64 fam10h_mmconf_start;
62 u64 fam10h_mmconf_end;
64 if (!early_pci_allowed())
68 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
73 bus = pci_probes[i].bus;
74 slot = pci_probes[i].slot;
75 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
78 device = (id>>16) & 0xffff;
79 if (pci_probes[i].vendor == vendor &&
80 pci_probes[i].device == device) {
90 for (i = 0; i < 4; i++) {
93 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
95 /* Check if that register is enabled for bus range */
99 min_bus = (reg >> 16) & 0xff;
100 max_bus = (reg >> 24) & 0xff;
101 node = (reg >> 4) & 0x07;
103 for (j = min_bus; j <= max_bus; j++)
104 set_mp_bus_to_node(j, node);
106 link = (reg >> 8) & 0x03;
108 info = &pci_root_info[pci_root_num];
109 info->bus_min = min_bus;
110 info->bus_max = max_bus;
113 sprintf(info->name, "PCI Bus #%02x", min_bus);
117 /* get the default node and link for left over res */
118 reg = read_pci_config(bus, slot, 0, 0x60);
119 def_node = (reg >> 8) & 0x07;
120 reg = read_pci_config(bus, slot, 0, 0x64);
121 def_link = (reg >> 8) & 0x03;
123 memset(range, 0, sizeof(range));
124 add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
125 /* io port resource */
126 for (i = 0; i < 4; i++) {
127 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
131 start = reg & 0xfff000;
132 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
134 link = (reg >> 4) & 0x03;
135 end = (reg & 0xfff000) | 0xfff;
137 /* find the position */
138 for (j = 0; j < pci_root_num; j++) {
139 info = &pci_root_info[j];
140 if (info->node == node && info->link == link)
143 if (j == pci_root_num)
144 continue; /* not found */
146 info = &pci_root_info[j];
147 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
148 node, link, start, end);
150 /* kernel only handle 16 bit only */
153 update_res(info, start, end, IORESOURCE_IO, 1);
154 subtract_range(range, RANGE_NUM, start, end + 1);
156 /* add left over io port range to def node/link, [0, 0xffff] */
157 /* find the position */
158 for (j = 0; j < pci_root_num; j++) {
159 info = &pci_root_info[j];
160 if (info->node == def_node && info->link == def_link)
163 if (j < pci_root_num) {
164 info = &pci_root_info[j];
165 for (i = 0; i < RANGE_NUM; i++) {
169 update_res(info, range[i].start, range[i].end - 1,
174 memset(range, 0, sizeof(range));
175 /* 0xfd00000000-0xffffffffff for HT */
176 end = cap_resource((0xfdULL<<32) - 1);
178 add_range(range, RANGE_NUM, 0, 0, end);
180 /* need to take out [0, TOM) for RAM*/
181 address = MSR_K8_TOP_MEM1;
182 rdmsrl(address, val);
183 end = (val & 0xffffff800000ULL);
184 printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
185 if (end < (1ULL<<32))
186 subtract_range(range, RANGE_NUM, 0, end);
189 fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
190 /* need to take out mmconf range */
192 printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
193 fam10h_mmconf_start = fam10h_mmconf->start;
194 fam10h_mmconf_end = fam10h_mmconf->end;
195 subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
196 fam10h_mmconf_end + 1);
198 fam10h_mmconf_start = 0;
199 fam10h_mmconf_end = 0;
203 for (i = 0; i < 8; i++) {
204 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
208 start = reg & 0xffffff00; /* 39:16 on 31:8*/
210 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
212 link = (reg >> 4) & 0x03;
213 end = (reg & 0xffffff00);
217 /* find the position */
218 for (j = 0; j < pci_root_num; j++) {
219 info = &pci_root_info[j];
220 if (info->node == node && info->link == link)
223 if (j == pci_root_num)
224 continue; /* not found */
226 info = &pci_root_info[j];
228 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
229 node, link, start, end);
231 * some sick allocation would have range overlap with fam10h
232 * mmconf range, so need to update start and end.
234 if (fam10h_mmconf_end) {
237 if (start >= fam10h_mmconf_start &&
238 start <= fam10h_mmconf_end) {
239 start = fam10h_mmconf_end + 1;
243 if (end >= fam10h_mmconf_start &&
244 end <= fam10h_mmconf_end) {
245 end = fam10h_mmconf_start - 1;
249 if (start < fam10h_mmconf_start &&
250 end > fam10h_mmconf_end) {
252 endx = fam10h_mmconf_start - 1;
253 update_res(info, start, endx, IORESOURCE_MEM, 0);
254 subtract_range(range, RANGE_NUM, start,
256 printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
257 start = fam10h_mmconf_end + 1;
262 printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
264 printk(KERN_CONT "%s\n", endx?"":" ==> none");
270 update_res(info, cap_resource(start), cap_resource(end),
272 subtract_range(range, RANGE_NUM, start, end + 1);
273 printk(KERN_CONT "\n");
276 /* need to take out [4G, TOM2) for RAM*/
278 address = MSR_K8_SYSCFG;
279 rdmsrl(address, val);
280 /* TOP_MEM2 is enabled? */
283 address = MSR_K8_TOP_MEM2;
284 rdmsrl(address, val);
285 end = (val & 0xffffff800000ULL);
286 printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
287 subtract_range(range, RANGE_NUM, 1ULL<<32, end);
291 * add left over mmio range to def node/link ?
292 * that is tricky, just record range in from start_min to 4G
294 for (j = 0; j < pci_root_num; j++) {
295 info = &pci_root_info[j];
296 if (info->node == def_node && info->link == def_link)
299 if (j < pci_root_num) {
300 info = &pci_root_info[j];
302 for (i = 0; i < RANGE_NUM; i++) {
306 update_res(info, cap_resource(range[i].start),
307 cap_resource(range[i].end - 1),
312 for (i = 0; i < pci_root_num; i++) {
316 info = &pci_root_info[i];
317 res_num = info->res_num;
318 busnum = info->bus_min;
319 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
320 info->bus_min, info->bus_max, info->node, info->link);
321 for (j = 0; j < res_num; j++) {
323 printk(KERN_DEBUG "bus: %02x index %x %pR\n",
331 #define ENABLE_CF8_EXT_CFG (1ULL << 46)
333 static void __cpuinit enable_pci_io_ecs(void *unused)
336 rdmsrl(MSR_AMD64_NB_CFG, reg);
337 if (!(reg & ENABLE_CF8_EXT_CFG)) {
338 reg |= ENABLE_CF8_EXT_CFG;
339 wrmsrl(MSR_AMD64_NB_CFG, reg);
343 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
344 unsigned long action, void *hcpu)
346 int cpu = (long)hcpu;
349 case CPU_ONLINE_FROZEN:
350 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
358 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
359 .notifier_call = amd_cpu_notify,
362 static void __init pci_enable_pci_io_ecs(void)
367 for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
368 u8 bus = amd_nb_bus_dev_ranges[i].bus;
369 u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
370 u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
372 for (; slot < limit; ++slot) {
373 u32 val = read_pci_config(bus, slot, 3, 0);
375 if (!early_is_amd_nb(val))
378 val = read_pci_config(bus, slot, 3, 0x8c);
379 if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
380 val |= ENABLE_CF8_EXT_CFG >> 32;
381 write_pci_config(bus, slot, 3, 0x8c, val);
389 static int __init pci_io_ecs_init(void)
393 /* assume all cpus from fam10h have IO ECS */
394 if (boot_cpu_data.x86 < 0x10)
397 /* Try the PCI method first. */
398 if (early_pci_allowed())
399 pci_enable_pci_io_ecs();
401 register_cpu_notifier(&amd_cpu_notifier);
402 for_each_online_cpu(cpu)
403 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
405 pci_probe |= PCI_HAS_IO_ECS;
410 static int __init amd_postcore_init(void)
412 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
415 early_fill_mp_bus_info();
421 postcore_initcall(amd_postcore_init);